Trac reminder: list of new ticket(s)

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Regarding: Error Unzipping coreboot + libpayload + coreinfo Ready-made QEMU images

Dear Coreboot Folks

http://www.coreboot.org/QEMU

in this site, there are some readymade coreboot payloads , which I thought of using it to see the output.
But when I tried to unzip the file Qemu_coreboot_coreinfo.zip, it throws an error.

I am doing this because i was not able to compile libpayload, as libpayload makes use of coreinfo, I cannot
use coreinfo as well.

If you guys can upload a good working image of coreboot+libpayoad+coreinfo, that would be great!!

Regards
Pradish

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Fwd: Re: Can the LiPPERT Cool RoadRunner-LX image be used for Gene 5315 Rev.B?

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How do I set GEODE graphics and video?

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ASRock E350M1: GRUB payload does not create AHCI device

Dear coreboot folks, dear Vladimir,

although this is a GRUB problem, I am posting this to the coreboot list
as it is in the GRUB payload and I am not subscribed to the GRUB list.

Currently using GRUB revision 4778 as a payload [1], loading the module
`ahci` I see the following errors (formatted serial output, “garbled”
one at the end) on the AMD SB800 based ASRock E350M1 [2].

        grub> set debug=ahci,ata
        grub> insmod ahci
        disk/ahci.c:291: Requesting AHCI ownership
        disk/ahci.c:294: Waiting for BIOS to give up ownership
        disk/ahci.c:305: AHCI ownership obtained
        disk/ahci.c:311: AHCI is in compat mode. Switching
        disk/ahci.c:357: 6 AHCI ports
        disk/ahci.c:367: status 0:123
        disk/ahci.c:184: found device ahci0 (port 0)
        disk/ahci.c:225: couldn't start CR
        grub> insmod ata
        grub> insmod mdraid
        grub> insmod mdraid09
        grub> ls
        (memdisk)

SeaBIOS has no problems finding the attached ATA drive.

If more information is needed, please tell me what and how I can get it,
and I will try to provide it.

Thanks,

Paul

[1] http://www.coreboot.org/GRUB2
[2] http://www.coreboot.org/ASRock_E350M1

grub> ins   set debug=ahci,ata
grub> insom  mot d ahci
disk/ahci.c:291: Requesting AHCI ownership
disk/ahci.c:294: Waiting for BIOS to give up ownership
disk/ahci.c:305: AHCI ownership obtained
disk/ahci.c:311: AHCI is in compat mode. Switching
disk/ahci.c:357: 6 AHCI ports
disk/ahci.c:367: status 0:123
disk/ahci.c:184: found device ahci0 (port 0)
disk/ahci.c:225: couldn't start CR
grub> insmod ata
grub> insomd   mod mdraid
grub> insmod mdraid09
grub> ls
(memdisk)

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Libpayload compilation error: conflicting types for ‘size_t’

Dear coreboot folks,

i am still not able to compile Libpayload, i downloaded the latest
version of it using the following command

$ git clone http://review.coreboot.org/p/coreboot
$ cd payloads/libpayload
$ make menuconfig
$ make install

i have not used git as i have always worked on windows, this is new to me.

bpci/libpci.libpci.o
In file included from include/libpayload.h:54:0,
                 from libpci/libpci.c:30:
include/x86/arch/types.h:56:23: error: conflicting types for ‘size_t’
/usr/lib/gcc/i686-linux-gnu/4.6.1/include/stddef.h:212:23: note:
previous declaration of ‘size_t’ was here
make: *** [build/libpci/libpci.libpci.o] Error 1

Note: I have tried my level best to send this mail in plain text.

regards
Pradish

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Ivy Bridge desktop support

Dear coreboot folks,

I'm looking forward to write a port for my Ivy Bridge desktop system based
on this board: Intel DH77EB (codenamed Eb Lake, [1]). It comes with the H77
platform controller hub (PCH) and a Winbond W83677HG super I/O chip (build
by Nuvoton as NCT6775F, [2]). I'm using it with a Core i3-3225 processor [3].
I've got the datasheet for the super I/O, so writing support for it should
be no problem.

Is there any doubt that the current code for Ivy Bridge and the Panther Point
PCH works out of the box on a desktop system? I see that at least I have to
add some device IDs.

Regarding the PCH code, is SOUTHBRIDGE_INTEL_C216 the general option for
Panther Point? or is it really C216 specific?

Then there are the binary blobs. I'm not quite sure, which are necessary:
`ifdtool -x` gives me four regions out of the original vendor firmware:
  flashregion_0_flashdescriptor.bin,
  flashregion_1_bios.bin,
  flashregion_2_intel_me.bin, and
  flashregion_3_gbe.bin.
Obviously, the second one will be replaced with coreboot. I guess, I'll need
to use or replace the flashdescriptor.bin and intel_me.bin? What about the
last one `flashregion_3_gbe.bin`? do I need it as well? I haven't seen an
equivalent in the 3rdparty directories for supported boards. Surprisingly, I
didn't find a VGA BIOS in there. Well, I might not need it, anyhow. The box
should be booted before any display device is up :)

Regards,
Nico

[1] http://ark.intel.com/products/59505/Intel-Desktop-Board-DH77EB

[2] http://www.nuvoton.com/NuvotonMOSS/Community/ProductInfo.aspx?tp_GUID=746a4e20-12bc-4170-872b-38ecc32e6dbc

[3] http://ark.intel.com/products/65692/Intel-Core-i3-3225-Processor-3M-Cache-3_30-GHz

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Build system: Where do I add `-E` switch for GCC to view preprocessor output?

Dear coreboot folks,

I was unsuccessful in finding the correct place to add the `-E` switch
to `gcc` so I can see the preprocessor output.

Adding it to `CFLAGS` in `Makefile` and `Makefile.inc` resulted in a
non-working build. Changing `.xcompile` is not possible as it gets
rewritten when doing `make`.

Thanks,

Paul

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DSDT: New warnings after adding _OSC method

Dear coreboot folks,

the patches adding the _OSC method to the DSDT, like [1][2][3],
introduce the following ACPI warnings [4][5], which went unnoticed by
the reviewers, myself included.

            IASL       coreboot-builds/amd_persimmon/mainboard/amd/persimmon/dsdt.ramstage.o
            CC         mainboard/amd/persimmon/get_bus_conf.ramstage.o

        Intel ACPI Component Architecture
        ASL Optimizing Compiler version 20100528 [Oct 15 2010]
        Copyright (c) 2000 - 2010 Intel Corporation
        Supports ACPI Specification Revision 4.0a

        dsdt.ramstage.asl  1143:    Method(_OSC,4)
        Warning  1088 -                       ^ Not all control paths return a value (_OSC)

        dsdt.ramstage.asl  1143:    Method(_OSC,4)
        Warning  1081 -                       ^ Reserved method must return a value (Buffer required for _OSC)

        ASL Input:  dsdt.ramstage.asl - 1724 lines, 34917 bytes, 889 keywords
        AML Output: dsdt.ramstage.aml - 10470 bytes, 409 named objects, 480 executable opcodes

        Compilation complete. 0 Errors, 2 Warnings, 0 Remarks, 494 Optimizations

It should be as simple as adding the following as commented in
[1 (Mar 14 12:23 AM)] already.

        } Else {
            Or(CDW1,4,CDW1)
            // Unrecognized UUID
            Return(Arg3)
        }

I am not submitting a patch, as the Sage folks are currently doing some
unification work, I do not want to interfere with.

Thanks,

Paul

[1] http://review.coreboot.org/#/c/2684/
[2] http://review.coreboot.org/#/c/2739/
[3] http://review.coreboot.org/#/c/2714/
[4] http://qa.coreboot.org/job/coreboot-gerrit/5591/testReport/(root)/board/i386_amd_persimmon/?
[5] http://qa.coreboot.org/job/coreboot-gerrit/5591/testReport/(root)/board/i386_intel_eagleheights/?
(logs will not be archived forever, so URL might be invalid)

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ASRock E350M1: Linux reports `piix4_smbus 0000:00:14.0: SMBus base address index region 0xcd6 already in use!`

Dear coreboot folks,

since [1]

        commit df729d7778a7e5878fac5545883f68e42372456a
        Author: Jens Rottmann <JRottmann <at> LiPPERTembedded.de>
        Date:   Tue Feb 19 14:46:31 2013 +0100

            AMD Fam14 boards: dimmSpd.c: Set `iobase` to `SMBUS0_BASE_ADDRESS` instead of `0xB00`

which I expanded to the ASRock E350M1, overlooking the new error
message, Linux complains about an already used base address index
region.

        calling  i2c_piix4_init+0x0/0x1000 [i2c_piix4]  <at>  559
        piix4_smbus 0000:00:14.0: SMBus base address index region 0xcd6 already in use!
        piix4_smbus: probe of 0000:00:14.0 failed with error -16

The address 0xb00 was used before and this should not have been changed
with the patch above. But it did. I looked through the code but could
not find where 0xcd6 comes from. Any pointers would be very much
appreciated.

Thanks,

Paul

[1] http://review.coreboot.org/2453

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libpayload: Missing inclusion of `libpayload-config.h`

Dear coreboot folks,

using latest master

        commit 3cc0d1eb3f611cb7bf0e45d8ccdb0c84f54f54dc
        Author: David Hendricks <dhendrix <at> chromium.org>
        Date:   Tue Mar 26 16:28:21 2013 -0700

            exynos5250: assign RAM resources in cpu_init()

        […]

            Reviewed-on: http://review.coreboot.org/2923

it looks like libpayload’s PDCurses backend is not including
`libpayload-config.h` in some files so the configuration is ignored,
right? I noticed this due to the following warning.

        /src/coreboot/payloads/libpayload(master) $ make clean
        /src/coreboot/payloads/libpayload(master) $ make
        […]
            CC         curses/pdcurses-backend/pdcscrn.libcurses.o
        curses/pdcurses-backend/pdcscrn.c: In function 'PDC_scr_open':
        curses/pdcurses-backend/pdcscrn.c:75:5: warning: "CONFIG_SPEAKER" is not defined [-Wundef]
        […]

No warnings are printed for the other files, because `#ifdef` is used
there. But these macros will never be defined, when
`libpayload-config.h` is not included, if I am not mistaken.

So is the solution to just include `config.h` or `libpayload-config.h`
everywhere?

        /src/coreboot/payloads/libpayload(master) $ grep -R
        CONFIG_SPEA .
        ./configs/defconfig:CONFIG_SPEAKER=y
        ./curses/pdcurses-backend/pdcscrn.c:#ifdef CONFIG_SPEAKER
        ./curses/pdcurses-backend/pdcutil.c:#ifdef CONFIG_SPEAKER
        ./curses/tinycurses.c:#ifdef CONFIG_SPEAKER
        ./drivers/Makefile.inc:libc-$(CONFIG_SPEAKER) += speaker.c
        ./build/config.h:#define CONFIG_SPEAKER 1
        ./build/auto.conf:CONFIG_SPEAKER=y
        ./build/libpayload-config.h:#define CONFIG_SPEAKER 1
        ./.config:CONFIG_SPEAKER=y
        ./tests/libpayload-config.h:#define CONFIG_SPEAKER 1

If you tell me the preferred solution, I am going to submit a patch.

Thanks,

Paul

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