Kyösti Mälkki | 1 Aug 08:32 2012

New patch to review for coreboot: 3dc036b Remove uma_memory_base from build if no GFXUMA

Kyösti Mälkki (kyosti.malkki <at> gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1385

-gerrit

commit 3dc036bd59e0534a41d6c1f81d0c2f3a4b0ab6bf
Author: Kyösti Mälkki <kyosti.malkki <at> gmail.com>
Date:   Wed Aug 1 08:05:22 2012 +0300

    Remove uma_memory_base from build if no GFXUMA

    This patch validates the previous "drop uma_memory_base" patches;
    there are no more references to uma_memory_base when GFXUMA is not
    selected.

    Change-Id: I735b5e765b0c5cb4af1b4a7470cfe1af2bda7d38
    Signed-off-by: Kyösti Mälkki <kyosti.malkki <at> gmail.com>
---
 src/devices/device.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/devices/device.c b/src/devices/device.c
index 92a4447..6b1902d 100644
--- a/src/devices/device.c
+++ b/src/devices/device.c
 <at>  <at>  -54,10 +54,11  <at>  <at>  struct resource *free_resources = NULL;

 DECLARE_SPIN_LOCK(dev_lock)

-
+#if CONFIG_GFXUMA
(Continue reading)

Kyösti Mälkki | 1 Aug 09:42 2012

New patch to review for coreboot: c539aeb Add infrastructure to distribute MSRs across CPUs on init

Kyösti Mälkki (kyosti.malkki <at> gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1386

-gerrit

commit c539aeba4a570f209667255f1fd68c48bc46e12a
Author: Kyösti Mälkki <kyosti.malkki <at> gmail.com>
Date:   Tue Jul 31 20:52:47 2012 +0300

    Add infrastructure to distribute MSRs across CPUs on init

    Some MSRs need to be replicated from one CPU to another.
    As the first step handle TOP_MEM and TOP_MEM2 for AMD CPUs.

    There is no need to regenerate MTRR setup from the registered memory
    resources separately for each CPU, doing it once and saving a copy
    in a table should do it. Also writing of MTRR MSRs to CPUs should be
    synchronized, reading from a table should simplify that process.

    The created table can be moved to cbmem to use it on S2/S3 resumes.

    Change-Id: I9bf0c47f825f7174b5108a32fba56e9fec5bb62b
    Signed-off-by: Kyösti Mälkki <kyosti.malkki <at> gmail.com>
---
 src/cpu/x86/mtrr/Makefile.inc |    1 +
 src/cpu/x86/mtrr/msr.c        |   51 +++++++++++++++++++++++++++++++++++++++++
 src/include/cpu/x86/msr.h     |    7 +++++
 3 files changed, 59 insertions(+), 0 deletions(-)

diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc
index cecb826..65a53d3 100644
(Continue reading)

Zheng Bao | 1 Aug 10:39 2012

Patch set updated for coreboot: 2785a0c AMD F15tn northbridge: Remove the misleading 0x100 from the limitk.

Zheng Bao (zheng.bao <at> amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1265

-gerrit

commit 2785a0c0c64b140a1e0a57ca060b7b4d193a91e5
Author: zbao <fishbaozi <at> gmail.com>
Date:   Wed Aug 1 18:23:49 2012 +0800

    AMD F15tn northbridge: Remove the misleading 0x100 from the limitk.

    I dont known if missed something, but why an extra 0x100 was added to limit?
    My board would get the wrong memory table entry 7f000000-7fffffff as RAM, which
    is higher than TOM.
    coreboot memory table:
    0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
    1. 0000000000001000-000000000009ffff: RAM
    2. 00000000000c0000-000000005e13efff: RAM
    3. 000000005e13f000-000000005effffff: CONFIGURATION TABLES
    4. 000000005f000000-000000007effffff: RESERVED
    5. 000000007f000000-000000007fffffff: RAM
    6. 00000000a0000000-00000000afffffff: RESERVED

    Ronald G. Minnich:
     I think someone who wrote the code was trying to round up the
    next 0x100 boundary and did it incorrectly.
    Here is code that would do it correctly:
    limitk = ((resource_t)((d.mask + 0x00000ff) & 0x1fffff00)) << 9 ;

    Zheng:
     Plus 0xFF is correct, but the d.mask take bit 0 as enable it.
(Continue reading)

Zheng Bao | 1 Aug 10:46 2012

Patch set updated for coreboot: 117b2d4 AMD Thatcher Board based on trinity

Zheng Bao (zheng.bao <at> amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1382

-gerrit

commit 117b2d40a13d75355a14ac25f828afd2b57f043c
Author: zbao <fishbaozi <at> gmail.com>
Date:   Wed Aug 1 18:31:15 2012 +0800

    AMD Thatcher Board based on trinity
    
    Thatcher features: Family 15 trinity FP2. Hudson.
    close to Parmer.
    This board and parmer both need to revert the change
    http://review.coreboot.org/#/c/1359/, and add thatcher's own
    chip.h,otherwise the mainboard_enable can not be called.
    
    Change-Id: I54e1cfca845fbcea1d3aad5eff08d760d0d215c9
    Signed-off-by: Zheng Bao <zheng.bao <at> amd.com>
    Signed-off-by: zbao <fishbaozi <at> gmail.com>
---
 src/mainboard/amd/Kconfig                          |    3 +
 src/mainboard/amd/thatcher/BiosCallOuts.c          |  737 ++++++++++
 src/mainboard/amd/thatcher/BiosCallOuts.h          |   82 ++
 src/mainboard/amd/thatcher/Kconfig                 |  115 ++
 src/mainboard/amd/thatcher/Makefile.inc            |   33 +
 src/mainboard/amd/thatcher/OptionsIds.h            |   67 +
 src/mainboard/amd/thatcher/PlatformGnbPcie.c       |  206 +++
 .../amd/thatcher/PlatformGnbPcieComplex.h          |   72 +
 src/mainboard/amd/thatcher/acpi/AmdImc.asl         |   95 ++
 src/mainboard/amd/thatcher/acpi/cpstate.asl        |  115 ++
(Continue reading)

gerrit | 1 Aug 10:57 2012

Patch merged into coreboot/master: 15fa0ed Intel Sandybridge: add reserved memory as resources

the following patch was just integrated into master:
commit 15fa0edd877b491a807340d018369f303aee0722
Author: Kyösti Mälkki <kyosti.malkki <at> gmail.com>
Date:   Thu Jul 26 23:51:20 2012 +0300

    Intel Sandybridge: add reserved memory as resources

    Reserved memory resources will get removed from memory table at
    the end of write_coreboot_table(),

    Change-Id: I02711b4be4f25054bd3361295d8d4dc996b2eb3e
    Signed-off-by: Kyösti Mälkki <kyosti.malkki <at> gmail.com>

Build-Tested: build bot (Jenkins) at Sun Jul 29 08:17:27 2012, giving +1
Reviewed-By: Anton Kochkov <anton.kochkov <at> gmail.com> at Wed Aug  1 10:57:17 2012, giving +2
See http://review.coreboot.org/1372 for details.

-gerrit

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gerrit | 1 Aug 10:58 2012

Patch merged into coreboot/master: b0ab0b5 Intel Sandybridge and UMA: use mmio_resource()

the following patch was just integrated into master:
commit b0ab0b5948d3452f12b071f6105add111a5c9d03
Author: Kyösti Mälkki <kyosti.malkki <at> gmail.com>
Date:   Fri Jul 27 13:12:03 2012 +0300

    Intel Sandybridge and UMA: use mmio_resource()

    With SandyBridge northbridge code, uma_memory_size was reset to
    zero before variable MTRRs were set. This means MTRR setup routine
    did not previously create a un-cacheable hole for uma.

    Keep the behaviour that way, mmio_resource() has a prerequisuite that
    the new region does not overlap with any cacheable ram_resource().

    The result is not optimal setup in the number of used MTRRs, but
    continue with this approach until MTRR algorithm is improved.

    Change-Id: I63c8df19ad6b6350d46a3eca3055abf684b8b114
    Signed-off-by: Kyösti Mälkki <kyosti.malkki <at> gmail.com>

Build-Tested: build bot (Jenkins) at Sun Jul 29 08:02:08 2012, giving +1
Reviewed-By: Anton Kochkov <anton.kochkov <at> gmail.com> at Wed Aug  1 10:58:44 2012, giving +2
See http://review.coreboot.org/1373 for details.

-gerrit

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gerrit | 1 Aug 11:53 2012

Patch merged into coreboot/master: b161e56 Intel and GFXUMA: drop redundant use of lb_add_memory_range()

the following patch was just integrated into master:
commit b161e5614ce6660b14a10d39d9a673715b88160c
Author: Kyösti Mälkki <kyosti.malkki <at> gmail.com>
Date:   Wed Jul 18 14:38:54 2012 +0300

    Intel and GFXUMA: drop redundant use of lb_add_memory_range()

    Use of uma_resource() in northbridge code created a memory
    resource marked as reserved. Such resources are removed
    from system memory in write_coreboot_table().

    Change-Id: I14bfd560140d8d30ec156562f23072bfae747bde
    Signed-off-by: Kyösti Mälkki <kyosti.malkki <at> gmail.com>

Build-Tested: build bot (Jenkins) at Fri Jul 27 15:20:11 2012, giving +1
Reviewed-By: Anton Kochkov <anton.kochkov <at> gmail.com> at Wed Aug  1 11:52:53 2012, giving +2
See http://review.coreboot.org/1238 for details.

-gerrit

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gerrit | 1 Aug 11:54 2012

Patch merged into coreboot/master: c33f6d0 AMD and GFXUMA : drop redundant use of lb_add_memory_range()

the following patch was just integrated into master:
commit c33f6d04c9b8c67891002f26038933f00ba8c2fd
Author: Kyösti Mälkki <kyosti.malkki <at> gmail.com>
Date:   Sun Jul 29 10:34:59 2012 +0300

    AMD and GFXUMA : drop redundant use of lb_add_memory_range()

    See commit 505414a6cfb2aeef455b5144e4b96fc27f19eb39.

    Change-Id: Icc04af9726ae54141581aecc84c40e8aac54591d
    Signed-off-by: Kyösti Mälkki <kyosti.malkki <at> gmail.com>

Build-Tested: build bot (Jenkins) at Sun Jul 29 10:22:58 2012, giving +1
Reviewed-By: Anton Kochkov <anton.kochkov <at> gmail.com> at Wed Aug  1 11:54:09 2012, giving +2
See http://review.coreboot.org/1378 for details.

-gerrit

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Kyösti Mälkki | 1 Aug 15:43 2012

New patch to review for coreboot: a7e36bf AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution

Kyösti Mälkki (kyosti.malkki <at> gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1387

-gerrit

commit a7e36bf088ae53eb57025c6b8e0f85dfd5503a71
Author: Kyösti Mälkki <kyosti.malkki <at> gmail.com>
Date:   Tue Jul 31 20:51:48 2012 +0300

    AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution

    Take a copy of BSP CPU's TOP_MEM and TOP_MEM2 MSRs to be distributed
    to AP CPUs and factor out the debugging info from setup_uma_memory().

    Change-Id: I1acb4eaa3fe118aee223df1ebff997289f5d3a56
    Signed-off-by: Kyösti Mälkki <kyosti.malkki <at> gmail.com>
---
 src/cpu/amd/mtrr/amd_mtrr.c                        |   24 ++++++++++++++++++++
 src/include/cpu/amd/mtrr.h                         |    5 ++++
 src/northbridge/amd/agesa/family10/northbridge.c   |    1 +
 src/northbridge/amd/agesa/family12/northbridge.c   |   23 ++++---------------
 src/northbridge/amd/agesa/family14/northbridge.c   |   21 +++--------------
 src/northbridge/amd/agesa/family15/northbridge.c   |   22 ++++--------------
 src/northbridge/amd/agesa/family15tn/northbridge.c |   22 ++++--------------
 src/northbridge/amd/amdfam10/northbridge.c         |   22 +++---------------
 src/northbridge/amd/amdk8/northbridge.c            |   21 ++++-------------
 9 files changed, 58 insertions(+), 103 deletions(-)

diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index f639d59..7787d7e 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
(Continue reading)

Kyösti Mälkki | 1 Aug 15:43 2012

New patch to review for coreboot: 904f425 Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPU

Kyösti Mälkki (kyosti.malkki <at> gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/1388

-gerrit

commit 904f4257ab0b0bcf4ec35c8eaf807ca78eed66ab
Author: Kyösti Mälkki <kyosti.malkki <at> gmail.com>
Date:   Wed Aug 1 14:32:13 2012 +0300

    Replicate TOP_MEM and TOP_MEM2 from BSP to AP CPU

    The search loop for UMA resource was only used to check for the highest
    RAM address below 4GB. The cached values from BSP CPU can now be used
    for the replication.

    Change-Id: I5244ffa6f8a93f5ff5aaf8a71bd006b0f9cd518a
    Signed-off-by: Kyösti Mälkki <kyosti.malkki <at> gmail.com>
---
 src/cpu/amd/mtrr/amd_mtrr.c |   49 ++++++++++++++++++------------------------
 1 files changed, 21 insertions(+), 28 deletions(-)

diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c
index 7787d7e..8abc3d3 100644
--- a/src/cpu/amd/mtrr/amd_mtrr.c
+++ b/src/cpu/amd/mtrr/amd_mtrr.c
 <at>  <at>  -102,20 +102,6  <at>  <at>  static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc

 }

-static void uma_fb_resource(void *gp, struct device *dev, struct resource *res)
-{
(Continue reading)


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