Stefan Reinauer | 1 May 01:49 2012

New patch to review for coreboot: 887793d Set up the Emerald Lake 2 SMI and SCI sources based on the schematic.

Stefan Reinauer (stefan.reinauer <at> coreboot.org) just uploaded a new patch set to gerrit, which you can
find at http://review.coreboot.org/964

-gerrit

commit 887793df39d78bcdab65cb965a98fcd31b88fca4
Author: Gabe Black <gabeblack <at> google.com>
Date:   Thu Mar 29 17:58:52 2012 -0700

    Set up the Emerald Lake 2 SMI and SCI sources based on the schematic.

    This sets up the SMI and SCI inputs on the PCH for Emerald Lake 2 based on my
    best interpretation of the schematic. It may not be correct, but it doesn't
    seem to cause any problems either.

    Change-Id: I21238b3853a92893ec7f08baa2a3ebd35c49dd97
    Signed-off-by: Gabe Black <gabeblack <at> google.com>
---
 src/mainboard/intel/emeraldlake2/devicetree.cb |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb
index 2631cfc..686fe2e 100644
--- a/src/mainboard/intel/emeraldlake2/devicetree.cb
+++ b/src/mainboard/intel/emeraldlake2/devicetree.cb
 <at>  <at>  -45,8 +45,10  <at>  <at>  chip northbridge/intel/sandybridge
 			#  0 No effect (default)
 			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
 			#  2 SCI (if corresponding GPIO_EN bit is also set)
-			register "gpi1_routing" = "0"
(Continue reading)

Stefan Reinauer | 1 May 01:49 2012

New patch to review for coreboot: db4ce07 Set up ChromeOS dev mode, recovery, and write protect GPIOs on Emerald Lake 2.

Stefan Reinauer (stefan.reinauer <at> coreboot.org) just uploaded a new patch set to gerrit, which you can
find at http://review.coreboot.org/965

-gerrit

commit db4ce0735688cb695465e162974d88f95e8a4833
Author: Gabe Black <gabeblack <at> google.com>
Date:   Thu Mar 29 18:04:56 2012 -0700

    Set up ChromeOS dev mode, recovery, and write protect GPIOs on Emerald Lake 2.

    The Emerald Lake 2 CRB wasn't designed with ChromeOS in mind, so there aren't
    any actual developer mode, recovery mode, or write protect switches, let alone
    GPIOs to read them from. Instead, I've commandeered signals connected to GPIOs
    which are for other things but which aren't used by hardware or, for instance,
    the EC to do something Coreboot doesn't control.

    The recovery mode switch is connected to GPIO 22 and is called BIOS_REC on the
    schematic. The name is at least very reminiscent of the right thing even if
    it's supposed to be used for something else. There's a jumper on the board
    labelled J8G1 which can force the line to ground, and if not, there's a switch
    on the front of the case which toggles its value. "RECOVER" is for recovery
    mode and "KEEP" is for normal mode.

    The developer mode switch is connected to GPIO 57 and is called SV_DET on the
    schematic. It's connected to a jumper labelled J8E2 on the board and, as far as
    I can tell, can't be controlled in any other way. When the jumper is in place
    and the pins are shorted, developer mode is selected. When the jumper is
    removed, normal mode is selected.

(Continue reading)

Stefan Reinauer | 1 May 01:49 2012

New patch to review for coreboot: d7f3d69 Allow more CPU cores on Emerald Lake 2 CRB

Stefan Reinauer (stefan.reinauer <at> coreboot.org) just uploaded a new patch set to gerrit, which you can
find at http://review.coreboot.org/966

-gerrit

commit d7f3d6996e3d67f69533a69d773e4fde897d347a
Author: Stefan Reinauer <reinauer <at> chromium.org>
Date:   Wed Mar 28 13:19:15 2012 -0700

    Allow more CPU cores on Emerald Lake 2 CRB

    The Emerald Lake 2 CRB can potentially have more
    than 8 CPU cores, so update the number of max cores
    accordingly.

    Change-Id: Ia42ed8a84916f66dfbfdf2a72cbbed5cea61899b
    Signed-off-by: Stefan Reinauer <reinauer <at> google.com>
---
 src/mainboard/intel/emeraldlake2/Kconfig |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig
index 9916aaa..002ae2a 100644
--- a/src/mainboard/intel/emeraldlake2/Kconfig
+++ b/src/mainboard/intel/emeraldlake2/Kconfig
 <at>  <at>  -37,7 +37,7  <at>  <at>  config IRQ_SLOT_COUNT

 config MAX_CPUS
 	int
-	default 8
(Continue reading)

Stefan Reinauer | 1 May 01:49 2012

New patch to review for coreboot: ea39273 Clean up Emerald Lake 2 mainboard directory

Stefan Reinauer (stefan.reinauer <at> coreboot.org) just uploaded a new patch set to gerrit, which you can
find at http://review.coreboot.org/967

-gerrit

commit ea39273f80f64da5992b79e86ec950d6e0a3b420
Author: Gabe Black <gabeblack <at> google.com>
Date:   Fri Mar 30 14:33:02 2012 -0700

    Clean up Emerald Lake 2 mainboard directory

    Change-Id: I4a64a56dda22050a31232807096e15565a665377
    Signed-off-by: Gabe Black <gabeblack <at> google.com>
---
 src/mainboard/intel/emeraldlake2/gpio.h     |    6 +++---
 src/mainboard/intel/emeraldlake2/romstage.c |    2 +-
 src/mainboard/intel/emeraldlake2/thermal.h  |    4 ++--
 3 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/mainboard/intel/emeraldlake2/gpio.h b/src/mainboard/intel/emeraldlake2/gpio.h
index c458c83..05b9164 100644
--- a/src/mainboard/intel/emeraldlake2/gpio.h
+++ b/src/mainboard/intel/emeraldlake2/gpio.h
 <at>  <at>  -17,8 +17,8  <at>  <at> 
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */

-#ifndef LINK_GPIO_H
-#define LINK_GPIO_H
+#ifndef EMERALDLAKE2_GPIO_H
(Continue reading)

Stefan Reinauer | 1 May 01:50 2012

New patch to review for coreboot: e1b81de add new LPC controller device ID value

Stefan Reinauer (stefan.reinauer <at> coreboot.org) just uploaded a new patch set to gerrit, which you can
find at http://review.coreboot.org/968

-gerrit

commit e1b81deaf1c17cb2c6723b8a35a595e0e6edf162
Author: Vadim Bendebury <vbendeb <at> chromium.org>
Date:   Sat Apr 7 02:11:36 2012 +0000

    add new LPC controller device ID value

    This adds the PCI device id of the LPC controller identifying the
    QPRJ/QS stepping of the Panther Point southbridge.

    Change-Id: Idcaa7dbd30224e3690ea469c6cb74f75de287631
    Signed-off-by: Vadim Bendebury <vbendeb <at> chromium.org>
---
 src/southbridge/intel/bd82x6x/lpc.c |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 1ecaf8f..9a3dc99 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
 <at>  <at>  -676,3 +676,8  <at>  <at>  static const struct pci_driver c216_lpc __pci_driver = {
 	.vendor	= PCI_VENDOR_ID_INTEL,
 	.device	= 0x1e55,
 };
+static const struct pci_driver hm75_lpc __pci_driver = {
+	.ops	= &device_ops,
(Continue reading)

Stefan Reinauer | 1 May 01:50 2012

New patch to review for coreboot: e3e901d Modify DMI init for IvyBridge

Stefan Reinauer (stefan.reinauer <at> coreboot.org) just uploaded a new patch set to gerrit, which you can
find at http://review.coreboot.org/969

-gerrit

commit e3e901db657591603411402a1ceb581873480442
Author: Vincent Palatin <vpalatin <at> chromium.org>
Date:   Wed Mar 28 16:10:29 2012 -0700

    Modify DMI init for IvyBridge

    The ASPM setting for the Direct Media Interface should no longer be done on
    Ivybridge/PantherPoint based systems.

    Change-Id: Id30de1beb1b162564048e76712736ccf7049dc7c
    Signed-off-by: Vincent Palatin <vpalatin <at> chromium.org>
---
 src/northbridge/intel/sandybridge/northbridge.c |   18 +++++++++++-------
 1 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index e3334c4..b1f7c72 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
 <at>  <at>  -347,10 +347,12  <at>  <at>  static void northbridge_dmi_init(struct device *dev)
 	DMIBAR32(0x1d0) = 0xffffffff;

 	/* Steps prior to DMI ASPM */
-	reg32 = DMIBAR32(0x250);
-	reg32 &= ~((1 << 22)|(1 << 20));
(Continue reading)

Stefan Reinauer | 1 May 01:50 2012

New patch to review for coreboot: 448a583 Only send ME Dram Init Done message on Sandybridge

Stefan Reinauer (stefan.reinauer <at> coreboot.org) just uploaded a new patch set to gerrit, which you can
find at http://review.coreboot.org/970

-gerrit

commit 448a58332fe61afe811862167486c6ec291963ba
Author: Duncan Laurie <dlaurie <at> chromium.org>
Date:   Mon Apr 9 12:30:43 2012 -0700

    Only send ME Dram Init Done message on Sandybridge

    This is done inside the SystemAgent binary on Ivybridge.

    Change-Id: I8fb0f593a65a4803e160b284c21b9d5021e2e4a0
    Signed-off-by: Duncan Laurie <dlaurie <at> chromium.org>
---
 src/northbridge/intel/sandybridge/raminit.c |    9 ++++++++-
 1 files changed, 8 insertions(+), 1 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index dcf9f63..bbb743f 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
 <at>  <at>  -27,6 +27,7  <at>  <at> 
 #include <cbfs.h>
 #include <ip_checksum.h>
 #include <pc80/mc146818rtc.h>
+#include <device/pci_def.h>
 #include "raminit.h"
 #include "pei_data.h"
(Continue reading)

Stefan Reinauer | 1 May 01:50 2012

New patch to review for coreboot: dc5c7e0 Don't disable ACPI in the S3 resume path

Stefan Reinauer (stefan.reinauer <at> coreboot.org) just uploaded a new patch set to gerrit, which you can
find at http://review.coreboot.org/971

-gerrit

commit dc5c7e0b63d9b8b3429ae6fb929cbb39efec4159
Author: Duncan Laurie <dlaurie <at> chromium.org>
Date:   Mon Apr 9 12:31:43 2012 -0700

    Don't disable ACPI in the S3 resume path

    The OS does not re-execute the APMC 'enable ACPI' SMI
    on resume so this has the potential to leave things
    in an unknown state.

    Change-Id: Iaf0fcb99f699e9e0ecacaab3f529026782a95151
    Signed-off-by: Duncan Laurie <dlaurie <at> chromium.org>
---
 src/southbridge/intel/bd82x6x/lpc.c |   15 +++++++++------
 1 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 9a3dc99..dddab6a 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
 <at>  <at>  -396,15 +396,18  <at>  <at>  static void pch_lock_smm(struct device *dev)
 	u8 reg8;
 #endif

+	if (acpi_slp_type != 3) {
(Continue reading)

Stefan Reinauer | 1 May 01:50 2012

New patch to review for coreboot: d3884c8 Fix TPM driver to work with multiple vendor TPMs

Stefan Reinauer (stefan.reinauer <at> coreboot.org) just uploaded a new patch set to gerrit, which you can
find at http://review.coreboot.org/972

-gerrit

commit d3884c83a8cc31b3b3bae3eee92e4d429d4c8d52
Author: Stefan Reinauer <reinauer <at> chromium.org>
Date:   Mon Apr 30 16:33:44 2012 -0700

    Fix TPM driver to work with multiple vendor TPMs

    Port u-boot patch for low-level driver:
    - Fix bug in traversal of vendor name list.
    - Sending "command ready" needs additional logic to handle
    TPMs that need that bit set twice: once to empty the read
    FIFOs and once to actualy set command ready.

    Change-Id: I57c280266b2e966c5b90e4f9e968426a33b93cf1
    Signed-off-by: Duncan Laurie <dlaurie <at> chromium.org>
---
 src/drivers/pc80/tpm.c |   85 ++++++++++++++++++++++++++++++++++++++++++------
 1 files changed, 75 insertions(+), 10 deletions(-)

diff --git a/src/drivers/pc80/tpm.c b/src/drivers/pc80/tpm.c
index 17e1ed7..c7b5081 100644
--- a/src/drivers/pc80/tpm.c
+++ b/src/drivers/pc80/tpm.c
 <at>  <at>  -127,13 +127,31  <at>  <at>  struct vendor_name {
 	const struct device_name* dev_names;
 };
(Continue reading)

Stefan Reinauer | 1 May 01:50 2012

New patch to review for coreboot: 8f492d6 Update ivybridge graphics initialization

Stefan Reinauer (stefan.reinauer <at> coreboot.org) just uploaded a new patch set to gerrit, which you can
find at http://review.coreboot.org/973

-gerrit

commit 8f492d6c487068317267a59a9a47c9be7b72a543
Author: Duncan Laurie <dlaurie <at> chromium.org>
Date:   Mon Apr 9 12:05:18 2012 -0700

    Update ivybridge graphics initialization

    - Add config options to set backlight registers
    - Update powermeter weight tables for IvyBridge GT1 and
    add a new table for GT2 SKU
    - Fix a few registers used during GPU PM init sequence

    Change-Id: I1500bc07e3ba1bc10c77e7856089e716489dc07a
    Signed-off-by: Duncan Laurie <dlaurie <at> chromium.org>
---
 src/northbridge/intel/sandybridge/chip.h |    3 +
 src/northbridge/intel/sandybridge/gma.c  |  309 ++++++++++++++++++++----------
 2 files changed, 213 insertions(+), 99 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h
index b891884..bd89787 100644
--- a/src/northbridge/intel/sandybridge/chip.h
+++ b/src/northbridge/intel/sandybridge/chip.h
 <at>  <at>  -35,6 +35,9  <at>  <at>  struct northbridge_intel_sandybridge_config {
 	u16 gpu_panel_power_down_delay;          /* T3 time sequence */
 	u16 gpu_panel_power_backlight_on_delay;  /* T5 time sequence */
(Continue reading)


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