Patrick Georgi | 4 Apr 19:53 2012
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Re: New patch to review for coreboot: c2e50ec Use fast memset in SMM mode, too

Am 04.04.2012 19:51, schrieb Peter Stuge:
> Stefan Reinauer wrote:
>> ... and always include IP checksumming in romstage. It's generally
>> useful and our upcoming port needs it.
> I don't know.. Why add code which in most cases isn't being used. 
> We've created a fairly elaborate and powerful build system 
> specifically to avoid this, and you ignore it because of "useful" ?
The linker should kick it out again. I oppose having a config flag for
every single source file.

Patrick

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Jonathan Bennett | 4 Apr 20:30 2012
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Re: Asus M5A88-v evo

I've done a bit of looking, and found the code in question. It looks
like the code is trying to figure out what family10 proc it is. The
only problem, it's running a bulldozer processor. cpuinfo lists it as
a family 21. Are the fx family processors supported at all?

~Jonathan

>That's pretty clear. I suggest to boot with factory BIOS, check the
>exact parameters of the CPU, look at the code which is being run, and
>look for relevant documentation for your CPU in the scope of that
>code.

>If you are lucky you only need to add a few values from the
>documentation to tables in the code.

>//Peter
>On Tue, Apr 3, 2012 at 5:24 PM, Jonathan Bennett <jbscience87 <at> gmail.com> wrote:
>> On Tue, Mar 20, 2012 at 4:36 PM, Julian Shulika <hercares <at> gmail.com> wrote:
>>> Could you please show log from serial,your board has com port.
>> Finally got a couple spare flash chips and a way to capture the serial output.
>>
>> coreboot-4.0-2227-g4a2daf6 Tue Apr  3 15:29:40 CDT 2012 starting...
>>
>> BSP Family_Model: 00600f12
>> *sysinfo range: [000cc000,000cf360]
>> bsp_apicid = 00
>> cpu_init_detectedx = 00000000
>> microcode: rev id not foung, Skipping microcode patch!
>> POST: 0x33
>> cpuSetAMDMSR FIXME! CPU Version unknown or not supported!
(Continue reading)

Svetoslav Trochev | 4 Apr 23:17 2012
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Re: GSoC project ideas

Hi Paul,

On Tue, Apr 3, 2012 at 11:19 PM, Paul Geraedts <p.f.j.geraedts <at> gmail.com> wrote:

>> - Flash ICE device with SPI support.
>> - Flash ICE device with LPC/FWH support.
>> - Serial emulation for LPC buses on a configurable I/O port with USB
>> output on the other side.
>> - Dual serial emulation for two LPC buses either on the same device or
>> with two identical devices and a fast bus in between.
>> - Serial emulation for PCI buses (i.e. PCI/serial card).
>
> Currently I am working towards items 1 and 3 of your list. Eventually I
> want to use this hardware to replace the flash content of my MSI Wind
> U100 netbook with free software (openec, coreboot, seabios, ipxe, grub2,
> etc). I want to keep my implementation sufficiently generic to allow for
> extensions like items 2, 4 and 5 of your list.

I am also interested in item 1. [1] But looks like you are far ahead
of me. :) Currently I am waiting for my hardware to arrive. I ordered
Open Workbench Logic Sniffer [2]. Do you think I can help you in your
work?

Best regards,
Svetoslav

[1] http://www.coreboot.org/pipermail/coreboot/2012-March/068993.html
[2] http://www.seeedstudio.com/depot/open-workbench-logic-sniffer-p-612.html?cPath=174

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(Continue reading)

ron minnich | 4 Apr 23:44 2012
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Re: New patch to review for coreboot: c2e50ec Use fast memset in SMM mode, too

On Wed, Apr 4, 2012 at 10:53 AM, Patrick Georgi <patrick <at> georgi-clan.de> wrote:

> The linker should kick it out again. I oppose having a config flag for
> every single source file.

by analogy, there is a huge amount of code compiled into glibc that I
don't use. It's the compilers/linkers job to not build in those things
I don't need, even if I compile them. I agree with patrick and stefan
on this one.

ron

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Oliver Schinagl | 5 Apr 01:08 2012
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Re: Dual SPI Flash adapter

Hi list,

Unfortunately I have had little feedback so far. But here's a small update.

I have finally received my SO8 memory modules and those babies are 
small. Because of this, I have replaced the SO8M footprint with an SO8W 
footprint, making it quite a bit wider, but should be much easier to 
manually solder. I tried for an hour to fit a 1008 footprint for the 
resistors but there would be hardly any room left for silkscreening. 
Also all the smd compontens that I have to salvage seem to be 0603 
components anyway. I'm sure people will manage to solder 2 resistors.

I've also saw a screenshot of an Asus motherboard that had the bios chip 
right next to a Sata port, in the wrong/different orientation, so I've 
added a 3rd design so all 3 possible insertations are possible. (Left, 
center and right facing connector).

I've attached the gEDA .pcb file with the 3 orientation, with each 
having their individually nets/defs so that the DRC/rat check works. 
When sending out the final rev. I'll copy/paste the silk screens from 
the left design so they all look identical.

If I get no negative feedback, I'll try to send the boards out for 
manufacture next week, so in a month or two I should have about 40 PCB's 
and would be happy to send a few out to coreboot dev's, if there's any 
interest at all :)

Oliver
Attachment (dspif.pcb): application/x-pcb-layout, 72 KiB
(Continue reading)

Peter Stuge | 5 Apr 01:23 2012
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Re: Dual SPI Flash adapter

Oliver Schinagl wrote:
> Unfortunately I have had little feedback so far. But here's a small
> update.

Thanks for the update.

I did look at your previous board but needed more time to really look
closely.

> I have finally received my SO8 memory modules and those babies are
> small.

Oh it's not so bad. :) Try the 0603 resistors.

> Because of this, I have replaced the SO8M footprint with an SO8W
> footprint,

This is actually correct. All SPI flash chips used in PCs are in the
200 mil wide package, not the standard SO8 which is only 150 mil.

> I've also saw a screenshot of an Asus motherboard that had the bios chip 
> right next to a Sata port, in the wrong/different orientation, so I've 
> added a 3rd design so all 3 possible insertations are possible. (Left, 
> center and right facing connector).

Ah, so the plan is that your PCB is plugged into the factory BIOS
socket? That's a nice idea, but as you discovered there are four ways
that the chip can be oriented, so you really have to make four
boards to have a solution that works on every board. :\

(Continue reading)

Oliver Schinagl | 5 Apr 01:40 2012
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Re: Dual SPI Flash adapter

On 04/05/12 01:23, Peter Stuge wrote:
> Oliver Schinagl wrote:
>> Unfortunately I have had little feedback so far. But here's a small
>> update.
>
> Thanks for the update.
>
> I did look at your previous board but needed more time to really look
> closely.
That would be grand!

>
>
>> I have finally received my SO8 memory modules and those babies are
>> small.
>
> Oh it's not so bad. :) Try the 0603 resistors.
>
>
>> Because of this, I have replaced the SO8M footprint with an SO8W
>> footprint,
>
> This is actually correct. All SPI flash chips used in PCs are in the
> 200 mil wide package, not the standard SO8 which is only 150 mil.

There are 3 SO8 package footprints in PCB, SO8, SO8M and SO8W. None fit 
'perfectly'. S08 is way to small to be usefull, SO8M fits 'perfectly' 
but makes it extremly hard to solder I recon, since the pad, ends at the 
legs. SO8W seems to be a little to wide, the legs end up perfectly on 
the inner sides, which might make it not to cover the back 'cavities' 
(Continue reading)

Peter Stuge | 5 Apr 01:53 2012
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Re: Dual SPI Flash adapter

Oliver Schinagl wrote:
> There are 3 SO8 package footprints in PCB, SO8, SO8M and SO8W. None fit 
> 'perfectly'.

I'll see if I can send you a footprint I've used.

>> Thanks. I'll try to give some more detailed feedback, but one big
>> no-no that I've seen already is that your silk is covering pads.
>> Noone will do any cropping for you, so you will indeed get silkscreen
>> on your pads, which 1) potentially makes the board house unhappy
>> because it may make a mess in their machines, and 2) makes it
>> difficult for solder to flow over the pad.
> 
> Hmm, I assumed silk screening is applied last, as I have seen
> soldermasks and silkscreening covering via's. The only thing I
> cover IS via's ...

No. See attached file, or http://stuge.se/4.png if it gets stripped
from the list.

//Peter
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Zheng Bao | 5 Apr 06:11 2012

Patch set updated for coreboot: 325bdf4 S3 code in the mainboard.

Zheng Bao (zheng.bao <at> amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/624

-gerrit

commit 325bdf4d44842c49c9d767fb95fc0f97a6bf69a9
Author: zbao <fishbaozi <at> gmail.com>
Date:   Thu Apr 5 13:22:50 2012 +0800

    S3 code in the mainboard.

    Persimmon is the demo board. Tested by Linux and Windows 7.

    Change-Id: I5ded942b51e63ebeb08ace0b202b4ed239b0c14c
    Signed-off-by: Zheng Bao <zheng.bao <at> amd.com>
    Signed-off-by: zbao <fishbaozi <at> gmail.com>
---
 src/mainboard/amd/persimmon/BiosCallOuts.c         |   40 +++--
 src/mainboard/amd/persimmon/BiosCallOuts.h         |    4 +-
 src/mainboard/amd/persimmon/Kconfig                |    1 +
 src/mainboard/amd/persimmon/PlatformGnbPcie.c      |    2 +-
 .../amd/persimmon/PlatformGnbPcieComplex.h         |    1 +
 src/mainboard/amd/persimmon/agesawrapper.c         |  175 +++++++++++++++++++-
 src/mainboard/amd/persimmon/agesawrapper.h         |    5 +
 src/mainboard/amd/persimmon/buildOpts.c            |    6 +-
 src/mainboard/amd/persimmon/get_bus_conf.c         |   21 ++-
 src/mainboard/amd/persimmon/mainboard.c            |   16 ++-
 src/mainboard/amd/persimmon/romstage.c             |   90 ++++++++--
 11 files changed, 312 insertions(+), 49 deletions(-)

diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c
(Continue reading)

Zheng Bao | 5 Apr 06:11 2012

Patch set updated for coreboot: fe35e15 S3 code in vendorcode folder.

Zheng Bao (zheng.bao <at> amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/622

-gerrit

commit fe35e15686970be4488bfe86cda8559f9172bde8
Author: zbao <fishbaozi <at> gmail.com>
Date:   Thu Apr 5 13:20:50 2012 +0800

    S3 code in vendorcode folder.

    Change the ExecuteFinalHltInstruction to assembly code. so we can make
    sure the code can run stackless.

    Change-Id: I783ced6cf7c5bc29c12a37aef29077e610d8957d
    Signed-off-by: Zheng Bao <zheng.bao <at> amd.com>
    Signed-off-by: zbao <fishbaozi <at> gmail.com>
---
 src/cpu/amd/agesa/family14/Makefile.inc            |    1 +
 src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h  |   10 +-
 src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.c     |  141 +-------------
 src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S  |  203 ++++++++++++++++++++
 .../amd/agesa/f14/Proc/Common/AmdS3Save.c          |    2 +-
 .../amd/agesa/f14/Proc/Mem/Feat/S3/mfs3.c          |   10 +-
 src/vendorcode/amd/agesa/f14/gcccar.inc            |  192 ++++++++++---------
 7 files changed, 325 insertions(+), 234 deletions(-)

diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc
index 774d401..b08ceeb 100644
--- a/src/cpu/amd/agesa/family14/Makefile.inc
+++ b/src/cpu/amd/agesa/family14/Makefile.inc
(Continue reading)


Gmane