Discussions regarding the LinuxBIOS project

Kerry Sheh | 1 Feb 06:13

New patch to review for coreboot: 425158e CIMX wrapper: remove redudant traversing sb800 and sb900 CIMX dir

Kerry Sheh (shekairui <at> gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/602

-gerrit

commit 425158e483eb7ea8a5faf742742b42396ecd8fd4
Author: Kerry Sheh <shekairui <at> gmail.com>
Date:   Wed Feb 1 14:07:38 2012 +0800

    CIMX wrapper: remove redudant traversing sb800 and sb900 CIMX dir

    AGESA and CIMX build changed from commit 2a830d0b,
    sb800 and sb900 CIMX dir already traversed in vendorcode Makefile.

    Change-Id: I5101b22e140725337bf5074b9170e582c8e3bf40
    Signed-off-by: Kerry Sheh <kerry.she <at> amd.com>
    Signed-off-by: Kerry Sheh <shekairui <at> gmail.com>
---
 src/southbridge/amd/cimx/sb800/Makefile.inc |    1 -
 src/southbridge/amd/cimx/sb900/Makefile.inc |    1 -
 2 files changed, 0 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/amd/cimx/sb800/Makefile.inc b/src/southbridge/amd/cimx/sb800/Makefile.inc
index 48b198d..30d2133 100644
--- a/src/southbridge/amd/cimx/sb800/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb800/Makefile.inc
@@ -17,7 +17,6 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #

-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += ../../../../../src/vendorcode/amd/cimx/sb800

(Continue reading)

Kerry Sheh | 1 Feb 06:13

Patch set updated for coreboot: cd71eb2 Mainboard: Supermicro/h8qgi mainboard update

Kerry Sheh (shekairui <at> gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/567

-gerrit

commit cd71eb2ca5f4da5af050e606e608345c5933164d
Author: Kerry Sheh <shekairui <at> gmail.com>
Date:   Wed Feb 1 13:59:01 2012 +0800

    Mainboard: Supermicro/h8qgi mainboard update
    
    1. Supermicro H8QGI mainboard update to support both family10 Revison D
       processor and family15 model 00-0fh processor in one binary image.
    2. RD890/SR56X0 IO hub CIMX wrapper support.
    3. SP5100/SB700 southbridge CIMX wrapper support.
    
    Both 8 cores and 16 Cores InterLagos Opteron Processor are
    tested on this platform.
    Debian Linux 5.0 and Windows Server 2008 R2 Statdard are tested.
    
    Change-Id: Iaad8c9b08310813441188deee6797b3f6dd37d6d
    Signed-off-by: Kerry Sheh <kerry.she <at> amd.com>
    Signed-off-by: Kerry Sheh <shekairui <at> gmail.com>
---
 src/mainboard/supermicro/h8qgi/BiosCallOuts.c   |    2 +-
 src/mainboard/supermicro/h8qgi/BiosCallOuts.h   |    2 +-
 src/mainboard/supermicro/h8qgi/Kconfig          |   20 +-
 src/mainboard/supermicro/h8qgi/Makefile.inc     |   18 ++-
 src/mainboard/supermicro/h8qgi/OptionsIds.h     |    2 +-
 src/mainboard/supermicro/h8qgi/acpi/cpstate.asl |    2 +-
 src/mainboard/supermicro/h8qgi/acpi/ide.asl     |    2 +-

(Continue reading)

Kerry Sheh | 1 Feb 06:13

Patch set updated for coreboot: 22d10e9 SIO: condition compile Nuvoton WPCM450 early_init.c

Kerry Sheh (shekairui <at> gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/566

-gerrit

commit 22d10e91dec3aefb162cba777f32815bd745a295
Author: Kerry Sheh <shekairui <at> gmail.com>
Date:   Wed Feb 1 13:59:00 2012 +0800

    SIO: condition compile Nuvoton WPCM450 early_init.c

    Compile Nuvoton WPCM450 early_init.c when CONFIG_SUPERIO_NUVOTON_WPCM450

    Change-Id: Ie31b8ae6aa45d6f77efa2b61e215ba0987abf878
    Signed-off-by: Kerry Sheh <kerry.she <at> amd.com>
    Signed-off-by: Kerry Sheh <shekairui <at> gmail.com>
---
 src/superio/nuvoton/wpcm450/Makefile.inc |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/superio/nuvoton/wpcm450/Makefile.inc b/src/superio/nuvoton/wpcm450/Makefile.inc
index c70b2fb..b4e4ea7 100644
--- a/src/superio/nuvoton/wpcm450/Makefile.inc
+++ b/src/superio/nuvoton/wpcm450/Makefile.inc
@@ -1,7 +1,7 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2011 Advanced Micro Devices, Inc.
+## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
 ##

(Continue reading)

Kerry Sheh | 1 Feb 06:13

Patch set updated for coreboot: 6eff497 SIO: Winbond w83627dhg update

Kerry Sheh (shekairui <at> gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/565

-gerrit

commit 6eff4971430c641cdba28b38798026bb8f23f7bc
Author: Kerry Sheh <shekairui <at> gmail.com>
Date:   Wed Feb 1 13:58:57 2012 +0800

    SIO: Winbond w83627dhg update

    1. Stop include c file.
    2. W83627dhg Pin 89, Pin 90 are multi function pins,
       add support to select them to I2C function.

    Change-Id: I42eaaf7d70aa48d7edf2710349b51e401526c1a6
    Signed-off-by: Kerry Sheh <kerry.she <at> amd.com>
    Signed-off-by: Kerry Sheh <shekairui <at> gmail.com>
---
 src/mainboard/asrock/939a785gmh/romstage.c   |    2 +-
 src/mainboard/kontron/kt690/romstage.c       |    2 +-
 src/superio/winbond/w83627dhg/Makefile.inc   |    2 +
 src/superio/winbond/w83627dhg/early_serial.c |   29 +++++++++++++++++++++++--
 src/superio/winbond/w83627dhg/superio.c      |    4 +-
 src/superio/winbond/w83627dhg/w83627dhg.h    |    6 +++++
 6 files changed, 38 insertions(+), 7 deletions(-)

diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index 3183c1c..4a1b1c3 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c

(Continue reading)

Kerry Sheh | 1 Feb 06:13

Patch set updated for coreboot: 0dcb076 Mainboard: Add AMD dinar mainboard.

Kerry Sheh (shekairui <at> gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/564

-gerrit

commit 0dcb076b020e1395ec40cea2309d2ce93a80c153
Author: Kerry Sheh <shekairui <at> gmail.com>
Date:   Wed Feb 1 13:58:52 2012 +0800

    Mainboard: Add AMD dinar mainboard.
    
    Dinar mainboard is an AMD evaluation board for
    Orochi Platform family15 model 00-0f processor.
    
    The mainbaord has dual G34 Socket, SR5690/SR5670/SR5650 and SP5100 chipsets.
    16 cores InterLagos Opteron processor are supported.
    Windows 7 are verified on this platform.
    
    Change-Id: Id97d35e7bca9f0d422841e23f4b762f1ed101ea0
    Signed-off-by: Kerry Sheh <kerry.she <at> amd.com>
    Signed-off-by: Kerry Sheh <shekairui <at> gmail.com>
---
 src/mainboard/amd/Kconfig                        |    3 +
 src/mainboard/amd/dinar/BiosCallOuts.c           |  563 ++++++
 src/mainboard/amd/dinar/BiosCallOuts.h           |   79 +
 src/mainboard/amd/dinar/Kconfig                  |  211 ++
 src/mainboard/amd/dinar/Makefile.inc             |   40 +
 src/mainboard/amd/dinar/Oem.h                    |   79 +
 src/mainboard/amd/dinar/OptionsIds.h             |   64 +
 src/mainboard/amd/dinar/PlatformGnbPcie.c        |  176 ++
 src/mainboard/amd/dinar/PlatformGnbPcieComplex.h |   72 +

(Continue reading)

Kerry Sheh | 1 Feb 06:13

Patch set updated for coreboot: 69f2e61 SIO: Add smsc sio1036 superio

Kerry Sheh (shekairui <at> gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/563

-gerrit

commit 69f2e61ac499ca29e661dcbde4adf5ac6ec63fb7
Author: Kerry Sheh <shekairui <at> gmail.com>
Date:   Wed Feb 1 13:55:29 2012 +0800

    SIO: Add smsc sio1036 superio

    Change-Id: Iaf5519f304f9f16f7ff6e4b02060bb75a3605ce9
    Signed-off-by: Kerry Sheh <kerry.she <at> amd.com>
    Signed-off-by: Kerry Sheh <shekairui <at> gmail.com>
---
 src/superio/smsc/Kconfig                      |    2 +
 src/superio/smsc/Makefile.inc                 |    1 +
 src/superio/smsc/sio1036/Makefile.inc         |   21 ++++
 src/superio/smsc/sio1036/chip.h               |   34 +++++++
 src/superio/smsc/sio1036/sio1036.h            |   25 +++++
 src/superio/smsc/sio1036/sio1036_early_init.c |  101 ++++++++++++++++++++
 src/superio/smsc/sio1036/superio.c            |  122 +++++++++++++++++++++++++
 7 files changed, 306 insertions(+), 0 deletions(-)

diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig
index ddd5b96..d4f07ec 100644
--- a/src/superio/smsc/Kconfig
+++ b/src/superio/smsc/Kconfig
@@ -40,5 +40,7 @@ config SUPERIO_SMSC_KBC1100
 	bool
 config SUPERIO_SMSC_SMSCSUPERIO

(Continue reading)

Kerry Sheh | 1 Feb 06:13

Patch set updated for coreboot: fbf9599 SIO: Add smsc/sch4037 superio support

Kerry Sheh (shekairui <at> gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/562

-gerrit

commit fbf959965fd4b88fe68017d931bec8fede1cf351
Author: Kerry Sheh <shekairui <at> gmail.com>
Date:   Wed Feb 1 13:55:28 2012 +0800

    SIO: Add smsc/sch4037 superio support

    Change-Id: I3b113a27541b8efd096f3bd44e6621344ec916a5
    Signed-off-by: Kerry Sheh <kerry.she <at> amd.com>
    Signed-off-by: Kerry Sheh <shekairui <at> gmail.com>
---
 src/superio/smsc/Kconfig                      |    3 +
 src/superio/smsc/Makefile.inc                 |    2 +
 src/superio/smsc/sch4037/Makefile.inc         |   20 +++
 src/superio/smsc/sch4037/chip.h               |   34 ++++
 src/superio/smsc/sch4037/sch4037.h            |  227 +++++++++++++++++++++++++
 src/superio/smsc/sch4037/sch4037_early_init.c |   71 ++++++++
 src/superio/smsc/sch4037/superio.c            |  123 +++++++++++++
 7 files changed, 480 insertions(+), 0 deletions(-)

diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig
index 7378d18..ddd5b96 100644
--- a/src/superio/smsc/Kconfig
+++ b/src/superio/smsc/Kconfig
@@ -2,6 +2,7 @@
 ## This file is part of the coreboot project.
 ##

(Continue reading)

Kerry Sheh | 1 Feb 06:13

Patch set updated for coreboot: 876830b SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper

Kerry Sheh (shekairui <at> gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/561

-gerrit

commit 876830b1cb1ac3c89549318176e81b2dd2b86489
Author: Kerry Sheh <shekairui <at> gmail.com>
Date:   Wed Feb 1 13:55:26 2012 +0800

    SB700 southbridge: AMD SB700/SP5100 southbridge CIMX wrapper
    
    Change-Id: If924b7eb176e7d3d82fa394929b653b1ced3a743
    Signed-off-by: Kerry Sheh <kerry.she <at> amd.com>
    Signed-off-by: Kerry Sheh <shekairui <at> gmail.com>
---
 src/southbridge/amd/Makefile.inc            |    1 +
 src/southbridge/amd/cimx/Kconfig            |    3 +-
 src/southbridge/amd/cimx/Makefile.inc       |    3 +-
 src/southbridge/amd/cimx/sb700/Amd.h        |  363 +++++++++++++++++++++++++++
 src/southbridge/amd/cimx/sb700/AmdSbLib.h   |  181 +++++++++++++
 src/southbridge/amd/cimx/sb700/Kconfig      |   63 +++++
 src/southbridge/amd/cimx/sb700/Makefile.inc |   31 +++
 src/southbridge/amd/cimx/sb700/Platform.h   |   87 +++++++
 src/southbridge/amd/cimx/sb700/bootblock.c  |   97 +++++++
 src/southbridge/amd/cimx/sb700/cbtypes.h    |   53 ++++
 src/southbridge/amd/cimx/sb700/chip.h       |   42 +++
 src/southbridge/amd/cimx/sb700/chip_name.c  |   25 ++
 src/southbridge/amd/cimx/sb700/early.c      |   75 ++++++
 src/southbridge/amd/cimx/sb700/late.c       |  329 ++++++++++++++++++++++++
 src/southbridge/amd/cimx/sb700/lpc.c        |  195 ++++++++++++++
 src/southbridge/amd/cimx/sb700/lpc.h        |   30 +++

(Continue reading)

Kerry Sheh | 1 Feb 06:13

Patch set updated for coreboot: 33b60dd SB700 southbridge: AMD SB700/SP5100 southbridge CIMX code

Kerry Sheh (shekairui <at> gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/560

-gerrit

commit 33b60ddb3d34150cd8d5a962758b02dcfd0e2127
Author: Kerry Sheh <shekairui <at> gmail.com>
Date:   Wed Feb 1 13:55:13 2012 +0800

    SB700 southbridge: AMD SB700/SP5100 southbridge CIMX code
    
    Support AMD SB700 and SP5100 chipsets.
    
    Change-Id: I0955abf7f48a79483f624b46a61b22711315f888
    Signed-off-by: Kerry Sheh <kerry.she <at> amd.com>
    Signed-off-by: Kerry Sheh <shekairui <at> gmail.com>
---
 src/vendorcode/amd/cimx/Makefile.inc       |    1 +
 src/vendorcode/amd/cimx/sb700/ACPILIB.c    |  120 ++++
 src/vendorcode/amd/cimx/sb700/ACPILIB.h    |   61 ++
 src/vendorcode/amd/cimx/sb700/AMDLIB.c     |  434 ++++++++++++
 src/vendorcode/amd/cimx/sb700/AMDSBLIB.c   |  276 ++++++++
 src/vendorcode/amd/cimx/sb700/AZALIA.c     |  304 ++++++++
 src/vendorcode/amd/cimx/sb700/DEBUG.c      |  169 +++++
 src/vendorcode/amd/cimx/sb700/DISPATCHER.c |  208 ++++++
 src/vendorcode/amd/cimx/sb700/EC.c         |  132 ++++
 src/vendorcode/amd/cimx/sb700/FLASH.c      |   58 ++
 src/vendorcode/amd/cimx/sb700/LEGACY.c     |   38 +
 src/vendorcode/amd/cimx/sb700/Makefile.inc |   77 ++
 src/vendorcode/amd/cimx/sb700/OEM.h        |   87 +++
 src/vendorcode/amd/cimx/sb700/SATA.c       |  453 ++++++++++++

(Continue reading)

Kerry Sheh | 1 Feb 06:13

Patch set updated for coreboot: 4b5a0b1 RD890: AMD RD890/SR56X0 CIMX wrapper

Kerry Sheh (shekairui <at> gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/559

-gerrit

commit 4b5a0b16088db08659d5d7176b33977f7538b5f6
Author: Kerry Sheh <shekairui <at> gmail.com>
Date:   Wed Feb 1 13:55:12 2012 +0800

    RD890: AMD RD890/SR56X0 CIMX wrapper

    Support AMD RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0,
    RD890 and 990FX chipsets.

    Change-Id: I39dc5fc316fbb465808bac48a13a49b7d867f04f
    Signed-off-by: Kerry Sheh <kerry.she <at> amd.com>
    Signed-off-by: Kerry Sheh <shekairui <at> gmail.com>
---
 src/northbridge/amd/Kconfig                 |    1 +
 src/northbridge/amd/Makefile.inc            |    1 +
 src/northbridge/amd/cimx/Kconfig            |   24 ++
 src/northbridge/amd/cimx/Makefile.inc       |   20 ++
 src/northbridge/amd/cimx/rd890/Kconfig      |   33 +++
 src/northbridge/amd/cimx/rd890/Makefile.inc |   25 ++
 src/northbridge/amd/cimx/rd890/NbPlatform.h |  147 ++++++++++
 src/northbridge/amd/cimx/rd890/amd.h        |  385 +++++++++++++++++++++++++++
 src/northbridge/amd/cimx/rd890/cbtypes.h    |   71 +++++
 src/northbridge/amd/cimx/rd890/chip.h       |   38 +++
 src/northbridge/amd/cimx/rd890/early.c      |  113 ++++++++
 src/northbridge/amd/cimx/rd890/late.c       |  269 +++++++++++++++++++
 src/northbridge/amd/cimx/rd890/nb_cimx.h    |   44 +++

(Continue reading)

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Recent entries

Patch merged into coreboot/master: 88a1ccf nvramtool: use C99 PRIx64 / (25 May 08:01)
Patch merged into coreboot/master: c960958 Fix size_t for certain vers (25 May 08:00)
Patch set updated for coreboot: b3d2676 Reduce default verbosity of SP (24 May 23:31)
Patch set updated for coreboot: 2af8cea Fix printk types in SPI flash (24 May 23:31)
New patch to review for coreboot: 88a1ccf nvramtool: use C99 PRIx64 / (24 May 22:40)
Patch set updated for coreboot: c960958 Fix size_t for certain version (24 May 22:30)
Patch merged into coreboot/master: b972fec Add EM100 mode to Intel Fir (24 May 22:22)
Patch merged into coreboot/master: 813532b chromeos: Fix compilation o (24 May 22:22)
make und Git: fatal: No names found, cannot describe anything. (24 May 22:09)
Patch merged into coreboot/master: cb5e566 Converted the FRAMEBUFFER_V (24 May 21:54)
Patch merged into coreboot/master: b071aa2 abuild: Disable abuild-leve (24 May 18:09)
Patch merged into coreboot/master: 6cf94df cbtypes.h: Unify cbtypes.h (24 May 17:38)
Patch set updated for coreboot: d75af2f Sandybridge: Fix MRC cache cal (24 May 09:46)
Patch set updated for coreboot: d03766d Drop config variable CPU_MODEL (24 May 09:46)
Patch set updated for coreboot: a3e04c2 Fix compilation with CONFIG_DE (24 May 09:46)
Patch set updated for coreboot: fe81ee8 Reduce default verbosity of SP (24 May 09:46)
Patch set updated for coreboot: 5e0503e Move subsystem IDs to devicetr (24 May 09:46)
Patch set updated for coreboot: 01b7d07 Implement %zu / %zd in printk (24 May 09:46)
Patch set updated for coreboot: 595f2fc Fix size_t for certain version (24 May 09:46)
Patch set updated for coreboot: fbcadbd Fix printk types in SPI flash (24 May 09:46)
Patch set updated for coreboot: bafd5dc ChromeOS: Remove remnants of F (24 May 09:46)

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