Sylvain Ageneau | 1 Feb 03:12 2010
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Re : Tinyscheme ported to coreboot/libpayload

Hello Stefan,

Ok, I get your point about the impossibility to merge some of dietlibc into libpayload.

But for purpose of using tinyscheme as a scripting language on top of coreboot, would the fact the interpreter's executable is linked against GPL code also make any scheme script using it necessarily GPL ?

In the patches I sent you, the dietlibc part is kept separate from libpayload. In any case, I'll see if I can remove the dietlibc dependency, I had actually started to implement some of the missing functions before I found out about dietlibc.

Regards,
Sylvain


De : Stefan Reinauer <stepan <at> coresystems.de>
À : coreboot <at> coreboot.org; sylvain_ageneau <at> yahoo.fr
Envoyé le : Dim 31 Janvier 2010, 11 h 12 min 27 s
Objet : Re: [coreboot] Tinyscheme ported to coreboot/libpayload

Dear Silvain,

On 1/31/10 1:34 PM, Sylvain Ageneau wrote:
Hello,

I'd like to announce that tinyscheme can now run as a coreboot payload.

TinyScheme is a lightweight Scheme interpreter that implements as large a subset of R5RS as was possible without getting very large and complicated. It is meant to be used as an embedded scripting interpreter for other programs. As such, it does not offer IDEs or extensive toolkits although it does sport a small top-level loop, included conditionally. A lot of functionality in TinyScheme is included conditionally, to allow developers freedom in balancing features and footprint. Programmatically, foreign functions in C can be added and values can be defined in the Scheme environment.
Thank you very much for your efforts.
The port was quite straightforward, most of the needed fonctionality needed was already in libpayload. It was probably possible to adapt tinyscheme to run on an unmodified libpayload but it didn't seem difficult to take the needed C functions from dietlibc (mostly stdio / math stuff) so I went that way instead (just needed to make some stubs for some low level functions like read/write). I don't know what your policy is with respect to integrating code from another GPL project but it looks like quite a bit of dietlibc could be easily integrated into libpayload. Some stuff uses syscalls and the like but other code doesn't require any fancy OS functionality.
Please note that libpayload is _not_ released under the GPL, but under the BSD license (just like tinyscheme, btw), so it can not share code with GPL projects.

Please also check http://www.coreboot.org/Development_Guidelines#How_to_contribute, especially the section on signing off patches. :-)

Best regards,

Stefan


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Peter Stuge | 1 Feb 04:38 2010
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Re: Re : Tinyscheme ported to coreboot/libpayload

Sylvain Ageneau wrote:
> But for purpose of using tinyscheme as a scripting language on top
> of coreboot, would the fact the interpreter's executable is linked
> against GPL code also make any scheme script using it necessarily
> GPL ?

What GPL code do you mean?

In any case, if you create a GPL payload out of
libpayload+dietlibc+tinyscheme then that is an interpreter, and any
code you execute using that interpreter can have a different license
since they are not, in fact, linked together.

> In the patches I sent you, the dietlibc part is kept separate from
> libpayload. In any case, I'll see if I can remove the dietlibc
> dependency, I had actually started to implement some of the missing
> functions before I found out about dietlibc.

That would be great. libpayload has already reused code from other
BSD-licensed projects, in particular HelenOS IIRC, so possibly you
can find another source of some of the code at least.

//Peter

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Peter Stuge | 1 Feb 05:21 2010
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Re: Request for Help/Information - Booting Linux Kernel (Embedded x86)

Graeme Russ wrote:
> A quick update - I think I'm getting even closer.

Did you get some traction on the mkelfImage path too?

> U-Boot had some primitive BIOS Interrupt Service Routines and a
> Real Mode bootstrap
..
> So far I have seen instances of IRQ15, IRQ16 and IRQ10

Sounds like the kernel is running then.

> Digging deeper...

arch/x86/boot/header.S calls arch/x86/boot/main.c

//Peter

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Ward Vandewege | 1 Feb 04:44 2010
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dell server BIOS setting insanity

Hi all,

I thought I'd point out this little gem from the linux-poweredge list

  http://lists.us.dell.com/pipermail/linux-poweredge/2010-January/041170.html  

Apparently several lines of Dell servers have a BIOS setting called
"Cores-per-processor".

It seems they ship these machines with the setting configured to 'dual',
regardless of what CPUs are in the system.

The poor guy who reported this to the list just took delivery of 300 of those
machines - with quad core CPUs. They show up as dual core until he goes into
the BIOS and changes the setting. That's also the 'official' solution for the
problem from the Dell rep.

Seriously.

Thanks,
Ward.

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Peter Stuge | 1 Feb 05:51 2010
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Re: dell server BIOS setting insanity

Ward Vandewege wrote:
> 300 of those machines - with quad core CPUs. They show up as dual
> core until he goes into the BIOS and changes the setting. That's
> also the 'official' solution for the problem from the Dell rep.

Ask him to come to IRC. If really lucky it will be faster to create a
program for it. But my guess is that it will be quicker to walk
around and change the setting.

//Peter

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ron minnich | 1 Feb 06:05 2010
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Re: dell server BIOS setting insanity

Do you know if it is in CMOS or FLASH? I could not tell.

If in CMOS it's trivial to script and they're going to want that
script, because in the typical factory BIOS these settings have a way
of "reverting to default", which is why we once had 4600 nodes come up
and want a keyboard to be attached; they forgot that we'd told them
there were no keyboards.  ... and those are hardly the only nodes
we've seen the problem on over the last 10 years.

ron

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Carl-Daniel Hailfinger | 1 Feb 06:00 2010
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Re: dell server BIOS setting insanity

On 01.02.2010 04:44, Ward Vandewege wrote:
> I thought I'd point out this little gem from the linux-poweredge list
>
>   http://lists.us.dell.com/pipermail/linux-poweredge/2010-January/041170.html  
>
> Apparently several lines of Dell servers have a BIOS setting called
> "Cores-per-processor".
>
> It seems they ship these machines with the setting configured to 'dual',
> regardless of what CPUs are in the system.
>
> The poor guy who reported this to the list just took delivery of 300 of those
> machines - with quad core CPUs. They show up as dual core until he goes into
> the BIOS and changes the setting. That's also the 'official' solution for the
> problem from the Dell rep.
>
> Seriously.
>   

You must be kidding. I mean, if Dell declare this to be a "feature",
they could go all the way to set the CPUs to single-core.
Poor users.

I envision a new option in Dell order forms: "Apply correct BIOS
settings. $25"

Anyway, could you ask the guy to dump with nvramtool before and after
the settings change? Maybe the settings live in NVRAM. That would make
it scriptable.

Regards,
Carl-Daniel

-- 
Developer quote of the year:
"We are juggling too many chainsaws and flaming arrows and tigers."

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Joseph Smith | 1 Feb 07:48 2010

[PATCH] Intel 82830 overhaul

Hello,
Attached is major overhaul to the 82830 raminit. Alot of it is trivial 
clean ups. With on major change. The i830 is now able to initialize one 
row (side) of memory at a time (this is the way it is supposed to be 
done). See bootlog snip below (shows 512MB double sided SO-DIMM in 
socket 1 and 64MB single sided onboard memory) and attached patch.

Signed-off-by: Joseph Smith <joe <at> settoplinux.org>

coreboot-2.3" Sun Jan 31 23:42:28 EST 2010 starting...
SMBus controller enabled
Setting initial sdram registers....
Found DIMM in slot 00
DIMM is 0x0100 on side 1
DIMM is 0x0100 on side 2
DRB 0x60 has been set to 0x08
DRB1 0x61 has been set to 0x10
Found DIMM in slot 01
DIMM is 0x0040 on side 1
DIMM is 0x0000 on side 2
DRB2 0x62 has been set to 0x12
DRB3 0x63 has been set to 0x12
Found DIMM in slot 00, setting DRA...
DRA 0x70 has been set to 0x22
Found DIMM in slot 01, setting DRA...
DRA 0x71 has been set to 0xf1
Initial sdram registers have been set.
Initializing SDRAM Row 00
  NOP RAM command 0x00000010
   Sending RAM command to 0x00000000
  Pre-charging all banks RAM command 0x00000020
   Sending RAM command to 0x00000000
  8 CBR refreshes RAM command 0x00000060
   Sending RAM command to 0x00000000
RAM command 0x00000060
   Sending RAM command to 0x00000000
RAM command 0x00000060
   Sending RAM command to 0x00000000
RAM command 0x00000060
   Sending RAM command to 0x00000000
RAM command 0x00000060
   Sending RAM command to 0x00000000
RAM command 0x00000060
   Sending RAM command to 0x00000000
RAM command 0x00000060
   Sending RAM command to 0x00000000
RAM command 0x00000060
   Sending RAM command to 0x00000000
  MRS RAM command 0x00000030
   Sending RAM command to 0x000001d0
  Normal operation mode RAM command 0x00000070
   Sending RAM command to 0x00000000
  Performing dummy read/write
   Reading RAM at 0x00000000 => 0x3e5e556c
   Writing RAM at 0x00000000 <= 0x55aa55aa
   Reading RAM at 0x00000000 => 0x55aa55aa
Initializing SDRAM Row 01
  NOP RAM command 0x00000010
   Sending RAM command to 0x10000000
  Pre-charging all banks RAM command 0x00000020
   Sending RAM command to 0x10000000
  8 CBR refreshes RAM command 0x00000060
   Sending RAM command to 0x10000000
RAM command 0x00000060
   Sending RAM command to 0x10000000
RAM command 0x00000060
   Sending RAM command to 0x10000000
RAM command 0x00000060
   Sending RAM command to 0x10000000
RAM command 0x00000060
   Sending RAM command to 0x10000000
RAM command 0x00000060
   Sending RAM command to 0x10000000
RAM command 0x00000060
   Sending RAM command to 0x10000000
RAM command 0x00000060
   Sending RAM command to 0x10000000
  MRS RAM command 0x00000030
   Sending RAM command to 0x100001d0
  Normal operation mode RAM command 0x00000070
   Sending RAM command to 0x10000000
  Performing dummy read/write
   Reading RAM at 0x10000000 => 0x55abf7aa
   Writing RAM at 0x10000000 <= 0x55aa55aa
   Reading RAM at 0x10000000 => 0x55aa55aa
Initializing SDRAM Row 02
  NOP RAM command 0x00000010
   Sending RAM command to 0x20000000
  Pre-charging all banks RAM command 0x00000020
   Sending RAM command to 0x20000000
  8 CBR refreshes RAM command 0x00000060
   Sending RAM command to 0x20000000
RAM command 0x00000060
   Sending RAM command to 0x20000000
RAM command 0x00000060
   Sending RAM command to 0x20000000
RAM command 0x00000060
   Sending RAM command to 0x20000000
RAM command 0x00000060
   Sending RAM command to 0x20000000
RAM command 0x00000060
   Sending RAM command to 0x20000000
RAM command 0x00000060
   Sending RAM command to 0x20000000
RAM command 0x00000060
   Sending RAM command to 0x20000000
  MRS RAM command 0x00000030
   Sending RAM command to 0x200001d0
  Normal operation mode RAM command 0x00000070
   Sending RAM command to 0x20000000
  Performing dummy read/write
   Reading RAM at 0x20000000 => 0x55ba55aa
   Writing RAM at 0x20000000 <= 0x55aa55aa
   Reading RAM at 0x20000000 => 0x55aa55aa
Enabling Refresh
Setting initialization complete
Setting initial nothbridge registers....
Initial northbridge registers have been set.
Northbridge following SDRAM init:
PCI: 00:00.00
00: 86 80 75 35 06 00 10 00 04 00 00 06 00 00 00 00
10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
40: 09 00 05 01 00 00 00 00 00 00 00 00 02 28 00 0e
50: 72 a0 40 00 00 00 00 00 00 30 33 33 33 33 33 33
60: 08 10 12 12 12 12 00 00 00 00 00 00 00 00 00 00
70: 22 f1 ff ff 00 00 00 00 10 00 00 00 70 01 00 20
80: 00 00 00 00 00 00 00 00 80 60 33 01 00 00 00 00
90: 02 38 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 02 00 20 00 17 02 00 1f 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 54 0e 41 a2 99 01 00 c0 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 1b 49 9b fc
f0: 11 11 01 00 00 00 0b 05 35 d0 2c cf 1f cd 1d cc
Copying coreboot to RAM.
Loading stage image.
Check CBFS header at fffeffe0
magic is 4f524243
Found CBFS header at fffeffe0
Check fallback/coreboot_ram
Stage: loading fallback/coreboot_ram  <at>  0x100000 (147456 bytes), entry  <at>  
0x100000
Stage: done loading.
Jumping to image.
coreboot-2.3 Sun Jan 31 23:42:28 EST 2010 booting...

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
Index: src/mainboard/thomson/ip1000/auto.c
===================================================================
--- src/mainboard/thomson/ip1000/auto.c	(revision 5069)
+++ src/mainboard/thomson/ip1000/auto.c	(working copy)
 <at>  <at>  -69,7 +69,6  <at>  <at> 
 }

 #include "northbridge/intel/i82830/raminit.c"
-#include "lib/generic_sdram.c"

 /**
  * Setup mainboard specific registers pre raminit.
 <at>  <at>  -103,13 +102,6  <at>  <at> 

 static void main(unsigned long bist)
 {
-	static const struct mem_controller memctrl[] = {
-		{
-			.d0 = PCI_DEV(0, 0, 0),
-			.channel0 = {0x50, 0x51},
-		}
-	};
-
 	if (bist == 0)
 		early_mtrr_init();
 		if (memory_initialized()) {
 <at>  <at>  -129,10 +121,8  <at>  <at> 
 	/* Setup mainboard specific registers */
 	mb_early_setup();

-	/* SDRAM init */
-	sdram_set_registers(memctrl);
-	sdram_set_spd_registers(memctrl);
-	sdram_enable(0, memctrl);
+	/* Initialize memory */
+	sdram_initialize();

 	/* Check RAM. */
 	/* ram_check(0, 640 * 1024); */
Index: src/mainboard/rca/rm4100/auto.c
===================================================================
--- src/mainboard/rca/rm4100/auto.c	(revision 5069)
+++ src/mainboard/rca/rm4100/auto.c	(working copy)
 <at>  <at>  -69,7 +69,6  <at>  <at> 
 }

 #include "northbridge/intel/i82830/raminit.c"
-#include "lib/generic_sdram.c"

 /**
  * Setup mainboard specific registers pre raminit.
 <at>  <at>  -103,13 +102,6  <at>  <at> 

 static void main(unsigned long bist)
 {
-	static const struct mem_controller memctrl[] = {
-		{
-			.d0 = PCI_DEV(0, 0, 0),
-			.channel0 = {0x50, 0x51},
-		}
-	};
-
 	if (bist == 0)
 		early_mtrr_init();
 		if (memory_initialized()) {
 <at>  <at>  -129,10 +121,8  <at>  <at> 
 	/* Setup mainboard specific registers */
 	mb_early_setup();

-	/* SDRAM init */
-	sdram_set_registers(memctrl);
-	sdram_set_spd_registers(memctrl);
-	sdram_enable(0, memctrl);
+	/* Initialize memory */
+	sdram_initialize();

 	/* Check RAM. */
 	/* ram_check(0, 640 * 1024); */
Index: src/northbridge/intel/i82830/raminit.c
===================================================================
--- src/northbridge/intel/i82830/raminit.c	(revision 5069)
+++ src/northbridge/intel/i82830/raminit.c	(working copy)
 <at>  <at>  -1,7 +1,7  <at>  <at> 
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008 Joseph Smith <joe <at> smittys.pointclark.net>
+ * Copyright (C) 2008-2010 Joseph Smith <joe <at> settoplinux.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
 <at>  <at>  -67,41 +67,122  <at>  <at> 
 #define RAM_COMMAND_IC			0x1

 /*-----------------------------------------------------------------------------
-SDRAM configuration functions.
+DIMM-initialization functions.
 -----------------------------------------------------------------------------*/

-/* Send the specified RAM command to all DIMMs. */
-
-static void do_ram_command(const struct mem_controller *ctrl, uint32_t command,
-			   uint32_t addr_offset)
+static void do_ram_command(uint32_t command)
 {
-	int i;
-	uint8_t dimm_start, dimm_end;
 	uint32_t reg32;

 	/* Configure the RAM command. */
-	reg32 = pci_read_config32(ctrl->d0, DRC);
+	reg32 = pci_read_config32(NORTHBRIDGE, DRC);
 	/* Clear bits 29, 10-8, 6-4. */
 	reg32 &= 0xdffff88f;
 	reg32 |= command << 4;
-	pci_write_config32(ctrl->d0, DRC, reg32);
+	pci_write_config32(NORTHBRIDGE, DRC, reg32);
+	PRINT_DEBUG("RAM command 0x");
+	PRINT_DEBUG_HEX32(reg32);
+	PRINT_DEBUG("\r\n");
+}

-	/* Send the ram command to each row of memory.
-	 * (DIMM_SOCKETS * 2) is the maximum number of rows possible.
-	 * Note: Each DRB defines the upper boundary address of 
-	 * each SDRAM row in 32-MB granularity.
-	 */
+static void ram_read32(uint8_t dimm_start, uint32_t offset)
+{
+	if (offset == 0x55aa55aa) {
+		PRINT_DEBUG("  Reading RAM at 0x");
+		PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024);
+		PRINT_DEBUG(" => 0x");
+		PRINT_DEBUG_HEX32(read32(dimm_start * 32 * 1024 * 1024));
+		PRINT_DEBUG("\r\n");
+
+		PRINT_DEBUG("  Writing RAM at 0x");
+		PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024);
+		PRINT_DEBUG(" <= 0x");
+		PRINT_DEBUG_HEX32(offset);
+		PRINT_DEBUG("\r\n");
+		write32(dimm_start * 32 * 1024 * 1024, offset);
+
+		PRINT_DEBUG("  Reading RAM at 0x");
+		PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024);
+		PRINT_DEBUG(" => 0x");
+		PRINT_DEBUG_HEX32(read32(dimm_start * 32 * 1024 * 1024));
+		PRINT_DEBUG("\r\n");
+	} else {
+		PRINT_DEBUG("  Sending RAM command to 0x");
+		PRINT_DEBUG_HEX32((dimm_start * 32 * 1024 * 1024) + offset);
+		PRINT_DEBUG("\r\n");
+		read32((dimm_start * 32 * 1024 * 1024) + offset);
+	}
+}
+
+static void initialize_dimm_rows(void)
+{
+	int i, row;
+	uint8_t dimm_start, dimm_end;
+	unsigned device;
+
 	dimm_start = 0;

-	for (i = 0; i < (DIMM_SOCKETS * 2); i++) {
-		dimm_end = pci_read_config8(ctrl->d0, DRB + i);
+	for (row = 0; row < (DIMM_SOCKETS * 2); row++) {
+
+		switch (row) {
+			case 0:
+				device = DIMM_SPD_BASE;
+				break;
+			case 1:
+				device = DIMM_SPD_BASE;
+				break;
+			case 2:
+				device = DIMM_SPD_BASE + 1;
+				break;
+			case 3:
+				device = DIMM_SPD_BASE + 1;
+				break;
+		}
+
+		dimm_end = pci_read_config8(NORTHBRIDGE, DRB + row);
+
 		if (dimm_end > dimm_start) {
-			PRINT_DEBUG("    Sending RAM command 0x");
-			PRINT_DEBUG_HEX32(reg32);
-			PRINT_DEBUG(" to 0x");
-			PRINT_DEBUG_HEX32((dimm_start * 32 * 1024 * 1024) + addr_offset);
-			PRINT_DEBUG("\r\n");
-			read32((dimm_start * 32 * 1024 * 1024) + addr_offset);
+			print_debug("Initializing SDRAM Row ");
+			print_debug_hex8(row);
+			print_debug("\r\n");
+
+			/* NOP command */
+			PRINT_DEBUG(" NOP ");
+			do_ram_command(RAM_COMMAND_NOP);
+			ram_read32(dimm_start, 0);
+			udelay(200);
+
+			/* Pre-charge all banks (at least 200 us after NOP) */
+			PRINT_DEBUG(" Pre-charging all banks ");
+			do_ram_command(RAM_COMMAND_PRECHARGE);
+			ram_read32(dimm_start, 0);
+			udelay(1);
+
+			/* 8 CBR refreshes (Auto Refresh) */
+			PRINT_DEBUG(" 8 CBR refreshes ");
+			for (i = 0; i < 8; i++) {
+				do_ram_command(RAM_COMMAND_CBR);
+				ram_read32(dimm_start, 0);
+				udelay(1);
+			}
+
+			/* MRS command */
+			/* TODO: Set offset 0x1d0 according to DRT values */
+			PRINT_DEBUG(" MRS ");
+			do_ram_command(RAM_COMMAND_MRS);
+			ram_read32(dimm_start, 0x1d0);
+			udelay(2);
+
+			/* Set GMCH-M Mode Select bits back to NORMAL operation mode */
+			PRINT_DEBUG(" Normal operation mode ");
+			do_ram_command(RAM_COMMAND_NORMAL);
+			ram_read32(dimm_start, 0);
+			udelay(1);
+
+			/* Perform a dummy memory read/write cycle */
+			PRINT_DEBUG(" Performing dummy read/write\r\n");
+			ram_read32(dimm_start, 0x55aa55aa);
+			udelay(1);
 		}
 		/* Set the start of the next DIMM. */
 		dimm_start = dimm_end;
 <at>  <at>  -122,8 +203,8  <at>  <at> 
 	struct dimm_size sz;
 	int i, module_density, dimm_banks;
 	sz.side1 = 0;
-	module_density = spd_read_byte(device, 31);
-	dimm_banks = spd_read_byte(device, 5);
+	module_density = spd_read_byte(device, SPD_DENSITY_OF_EACH_ROW_ON_MODULE);
+	dimm_banks = spd_read_byte(device, SPD_NUM_DIMM_BANKS);

 	/* Find the size of side1. */
 	/* Find the larger value. The larger value is always side1. */
 <at>  <at>  -163,19 +244,19  <at>  <at> 
 	return sz;
 }

-static void spd_set_dram_size(const struct mem_controller *ctrl)
+static void set_dram_row_boundaries(void)
 {
 	int i, value, drb1, drb2;

 	for (i = 0; i < DIMM_SOCKETS; i++) {
 		struct dimm_size sz;
 		unsigned device;
-		device = ctrl->channel0[i];
+		device = DIMM_SPD_BASE + i;
 		drb1 = 0;
 		drb2 = 0;

 		/* First check if a DIMM is actually present. */
-		if (spd_read_byte(device, 2) == 0x4) {
+		if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {
 			print_debug("Found DIMM in slot ");
 			print_debug_hex8(i);
 			print_debug("\r\n");
 <at>  <at>  -190,14 +271,15  <at>  <at> 
 			print_debug_hex16(sz.side2);
 			print_debug(" on side 2\r\n");

+			/* - Memory compatibility checks - */
 			/* Test for PC133 (i82830 only supports PC133) */
 			/* PC133 SPD9 - cycle time is always 75 */
-			if (spd_read_byte(device, 9) != 0x75) {
+			if (spd_read_byte(device, SPD_MIN_CYCLE_TIME_AT_CAS_MAX) != 0x75) {
 				print_err("SPD9 DIMM Is Not PC133 Compatable\r\n");
 				die("HALT\r\n");
 			}
 			/* PC133 SPD10 - access time is always 54 */
-			if (spd_read_byte(device, 10) != 0x54) {
+			if (spd_read_byte(device, SPD_ACCESS_TIME_FROM_CLOCK) != 0x54) {
 				print_err("SPD10 DIMM Is Not PC133 Compatable\r\n");
 				die("HALT\r\n");
 			}
 <at>  <at>  -225,6 +307,7  <at>  <at> 
 				    ("are not supported on this northbridge\r\n");
 				die("HALT\r\n");
 			}
+			/* - End Memory compatibility checks - */

 			/* We need to divide size by 32 to set up the
 			 * DRB registers.
 <at>  <at>  -244,8 +327,8  <at>  <at> 
 		}
 		/* Set the value for DRAM Row Boundary Registers */
 		if (i == 0) {
-			pci_write_config8(ctrl->d0, DRB, drb1);
-			pci_write_config8(ctrl->d0, DRB + 1, drb1 + drb2);
+			pci_write_config8(NORTHBRIDGE, DRB, drb1);
+			pci_write_config8(NORTHBRIDGE, DRB + 1, drb1 + drb2);
 			PRINT_DEBUG("DRB 0x");
 			PRINT_DEBUG_HEX8(DRB);
 			PRINT_DEBUG(" has been set to 0x");
 <at>  <at>  -257,10 +340,9  <at>  <at> 
 			PRINT_DEBUG_HEX8(drb1 + drb2);
 			PRINT_DEBUG("\r\n");
 		} else if (i == 1) {
-			value = pci_read_config8(ctrl->d0, DRB + 1);
-			pci_write_config8(ctrl->d0, DRB + 2, value + drb1);
-			pci_write_config8(ctrl->d0, DRB + 3,
-					  value + drb1 + drb2);
+			value = pci_read_config8(NORTHBRIDGE, DRB + 1);
+			pci_write_config8(NORTHBRIDGE, DRB + 2, value + drb1);
+			pci_write_config8(NORTHBRIDGE, DRB + 3, value + drb1 + drb2);
 			PRINT_DEBUG("DRB2 0x");
 			PRINT_DEBUG_HEX8(DRB + 2);
 			PRINT_DEBUG(" has been set to 0x");
 <at>  <at>  -276,23 +358,23  <at>  <at> 
 			 * These are supposed to be "Reserved" but memory will
 			 * not initialize properly if we don't.
 			 */
-			value = pci_read_config8(ctrl->d0, DRB + 3);
-			pci_write_config8(ctrl->d0, DRB + 4, value);
-			pci_write_config8(ctrl->d0, DRB + 5, value);
+			value = pci_read_config8(NORTHBRIDGE, DRB + 3);
+			pci_write_config8(NORTHBRIDGE, DRB + 4, value);
+			pci_write_config8(NORTHBRIDGE, DRB + 5, value);
 		}
 	}
 }

-static void set_dram_row_attributes(const struct mem_controller *ctrl)
+static void set_dram_row_attributes(void)
 {
 	int i, dra, col, width, value;

 	for (i = 0; i < DIMM_SOCKETS; i++) {
 		unsigned device;
-		device = ctrl->channel0[i];
+		device = DIMM_SPD_BASE + i;

 		/* First check if a DIMM is actually present. */
-		if (spd_read_byte(device, 2) == 0x4) {
+		if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) {
 			print_debug("Found DIMM in slot ");
 			print_debug_hex8(i);
 			print_debug(", setting DRA...\r\n");
 <at>  <at>  -300,10 +382,10  <at>  <at> 
 			dra = 0x00;

 			/* columns */
-			col = spd_read_byte(device, 4);
+			col = spd_read_byte(device, SPD_NUM_COLUMNS);

 			/* data width */
-			width = spd_read_byte(device, 6);
+			width = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB);

 			/* calculate page size in bits */
 			value = ((1 << col) * width);
 <at>  <at>  -312,7 +394,7  <at>  <at> 
 			dra = ((value / 8) >> 10);

 			/* # of banks of DIMM (single or double sided) */
-			value = spd_read_byte(device, 5);
+			value = spd_read_byte(device, SPD_NUM_DIMM_BANKS);

 			if (value == 1) {
 				if (dra == 2) {
 <at>  <at>  -355,7 +437,7  <at>  <at> 
 		}

 		/* Set the value for DRAM Row Attribute Registers */
-		pci_write_config8(ctrl->d0, DRA + i, dra);
+		pci_write_config8(NORTHBRIDGE, DRA + i, dra);
 		PRINT_DEBUG("DRA 0x");
 		PRINT_DEBUG_HEX8(DRA + i);
 		PRINT_DEBUG(" has been set to 0x");
 <at>  <at>  -364,14 +446,14  <at>  <at> 
 	}
 }

-static void set_dram_timing(const struct mem_controller *ctrl)
+static void set_dram_timing(void)
 {
 	/* Set the value for DRAM Timing Register */
 	/* TODO: Configure the value according to SPD values. */
-	pci_write_config32(ctrl->d0, DRT, 0x00000010);
+	pci_write_config32(NORTHBRIDGE, DRT, 0x00000010);
 }

-static void set_dram_buffer_strength(const struct mem_controller *ctrl)
+static void set_dram_buffer_strength(void)
 {
 	/* TODO: This needs to be set according to the DRAM tech
 	 * (x8, x16, or x32). Argh, Intel provides no docs on this!
 <at>  <at>  -380,23 +462,62  <at>  <at> 
 	 */

 	/* Set the value for System Memory Buffer Strength Control Registers */
-	pci_write_config32(ctrl->d0, BUFF_SC, 0xFC9B491B);
+	pci_write_config32(NORTHBRIDGE, BUFF_SC, 0xFC9B491B);
 }

 /*-----------------------------------------------------------------------------
 Public interface.
 -----------------------------------------------------------------------------*/

-static void sdram_set_registers(const struct mem_controller *ctrl)
+static void sdram_set_registers(void)
 {
+	PRINT_DEBUG("Setting initial sdram registers....\r\n");
+
+	/* Calculate the value for DRT DRAM Timing Register */
+	set_dram_timing();
+
+	/* Setup System Memory Buffer Strength Control Registers */
+	set_dram_buffer_strength();
+
+	/* Setup DRAM Row Boundary Registers */
+	set_dram_row_boundaries();
+
+	/* Setup DRAM Row Attribute Registers */
+	set_dram_row_attributes();
+
+	PRINT_DEBUG("Initial sdram registers have been set.\r\n");
+}
+
+static void northbridge_set_registers(void)
+{
 	uint16_t value;
 	int igd_memory = 0;

-	PRINT_DEBUG("Setting initial registers....\r\n");
+	PRINT_DEBUG("Setting initial nothbridge registers....\r\n");

+	/* Set the value for Fixed DRAM Hole Control Register */
+	pci_write_config8(NORTHBRIDGE, FDHC, 0x00);
+
+	/* Set the value for Programable Attribute Map Registers
+	 * Ideally, this should be R/W for as many ranges as possible.
+	 */
+	pci_write_config8(NORTHBRIDGE, PAM0, 0x30);
+	pci_write_config8(NORTHBRIDGE, PAM1, 0x33);
+	pci_write_config8(NORTHBRIDGE, PAM2, 0x33);
+	pci_write_config8(NORTHBRIDGE, PAM3, 0x33);
+	pci_write_config8(NORTHBRIDGE, PAM4, 0x33);
+	pci_write_config8(NORTHBRIDGE, PAM5, 0x33);
+	pci_write_config8(NORTHBRIDGE, PAM6, 0x33);
+
+	/* Set the value for System Management RAM Control Register */
+	pci_write_config8(NORTHBRIDGE, SMRAM, 0x02);
+
 	/* Set the value for GMCH Control Register #0 */
-	pci_write_config16(ctrl->d0, GCC0, 0xA072);
+	pci_write_config16(NORTHBRIDGE, GCC0, 0xA072);

+	/* Set the value for Aperture Base Configuration Register */
+	pci_write_config32(NORTHBRIDGE, APBASE, 0x00000008);
+
 	/* Set the value for GMCH Control Register #1 */
 	switch (CONFIG_VIDEO_MB) {
 	case 512: /* 512K of memory */
 <at>  <at>  -409,96 +530,46  <at>  <at> 
 		igd_memory = 0x4;
 		break;
 	default: /* No memory */
-		pci_write_config16(ctrl->d0, GCC1, 0x0002);
+		pci_write_config16(NORTHBRIDGE, GCC1, 0x0002);
 		igd_memory = 0x0;
 	}

-	value = pci_read_config16(ctrl->d0, GCC1);
+	value = pci_read_config16(NORTHBRIDGE, GCC1);
 	value |= igd_memory << 4;
-	pci_write_config16(ctrl->d0, GCC1, value);
+	pci_write_config16(NORTHBRIDGE, GCC1, value);

-	/* Set the value for Aperture Base Configuration Register */
-	pci_write_config32(ctrl->d0, APBASE, 0x00000008);
-
-	/* Set the value for Register Range Base Address Register */
-	pci_write_config32(ctrl->d0, RRBAR, 0x00000000);
-
-	/* Set the value for Fixed DRAM Hole Control Register */
-	pci_write_config8(ctrl->d0, FDHC, 0x00);
-
-	/* Set the value for Programable Attribute Map Registers
-	 * Ideally, this should be R/W for as many ranges as possible.
-	 */
-	pci_write_config8(ctrl->d0, PAM0, 0x30);
-	pci_write_config8(ctrl->d0, PAM1, 0x33);
-	pci_write_config8(ctrl->d0, PAM2, 0x33);
-	pci_write_config8(ctrl->d0, PAM3, 0x33);
-	pci_write_config8(ctrl->d0, PAM4, 0x33);
-	pci_write_config8(ctrl->d0, PAM5, 0x33);
-	pci_write_config8(ctrl->d0, PAM6, 0x33);
-
-	/* Set the value for DRAM Throttling Control Register */
-	pci_write_config32(ctrl->d0, DTC, 0x00000000);
-
-	/* Set the value for System Management RAM Control Register */
-	pci_write_config8(ctrl->d0, SMRAM, 0x02);
-
-	/* Set the value for Extended System Management RAM Control Register */
-	pci_write_config8(ctrl->d0, ESMRAMC, 0x38);
-
-	PRINT_DEBUG("Initial registers have been set.\r\n");
+	PRINT_DEBUG("Initial northbridge registers have been set.\r\n");
 }

-static void sdram_set_spd_registers(const struct mem_controller *ctrl)
+static void sdram_initialize(void)
 {
-	spd_set_dram_size(ctrl);
-	set_dram_row_attributes(ctrl);
-	set_dram_timing(ctrl);
-	set_dram_buffer_strength(ctrl);
-}
-
-static void sdram_enable(int controllers, const struct mem_controller *ctrl)
-{
 	int i;
 	uint32_t reg32;

+	/* Setup Initial SDRAM Registers */
+	sdram_set_registers();
+
 	/* 0. Wait until power/voltages and clocks are stable (200us). */
 	udelay(200);

-	/* 1. Apply NOP. */
-	PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
-	do_ram_command(ctrl, RAM_COMMAND_NOP, 0);
-	udelay(200);
+	/* Initialize each row of memory one at a time */
+	initialize_dimm_rows();

-	/* 2. Precharge all. Wait tRP. */
-	PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
-	do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0);
-	udelay(1);
+	/* Enable Refresh */
+	PRINT_DEBUG("Enabling Refresh\r\n");
+	reg32 = pci_read_config32(NORTHBRIDGE, DRC);
+	reg32 |= (RAM_COMMAND_REFRESH << 8);
+	pci_write_config32(NORTHBRIDGE, DRC, reg32);

-	/* 3. Perform 8 refresh cycles. Wait tRC each time. */
-	PRINT_DEBUG("RAM Enable 3: CBR\r\n");
-	for (i = 0; i < 8; i++) {
-		do_ram_command(ctrl, RAM_COMMAND_CBR, 0);
-		udelay(1);
-	}
+	/* Set initialization complete */
+	PRINT_DEBUG("Setting initialization complete\r\n");
+	reg32 = pci_read_config32(NORTHBRIDGE, DRC);
+	reg32 |= (RAM_COMMAND_IC << 29);
+	pci_write_config32(NORTHBRIDGE, DRC, reg32);

-	/* 4. Mode register set. Wait two memory cycles. */
-	/* TODO: Set offset according to DRT values */
-	PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
-	do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0);
-	udelay(2);
+	/* Setup Initial Northbridge Registers */
+	northbridge_set_registers();

-	/* 5. Normal operation (enables refresh) */
-	PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
-	do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0);
-	udelay(1);
-
-	/* 6. Enable refresh and Set initialization complete. */
-	PRINT_DEBUG("RAM Enable 6: Enable Refresh and IC\r\n");
-	reg32 = pci_read_config32(ctrl->d0, DRC);
-	reg32 |= ((RAM_COMMAND_REFRESH << 8) | (RAM_COMMAND_IC << 29));
-	pci_write_config32(ctrl->d0, DRC, reg32);
-
 	PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
 	DUMPNORTH();
 }
Index: src/northbridge/intel/i82830/raminit.h
===================================================================
--- src/northbridge/intel/i82830/raminit.h	(revision 5069)
+++ src/northbridge/intel/i82830/raminit.h	(working copy)
 <at>  <at>  -1,7 +1,7  <at>  <at> 
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2008 Joseph Smith <joe <at> smittys.pointclark.net>
+ * Copyright (C) 2008-2010 Joseph Smith <joe <at> settoplinux.org>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
 <at>  <at>  -21,12 +21,13  <at>  <at> 
 #ifndef NORTHBRIDGE_INTEL_I82830_RAMINIT_H
 #define NORTHBRIDGE_INTEL_I82830_RAMINIT_H

+/* 82830 Northbridge PCI device */
+#define NORTHBRIDGE	PCI_DEV(0, 0, 0)
+
 /* The 82830 supports max. 2 dual-sided SO-DIMMs. */
 #define DIMM_SOCKETS	2

-struct mem_controller {
-	device_t d0;
-	uint16_t channel0[DIMM_SOCKETS];
-};
+/* DIMM0 is at 0x50, DIMM1 is at 0x51. */
+#define DIMM_SPD_BASE	0x50

 #endif /* NORTHBRIDGE_INTEL_I82830_RAMINIT_H */
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Stefan Reinauer | 1 Feb 11:01 2010
Picon

Re: dell server BIOS setting insanity

On 2/1/10 5:51 AM, Peter Stuge wrote:
> Ward Vandewege wrote:
>   
>> 300 of those machines - with quad core CPUs. They show up as dual
>> core until he goes into the BIOS and changes the setting. That's
>> also the 'official' solution for the problem from the Dell rep.
>>     
> Ask him to come to IRC. If really lucky it will be faster to create a
> program for it. But my guess is that it will be quicker to walk
> around and change the setting.
>   
That program might already exist: nvramtool

Usage: nvramtool [-y LAYOUT_FILE | -t] PARAMETER ...
[..]
-b OUTPUT_FILE: Dump CMOS memory contents to file.
-B INPUT_FILE: Write file contents to CMOS memory.
-x: Show hex dump of CMOS memory.
-X DUMPFILE: Show hex dump of CMOS dumpfile.
[..]

Change the setting on one machine, dump CMOS to a file, and write that
CMOS file back on the other machines.

Stefan

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      Tel.: +49 761 7668825 • Fax: +49 761 7664613
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Knut Kujat | 1 Feb 11:51 2010
Picon

CB won't boot with changed folder name.

Hi,

I'm still trying to get a working copy for the coreboot tree of my H8QME
supermicro board. The board still got some issues to be resolved but not
preventing it form booting and from working quiet stable (15 hours
mPrime (Prime 95) no failures or warnings). But as I commented earlier
when I was working to get the board booting I was always in the folder
of the board I was porting from (/supermicro/h8dmr_fam10). Now to be
able to send in a valid patch I need to create a new folder and copy all
the files in it. So here is what I did:

at /src/supermicro/
mkdir h8qme_fam10
cp h8dmr_fam10/* h8qme_fam10/

at /targets/supermicro(
mkdir h8qme_fam10
cp h8dmr_fam10/* h8qme_fam10/

changed Config.lb in targets/supermicro/h8qme_fam10

I compiled it without any problems I flashed it and then started the
machine, so now two things usually happen; it reboots or it halts.

I'm so sorry to bother you guys with such a thing but I'm not able to
make it work and I'm now really curious about what could probably cause
such a strange behavior.  

Thanks,
Knut Kujat

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