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Jakob Bornecrantz | 1 Jul 01:11
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Re: [PATCH] Changes for DLP 1232H external programer to Flashrom

On Mon, Jun 29, 2009 at 2:19 PM, Carl-Daniel
Hailfinger<c-d.hailfinger.devel.2006 <at> gmx.net> wrote:
> On 27.06.2009 13:43, Jakob Bornecrantz wrote:
>> These are the changes I had to do the flashrom to get my in circuit
>> programer working. Not much as you can see.
>
> Alternative patch which allows runtime selection of FT2232H/FT4232H and
> interface A/B.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 <at> gmx.net>

[SNIP]

Tested it works well.

Acked-by: Jakob Bornecrantz <wallbraker <at> gmail.com>
Tested-by: Jakob Bornecrantz <wallbraker <at> gmail.com>

Cheers Jakob.

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Kevin O'Connor | 1 Jul 01:40

Re: Intel Eagle Height evaluation board support

On Tue, Jun 30, 2009 at 09:10:46AM +0200, Thomas JOURDAN wrote:
> My mistake ! Seabios run the VGA bios of the matrox graphics card
> flawless. When I tried seabios, the coreboot Options.lb file of my
> mainboard wasn't correct. I set :
> default CONFIG_VGA_ROM_RUN=0
> default CONFIG_PCI_ROM_RUN=0
> but also (and that was my mistake)
> default CONFIG_CONSOLE_VGA=0

That's odd - I didn't think these coreboot options had any impact to
SeaBIOS either.  As a guess, coreboot is initializing some hardware
only when the CONFIG_CONSOLE_VGA option is set.

-Kevin

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Carl-Daniel Hailfinger | 1 Jul 02:03
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Re: [PATCH] Changes for DLP 1232H external programer to Flashrom

On 01.07.2009 01:11, Jakob Bornecrantz wrote:
> On Mon, Jun 29, 2009 at 2:19 PM, Carl-Daniel
> Hailfinger<c-d.hailfinger.devel.2006 <at> gmx.net> wrote:
>   
>> allows runtime selection of FT2232H/FT4232H and
>> interface A/B.
>>
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 <at> gmx.net>
>>     
>
> Acked-by: Jakob Bornecrantz <wallbraker <at> gmail.com>
> Tested-by: Jakob Bornecrantz <wallbraker <at> gmail.com>
>   

Thanks, committed in r638.

Regards,
Carl-Daniel

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Carl-Daniel Hailfinger | 1 Jul 02:28
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[ANNOUNCE] Upcoming Flashrom Mailing List and IRC splitoff

Dear list participants,

flashrom has grown up to a point where it is large and vital enough to
live in its own home. To accommodate flashrom's new independence, the
#coreboot IRC channel on irc.freenode.net and the coreboot <at> coreboot.org
mailing list will be split in two.

New mailing list structure:
flashrom <at> flashrom.org is where flashrom development and usage will be
discussed.
coreboot <at> coreboot.org will carry all traffic not related to flashrom.
coreboot <at> coreboot.org list members will be subscribed automatically to
flashrom <at> flashrom.org over the next few days. If you are only interested
in either coreboot or flashrom, feel free to unsubscribe from either
list once the split is done.

New IRC structure:
#flashrom on irc.freenode.net is the new channel for flashrom
development and usage discussions. #flashrom is already active, please
join us.
#coreboot on irc.freenode.net will remain the place to discuss all
coreboot and non-flashrom matters.

You will get another mail once the new mailing list is active.

Thanks go to Stefan Reinauer and his company coresystems GmbH for
providing all the infrastructure for flashrom and coreboot.

Regards,
Carl-Daniel
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Myles Watson | 1 Jul 04:09
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Re: Intel Eagle Height evaluation board support


> On Tue, Jun 30, 2009 at 09:10:46AM +0200, Thomas JOURDAN wrote:
> > My mistake ! Seabios run the VGA bios of the matrox graphics card
> > flawless. When I tried seabios, the coreboot Options.lb file of my
> > mainboard wasn't correct. I set :
> > default CONFIG_VGA_ROM_RUN=0
> > default CONFIG_PCI_ROM_RUN=0
> > but also (and that was my mistake)
> > default CONFIG_CONSOLE_VGA=0
> 
> That's odd - I didn't think these coreboot options had any impact to
> SeaBIOS either.  As a guess, coreboot is initializing some hardware
> only when the CONFIG_CONSOLE_VGA option is set.

Yes.  If you don't have CONSOLE_VGA set then the PCI bridge bits don't get
set to allow the legacy I/O and memory ranges to be mapped.

Thanks,
Myles

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Kevin O'Connor | 1 Jul 04:40

Re: Intel Eagle Height evaluation board support

On Tue, Jun 30, 2009 at 08:09:05PM -0600, Myles Watson wrote:
> > That's odd - I didn't think these coreboot options had any impact to
> > SeaBIOS either.  As a guess, coreboot is initializing some hardware
> > only when the CONFIG_CONSOLE_VGA option is set.
> 
> Yes.  If you don't have CONSOLE_VGA set then the PCI bridge bits don't get
> set to allow the legacy I/O and memory ranges to be mapped.

That's unfortunate - setting CONSOLE_VGA also causes coreboot to try
and write to the vga screen.

I would think coreboot should always configure the legacy PCI bridge
bits and CONSOLE_VGA should just control whether or not coreboot tries
to write to the screen.  (Or, if there is a reason to not configure
the pci ranges, then make it a separate config item.)

-Kevin

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Bao, Zheng | 1 Jul 09:06
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Re: [PATCH]:AMD family 10 AM2r2 support

"CONFIG_" is added.

Committed, r4385.

-----Original Message-----
From: Marc Jones [mailto:marcj303 <at> gmail.com] 
Sent: Tuesday, June 30, 2009 11:23 PM
To: Bao, Zheng
Cc: coreboot <at> coreboot.org
Subject: Re: [coreboot] [PATCH]:AMD family 10 AM2r2 support

On Mon, Jun 29, 2009 at 11:46 PM, Bao, Zheng<Zheng.Bao <at> amd.com> wrote:
> Add AMD family 10 AM2r2 support.
> Coreboot used to take SYSTEM_TYPE as a label to tell what the socket is.
> The patch replaces (some of, not all) SYSTEM_TYPE with  CPU_SOCKET_TYPE.
>
> Signed-off-by: Zheng Bao <zheng.bao <at> amd.com>

T

> +default CPU_SOCKET_TYPE=0x11

Please add an equate for the socket names.

Acked-by: Marc Jones <marcj3030 <at> gmail.com>

-- 
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coreboot information | 1 Jul 09:23
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build service results for r4385

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "zbao" checked in revision 4385 to
the coreboot repository. This caused the following 
changes:

Change Log:
Add AMD family 10 AM2r2 support.

Coreboot used to take SYSTEM_TYPE as a lable to tell what the socket is.

This patch replaces (some of, not all) CONFIG_SYSTEM_TYPE with CONFIG_SOCKET_TYPE.
It also fix some compiling error in src/northbridge/amd/amdmct/mct/mctardk4.c

Signed-off-by: Zheng Bao <zheng.bao <at> amd.com>
Acked-by: Marc Jones <marcj303 <at> gmail.com>

Build Log:
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4385&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4385&device=epia-m700&vendor=via&num=2

If something broke during this checkin please be a pain 
in zbao's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.
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Harrison, Jon (SELEX GALILEO, UK | 1 Jul 12:42

Re: C3/CN400 Support - coreboot_tables

Ron,

Attached is the third revision of the CN400/EPIA-N(L) patch for CB V2.

Patch should work against r4381 (or later ?)

This version now boots all of the way through to attempting to launch a
payload (I'm trying FILO right now), where it falls over with exception
6 (invalid opcode)

The coreboot_table issue seems to have been automagically resolved by
the latest core files.

It may still be that the reason for the payload not starting is down to
some issue with the tables initialising, I'll look closer at that.

Signed-off-by: Jon Harrison <bothlyn <at> blueyonder.co.uk>

-----Original Message-----
From: ron minnich [mailto:rminnich <at> gmail.com] 
Sent: 30 June 2009 16:44
To: Harrison, Jon (SELEX GALILEO, UK)
Subject: Re: [coreboot] C3/CN400 Support - coreboot_tables

                    *** WARNING ***

 This message has originated outside your organisation,
  either from an external partner or the Global Internet. 
      Keep this in mind if you answer this message.
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svn | 1 Jul 12:57
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[v2] r4386 - in trunk/coreboot-v2: src/config src/mainboard/via src/mainboard/via/epia-n src/northbridge/via src/northbridge/via/cn400 targets/via targets/via/epia-n

Author: rminnich
Date: 2009-07-01 12:57:25 +0200 (Wed, 01 Jul 2009)
New Revision: 4386

Added:
   trunk/coreboot-v2/src/mainboard/via/epia-n/
   trunk/coreboot-v2/src/mainboard/via/epia-n/Config.lb
   trunk/coreboot-v2/src/mainboard/via/epia-n/Options.lb
   trunk/coreboot-v2/src/mainboard/via/epia-n/acpi_tables.c
   trunk/coreboot-v2/src/mainboard/via/epia-n/auto.c
   trunk/coreboot-v2/src/mainboard/via/epia-n/chip.h
   trunk/coreboot-v2/src/mainboard/via/epia-n/cmos.layout
   trunk/coreboot-v2/src/mainboard/via/epia-n/dsdt.asl
   trunk/coreboot-v2/src/mainboard/via/epia-n/dsdt.c
   trunk/coreboot-v2/src/mainboard/via/epia-n/fadt.c
   trunk/coreboot-v2/src/mainboard/via/epia-n/failover.c
   trunk/coreboot-v2/src/mainboard/via/epia-n/irq_tables.c
   trunk/coreboot-v2/src/mainboard/via/epia-n/mainboard.c
   trunk/coreboot-v2/src/northbridge/via/cn400/
   trunk/coreboot-v2/src/northbridge/via/cn400/Config.lb
   trunk/coreboot-v2/src/northbridge/via/cn400/agp.c
   trunk/coreboot-v2/src/northbridge/via/cn400/chip.h
   trunk/coreboot-v2/src/northbridge/via/cn400/cn400.h
   trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.c
   trunk/coreboot-v2/src/northbridge/via/cn400/northbridge.h
   trunk/coreboot-v2/src/northbridge/via/cn400/raminit.c
   trunk/coreboot-v2/src/northbridge/via/cn400/raminit.h
   trunk/coreboot-v2/src/northbridge/via/cn400/vga.c
   trunk/coreboot-v2/src/northbridge/via/cn400/vgabios.c
   trunk/coreboot-v2/src/northbridge/via/cn400/vgachip.h
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