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Carl-Daniel Hailfinger | 1 Jun 2009 01:14
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[PATCH] flashrom: Add bus type support to -p dummy

Add bus type support to the dummy external programmer.

The syntax is explained in the man page.
Example: flashrom -p dummy=lpc,fwh

Tested, works perfectly. ;-)

As a nice benefit, it allows easy testing of the "probe only compatible
flashes" patch.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 <at> gmx.net>

Index: flashrom-dummy_bustype/flashrom.8
===================================================================
--- flashrom-dummy_bustype/flashrom.8	(Revision 557)
+++ flashrom-dummy_bustype/flashrom.8	(Arbeitskopie)
 <at>  <at>  -135,6 +135,18  <at>  <at> 
 .sp
 .BR "* it87spi" " (for flash ROMs behind a IT87xx SuperI/O LPC/SPI translation unit)"
 .sp
+The dummy programmer has an optional parameter specifying the bus types it
+should support. For that you have to use the
+.B "flashrom -p dummy=type"
+syntax where
+.B type
+can be any comma-separated combination of
+.B parallel lpc fwh spi all
+in any order.
+.sp
+Example:
(Continue reading)

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audiossis | 1 Jun 2009 01:27
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Builing Coreboot

Hi,
I'm new to the Coreboot project. I am an experienced electronics technician, so 
desoldering and burning flash chips is second nature to me, but I'm not a 
programmer so please forgive me if this seems like a silly question.

I've been poking around the Coreboot home pages for the last few days. I've 
downloaded all the required packages to my Gentoo box and had a good look at 
what is there. I've read through some of the various documents on the web site 
about how to build Coreboot and I think I now have a basic understanding of how 
it all works.

My target system is a Clevo laptop with an Intel 82855PM/GM northbridge and an 
82801DB(ICH-4m) south bridge. Both of these chips are listed on the supported 
chipsets page (albeit I understand that the 82855PM/GM is still a work in 
progress).

My question is, do I have to set any build flags or edit any configuration 
files before building Coreboot, to support these chips? Or does Coreboot 
support every device on the supported chipsets page "out of the box" so to 
speak?

I know that I have to edit a configuration file to specify the payload I wish 
to use, but I cannot find anything that tells me wether or not I have to 
configure Coreboot for the specific chipset on the target mainboard.

Thanks for your time and keep up the good work. It's a very interesting project 
and I'm keen to help out even if only by testing on different platforms.

Regards,
Ben
(Continue reading)

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Uwe Hermann | 1 Jun 2009 01:40
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Re: [PATCH] flashrom: Add bus type support to -p dummy

On Mon, Jun 01, 2009 at 01:14:55AM +0200, Carl-Daniel Hailfinger wrote:
> Add bus type support to the dummy external programmer.
> 
> The syntax is explained in the man page.
> Example: flashrom -p dummy=lpc,fwh
> 
> Tested, works perfectly. ;-)
> 
> As a nice benefit, it allows easy testing of the "probe only compatible
> flashes" patch.
> 
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 <at> gmx.net>

Acked-by: Uwe Hermann <uwe <at> hermann-uwe.de>

with the small changes below.

> Index: flashrom-dummy_bustype/dummyflasher.c
> ===================================================================
> --- flashrom-dummy_bustype/dummyflasher.c	(Revision 557)
> +++ flashrom-dummy_bustype/dummyflasher.c	(Arbeitskopie)
>  <at>  <at>  -20,16 +20,51  <at>  <at> 
>  
>  #include <string.h>
>  #include <stdlib.h>
> +#include <ctype.h>
>  #include <fcntl.h>
>  #include <sys/types.h>
>  #include <sys/stat.h>
>  #include <errno.h>
(Continue reading)

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Carl-Daniel Hailfinger | 1 Jun 2009 01:43
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Re: Builing Coreboot

Hi Ben,

On 01.06.2009 01:27, audiossis <at> netspace.net.au wrote:
> I'm new to the Coreboot project.

Welcome!

> I am an experienced electronics technician, so 
> desoldering and burning flash chips is second nature to me, but I'm not a 
> programmer so please forgive me if this seems like a silly question.
>   

There are no silly questions.

> My target system is a Clevo laptop with an Intel 82855PM/GM northbridge and an 
> 82801DB(ICH-4m) south bridge. Both of these chips are listed on the supported 
> chipsets page (albeit I understand that the 82855PM/GM is still a work in 
> progress).
>   

There's one problem with your target system: It's a laptop. Laptops have
embedded controllers and those are _very_ hairy to deal with because
they are usually undocumented and talking with them in unexpected ways
can even turn off the machine or wreak other havoc.

> My question is, do I have to set any build flags or edit any configuration 
> files before building Coreboot, to support these chips? Or does Coreboot 
> support every device on the supported chipsets page "out of the box" so to 
> speak?
>
(Continue reading)

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svn | 1 Jun 2009 02:02
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[flashrom] r559 - trunk

Author: hailfinger
Date: 2009-06-01 02:02:11 +0200 (Mon, 01 Jun 2009)
New Revision: 559

Modified:
   trunk/dummyflasher.c
   trunk/flash.h
   trunk/flashrom.8
   trunk/flashrom.c
Log:
Add bus type support to the dummy external programmer.

The syntax is explained in the man page.
Example: flashrom -p dummy=lpc,fwh

Tested, works perfectly. ;-)

As a nice benefit, it allows easy testing of the "probe only compatible
flashes" patch.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 <at> gmx.net>
Acked-by: Uwe Hermann <uwe <at> hermann-uwe.de>

Modified: trunk/dummyflasher.c
===================================================================
--- trunk/dummyflasher.c	2009-05-31 21:35:10 UTC (rev 558)
+++ trunk/dummyflasher.c	2009-06-01 00:02:11 UTC (rev 559)
 <at>  <at>  -20,16 +20,52  <at>  <at> 

 #include <string.h>
(Continue reading)

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Carl-Daniel Hailfinger | 1 Jun 2009 02:11
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Re: [PATCH] flashrom: Add bus type support to -p dummy

On 01.06.2009 01:40, Uwe Hermann wrote:
> On Mon, Jun 01, 2009 at 01:14:55AM +0200, Carl-Daniel Hailfinger wrote:
>   
>> Add bus type support to the dummy external programmer.
>>
>> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 <at> gmx.net>
>>     
>
> Acked-by: Uwe Hermann <uwe <at> hermann-uwe.de>
>   

Thanks, committed in r559.

Regards,
Carl-Daniel

-- 
http://www.hailfinger.org/

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Uwe Hermann | 1 Jun 2009 03:08
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Re: [PATCH] flashrom: Refactor HT-1000 GPIO setting

On Mon, May 25, 2009 at 06:58:42PM -0700, ron minnich wrote:
> Has this been tested anywhere?
> 
> I get a little worried about changes like this, which look fine in the
> abstract, unless they are tested. It "should" work, it looks fine to
> me, but ...

Yeah, should work. Sure, testing would be nice also, but I think it's ok
to commit this.

Acked-by: Uwe Hermann <uwe <at> hermann-uwe.de>

Uwe.
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Uwe Hermann | 1 Jun 2009 03:10
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Re: [flashrom] nic3com: address lines

On Sat, May 23, 2009 at 06:19:30PM +0200, Mats Erik Andersson wrote:
> Hello all,
> 
> using a signal probe I can verify two facts:
> 
> 1) 3c905B has address lines A0 -- A16 routed, but not A17.
>    Thus 128 kB is the maximal capacity achievable.
> 
> 2) 3c905 only routes the adress lines A0 -- A15, and therefore
>    limits itself to only 64 kB. On the other hand, I have not
>    succeeded in getting even read capabilities going in my
>    own code (not your "flashrom").

I'm not sure if the 3c905 is even supposed to work, not all 3com cards
support the parallel flash read/write interface via the registers
we use in flashrom right now. If the registers aren't there the
programming will fail, of course.

Uwe.
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Peter Stuge | 1 Jun 2009 03:23
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Re: Builing Coreboot

Hi Ben,

audiossis <at> netspace.net.au wrote:
> My target system is a Clevo laptop

What Carl-Daniel wrote about embedded controllers applies. But since
you can recover, it might still be interesting to give it a go.

> (albeit I understand that the 82855PM/GM is still a work in progress)

I have met at least one person who has production 855 code, I will
get in touch with them if you find that current code is lacking.

> I know that I have to edit a configuration file to specify the
> payload I wish to use,

Yes.

> but I cannot find anything that tells me wether or not I have to
> configure Coreboot for the specific chipset on the target
> mainboard.

Carl-Daniel mentioned targets. This is the starting point when
building coreboot.

In the v2 tree, there is the targets/ directory. In there you find
all targets, grouped by vendor. There is no target for your exact
system, so find one that is as close as possible. One target which
uses 855 is digitallogic/adl855pc. To build that, you do:
(Continue reading)

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Peter Stuge | 1 Jun 2009 03:25
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Re: Patch management

Good points Ron. I've also been on both ends of the spectrum.

Patrick Georgi wrote:
>> No code review system, however automated, can fix that kind of
>> problem.
>
> No, but they give a good overview at outstanding reviews, so less
> stuff ends up on the floor.

This elegantly summarizes the point I tried to make. I'll have a look
at the links David posted. Thanks David!

//Peter

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Gmane