Re: K8 patch for new v3 allocator

On Wed, Dec 31, 2008 at 1:51 PM, Myles Watson <mylesgw <at> gmail.com> wrote:
> This patch makes serengeti work as well as it did before.  I'm interested in
> feedback.
>
> Signed-off-by: Myles Watson <mylesgw <at> gmail.com>
>

I've given it two passes and liked it each time.

Acked-by: Ronald G. Minnich <rminnich <at> gmail.com>

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[RFC]flashrom: improve basic design

There is a defect in basic design of flashrom. It leads to problems
some developers are facing or going to face. A partial solution is
proposed.

1. The Defect

struct flashchip {

        /* ... */

	int (*probe) (struct flashchip *flash);
	int (*erase) (struct flashchip *flash);
	int (*write) (struct flashchip *flash, uint8_t *buf);
	int (*read) (struct flashchip *flash, uint8_t *buf);

        /* ... */

};

The struct specifies drivers for operations. It is a good design if
the drivers deal with flash chips directly and provide interfaces for
upper layer program to use. However, those drivers deal with every
component in the communication chain. They do not fit into a structure
storing information closely related to flash chips.

2. Problems

Supporting non-standard flash chips needs to write a new driver. It
requires the developer to be familiar with the internals of flashrom.

Re: #2: Complete tables of supported motherboards

#2: Complete tables of supported motherboards
----------------------------------+-----------------------------------------
 Reporter:  uwe                   |          Owner:  somebody
     Type:  task                  |         Status:  new     
 Priority:  major                 |      Milestone:          
Component:  wiki/website/tracker  |        Version:          
 Keywords:                        |   Dependencies:          
----------------------------------+-----------------------------------------

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Re: wiki page for Asus M2A-VM

Paul Menzel wrote:
> Done [1]. If you have time could you please send me or update the
> ROM chip package (PLCC, DIP32, DIP8, SOIC8)?

The board has a soldered PLCC LPC flash chip.

//Peter

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3 days left for CFP Chemnitzer Linux Tage

Hi,

the Chemnitzer Linux Tage 2009 Call for Lectures and Call for
Presentations deadline is this Sunday, January 5th.

Name: Chemnitzer Linux-Tage
Date: March 14, 2009
Location: Chemnitz, Germany
Colocated with: Workshop on Innovative Operating System Concepts (WIOSC)
http://osg.informatik.tu-chemnitz.de/wiosc09/cfp.php

Call for presentations:
http://chemnitzer.linux-tage.de/2009/live/call_form.html (de)
http://chemnitzer.linux-tage.de/2009/live/call_form_en.html (en)

Call for Lectures:
http://chemnitzer.linux-tage.de/2009/vortraege/call.html (de)
http://chemnitzer.linux-tage.de/2009/vortraege/call_en.html (en)

Coreboot has been explicitly asked to present there and I'd like to make
sure this happens.

Unfortunately my internet access is and will be spotty in the next few
days, so it is rather unlikely I can submit a
presentation/lecture/workshop before the deadline.

Besides the usual coreboot talk, installing coreboot on a Asus M2A-VM
could be a nice workshop with readily available and cheap hardware. (The
top hat flash trick should work on that board.)

Re: Help with boot block problem

Myles Watson wrote:
> I'm porting a board from v2->v3, and I'm running out of space in the
> bootblock, even though it doesn't seem like I should.
> 
> Snippet of broken coreboot.initram.map:
> 
> ffffe3f3 A stage0_rawpnp_exit_ext_func_mode
> ffffe3fc A stage0_rawpnp_set_logical_device
> ffffe41f A stage0_rawpnp_set_iobase
> ffffe448 A stage0_rawpnp_set_enable
> ffffe470 A stage0_protected_stage0
> ffffe47f A stage0___protected_stage0
> ffffe5e8 A stage0__stage0
> ffffe630 A stage0_gdtptr
> fffff960 A stage0_option_table
> fffffff0 A stage0__resetjump
> fffffff0 A stage0__ROMTOP
> 
> Notice that stage0_gdtptr takes fffff960 - ffffe630 = 0x1966
> 
> And working coreboot.initram.map:
> 
> ffffe687 A stage0_rawpnp_read_config
> ffffe69f A stage0_rawpnp_exit_ext_func_mode
> ffffe6a8 A stage0_rawpnp_set_logical_device
> ffffe6cb A stage0_rawpnp_set_iobase
> ffffe6f4 A stage0_rawpnp_set_enable
> ffffe71c A stage0_protected_stage0
> ffffe72b A stage0___protected_stage0
> ffffe894 A stage0__stage0

Re: [RFC]flashrom: improve basic design

On Thu, 1 Jan 2009 18:21:23 +0800, "FENG Yu Ning"
<fengyuning1984 <at> gmail.com> wrote:
> There is a defect in basic design of flashrom. It leads to problems
> some developers are facing or going to face. A partial solution is
> proposed.
> 
> 1. The Defect
> 
> struct flashchip {
> 
>         /* ... */
> 
> 	int (*probe) (struct flashchip *flash);
> 	int (*erase) (struct flashchip *flash);
> 	int (*write) (struct flashchip *flash, uint8_t *buf);
> 	int (*read) (struct flashchip *flash, uint8_t *buf);
> 
>         /* ... */
> 
> };
> 
> The struct specifies drivers for operations. It is a good design if
> the drivers deal with flash chips directly and provide interfaces for
> upper layer program to use. However, those drivers deal with every
> component in the communication chain. They do not fit into a structure
> storing information closely related to flash chips.
> 
> 
> 2. Problems

Re: Help with boot block problem

> -----Original Message-----
> From: Jordan Crouse [mailto:jordan <at> cosmicpenguin.net]
> Sent: Thursday, January 01, 2009 8:30 PM
> To: Myles Watson
> Cc: Coreboot
> Subject: Re: [coreboot] Help with boot block problem
> 
> Myles Watson wrote:
> > I'm porting a board from v2->v3, and I'm running out of space in the
> > bootblock, even though it doesn't seem like I should.
> >
> > Snippet of broken coreboot.initram.map:
> >
> > ffffe3f3 A stage0_rawpnp_exit_ext_func_mode
> > ffffe3fc A stage0_rawpnp_set_logical_device
> > ffffe41f A stage0_rawpnp_set_iobase
> > ffffe448 A stage0_rawpnp_set_enable
> > ffffe470 A stage0_protected_stage0
> > ffffe47f A stage0___protected_stage0
> > ffffe5e8 A stage0__stage0
> > ffffe630 A stage0_gdtptr
> > fffff960 A stage0_option_table
> > fffffff0 A stage0__resetjump
> > fffffff0 A stage0__ROMTOP
> >
> > Notice that stage0_gdtptr takes fffff960 - ffffe630 = 0x1966
> >
> > And working coreboot.initram.map:
> >

Re: coreboot Digest, Vol 46, Issue 148

Hi, obrain a similar output when trying to flash a proprietary BIOS.
What I guess is that the initial address could be wrong. Here is the
output:

root <at> debian:~# flashrom -w -v A6T-ASUS-0706.ROMCalibrating delay
loop... OK.No coreboot table found.Found chipset "NVIDIA MCP51",
enabling flash write... OK.Found chip "PMC Pm49FL004" (512 KB) at
physical address 0xfff80000.Flash image seems to be a legacy BIOS.
Disabling checks.Programming page: 0007 at address:
0x00070000Verifying flash... FAILED!  Expected=0xf8, Read=0x68

2008/12/21, coreboot-request <at> coreboot.org <coreboot-request <at> coreboot.org>:
> Send coreboot mailing list submissions to
> 	coreboot <at> coreboot.org
>
> To subscribe or unsubscribe via the World Wide Web, visit
> 	http://www.coreboot.org/mailman/listinfo/coreboot
> or, via email, send a message with subject or body 'help' to
> 	coreboot-request <at> coreboot.org
>
> You can reach the person managing the list at
> 	coreboot-owner <at> coreboot.org
>
> When replying, please edit your Subject line so it is more specific
> than "Re: Contents of coreboot digest..."
>
>
> Today's Topics:
>
>    1. Re: need help with #define macro (Joseph Smith)

Re: ASUS M2N-SLI Deluxe

2008/12/30 Paul Menzel <paulepanter <at> users.sourceforge.net>:
> Dear Christian,
> [I added the list again.]
>
>
> Am Dienstag, den 30.12.2008, 16:09 +0100 schrieb Christian Ruppert:
>> 2008/12/30 Paul Menzel <paulepanter <at> users.sourceforge.net>:
>
>> > Am Dienstag, den 30.12.2008, 15:27 +0100 schrieb Christian Ruppert:
>> >
>> >> here is 'lspci -tvnn'.
>> >> additional cards are marked with PCIE CARD at the begin of line, rest
>> >> should be onboard.
>> >> i hope it help :)
>> >>
>> >> -[0000:00]-+-00.0  nVidia Corporation MCP55 Memory Controller [10de:0369]
>> >>            +-01.0  nVidia Corporation MCP55 LPC Bridge [10de:0360]
>> >>            +-01.1  nVidia Corporation MCP55 SMBus [10de:0368]
>> >>            +-02.0  nVidia Corporation MCP55 USB Controller [10de:036c]
>> >>            +-02.1  nVidia Corporation MCP55 USB Controller [10de:036d]
>> >>            +-04.0  nVidia Corporation MCP55 IDE [10de:036e]
>> >>            +-05.0  nVidia Corporation MCP55 SATA Controller [10de:037f]
>> >>            +-05.1  nVidia Corporation MCP55 SATA Controller [10de:037f]
>> >>            +-05.2  nVidia Corporation MCP55 SATA Controller [10de:037f]
>> >>            +-06.0-[0000:01]----0b.0  Texas Instruments TSB43AB22/A
>> >> IEEE-1394a-2000 Controller (PHY/Link) [104c:8023]
>> >>            +-06.1  nVidia Corporation MCP55 High Definition Audio [10de:0371]
>> >>            +-08.0  nVidia Corporation MCP55 Ethernet [10de:0373]
>> >>            +-09.0  nVidia Corporation MCP55 Ethernet [10de:0373]
>> >> PCIE CARD           +-0a.0-[0000:02]----00.0  nVidia Corporation G70