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svn | 1 Oct 08:47
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r876 - in coreboot-v3: device include/device mainboard/gigabyte/m57sli southbridge/nvidia/mcp55 superio/ite/it8716f

Author: rminnich
Date: 2008-10-01 08:47:51 +0200 (Wed, 01 Oct 2008)
New Revision: 876

Added:
   coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h
Modified:
   coreboot-v3/device/pnp_raw.c
   coreboot-v3/include/device/pnp.h
   coreboot-v3/mainboard/gigabyte/m57sli/Makefile
   coreboot-v3/mainboard/gigabyte/m57sli/initram.c
   coreboot-v3/mainboard/gigabyte/m57sli/stage1.c
   coreboot-v3/southbridge/nvidia/mcp55/stage1.c
   coreboot-v3/superio/ite/it8716f/it8716f.h
Log:
Bringing the m57sli to life. This includes changes to mcp55 and 
mainboard that we learned with the serengeti that we needed. New 
function in pnp that is for reading. new prototype in pnp.h. New 
constants for ite8716f. 

This board does not build yet; we are exercising code in k8 north that
the serengeti did not enable. More tomorrow. 

Now that we have two boards under way we can hopefully see our way to 
getting more put in. The 690 is the obvious next choice. 

Signed-off-by: Ronald G. Minnich <rminnich <at> gmail.com>
Acked-by: Ronald G. Minnich <rminnich <at> gmail.com>

Modified: coreboot-v3/device/pnp_raw.c
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svn | 1 Oct 09:23
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r877 - in coreboot-v3: arch/x86/amd/model_fxx mainboard/gigabyte/m57sli northbridge/amd/k8 southbridge/nvidia/mcp55

Author: rminnich
Date: 2008-10-01 09:23:05 +0200 (Wed, 01 Oct 2008)
New Revision: 877

Modified:
   coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c
   coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h
   coreboot-v3/northbridge/amd/k8/dqs.c
   coreboot-v3/northbridge/amd/k8/raminit.c
   coreboot-v3/southbridge/nvidia/mcp55/ide.c
   coreboot-v3/southbridge/nvidia/mcp55/lpc.c
   coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
   coreboot-v3/southbridge/nvidia/mcp55/pci.c
   coreboot-v3/southbridge/nvidia/mcp55/pcie.c
   coreboot-v3/southbridge/nvidia/mcp55/sata.c
   coreboot-v3/southbridge/nvidia/mcp55/usb2.c
Log:
m57sli mostly builds again. The stage0 is too large at 24k. 
We need to figure out if we should just grow stage0. My inclination is 
to say 'yes'.

Signed-off-by: Ronald G. Minnich <rminnich <at> gmail.com>
Acked-by: Ronald G. Minnich <rminnich <at> gmail.com>

Modified: coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c
===================================================================
--- coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c	2008-10-01 06:47:51 UTC (rev 876)
+++ coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c	2008-10-01 07:23:05 UTC (rev 877)
@@ -300,9 +300,9 @@
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Stefan Reinauer | 1 Oct 11:32
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Re: r877 - in coreboot-v3: arch/x86/amd/model_fxx mainboard/gigabyte/m57sli northbridge/amd/k8 southbridge/nvidia/mcp55

svn <at> coreboot.org wrote:
> Author: rminnich
> Date: 2008-10-01 09:23:05 +0200 (Wed, 01 Oct 2008)
> New Revision: 877
>
> Modified:
>    coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c
>    coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h
>    coreboot-v3/northbridge/amd/k8/dqs.c
>    coreboot-v3/northbridge/amd/k8/raminit.c
>    coreboot-v3/southbridge/nvidia/mcp55/ide.c
>    coreboot-v3/southbridge/nvidia/mcp55/lpc.c
>    coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
>    coreboot-v3/southbridge/nvidia/mcp55/pci.c
>    coreboot-v3/southbridge/nvidia/mcp55/pcie.c
>    coreboot-v3/southbridge/nvidia/mcp55/sata.c
>    coreboot-v3/southbridge/nvidia/mcp55/usb2.c
> Log:
> m57sli mostly builds again. The stage0 is too large at 24k. 
> We need to figure out if we should just grow stage0. My inclination is 
> to say 'yes'.
>   

What's in stage0 that makes it so big? Is that part really required in
stage0?

If so, we need to grow stage0. But we should try to answer that question
first.

--

--
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svn | 1 Oct 14:52
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r3624 - in trunk/coreboot-v2/src: arch/i386/boot arch/i386/lib arch/i386/smp arch/ppc/boot cpu/amd/model_10xxx cpu/amd/sc520 cpu/emulation/qemu-x86 drivers/ati/ragexl mainboard/a-trend/atc-6220 mainboard/agami/aruma mainboard/amd/dbm690t mainboard/amd/serengeti_cheetah mainboard/amd/serengeti_cheetah_fam10 mainboard/arima/hdama mainboard/artecgroup/dbe61 mainboard/asus/a8n_e mainboard/asus/mew-vm mainboard/asus/p2b mainboard/asus/p2b-f mainboard/asus/p3b-f mainboard/azza/pt-6ibd mainboard/biostar/m6tba mainboard/broadcom/blast mainboard/compaq/deskpro_en_sff_p600 mainboard/dell/s1850 mainboard/digitallogic/adl855pc mainboard/eaglelion/5bcm mainboard/gigabyte/ga-6bxc mainboard/gigabyte/ga_2761gxdk mainboard/gigabyte/m57sli mainboard/ibm/e325 mainboard/ibm/e326 mainboard/intel/jarrell mainboard/intel/xe7501devkit mainboard/iwill/dk8_htx mainboard/iwill/dk8s2 mainbo

Author: hailfinger
Date: 2008-10-01 14:52:52 +0200 (Wed, 01 Oct 2008)
New Revision: 3624

Modified:
   trunk/coreboot-v2/src/arch/i386/boot/acpi.c
   trunk/coreboot-v2/src/arch/i386/boot/coreboot_table.c
   trunk/coreboot-v2/src/arch/i386/lib/cpu.c
   trunk/coreboot-v2/src/arch/i386/lib/exception.c
   trunk/coreboot-v2/src/arch/i386/smp/ioapic.c
   trunk/coreboot-v2/src/arch/ppc/boot/coreboot_table.c
   trunk/coreboot-v2/src/cpu/amd/model_10xxx/init_cpus.c
   trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c
   trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c
   trunk/coreboot-v2/src/drivers/ati/ragexl/xlinit.c
   trunk/coreboot-v2/src/mainboard/a-trend/atc-6220/auto.c
   trunk/coreboot-v2/src/mainboard/agami/aruma/auto.c
   trunk/coreboot-v2/src/mainboard/agami/aruma/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/agami/aruma/resourcemap.c
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/resourcemap.c
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah/resourcemap.c
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/amd/serengeti_cheetah_fam10/resourcemap.c
   trunk/coreboot-v2/src/mainboard/arima/hdama/auto.c
   trunk/coreboot-v2/src/mainboard/arima/hdama/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/artecgroup/dbe61/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/asus/a8n_e/get_bus_conf.c
   trunk/coreboot-v2/src/mainboard/asus/mew-vm/auto.c
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svn | 1 Oct 15:10
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r3625 - trunk/coreboot-v2/src/mainboard/asus/a8n_e

Author: uwe
Date: 2008-10-01 15:10:39 +0200 (Wed, 01 Oct 2008)
New Revision: 3625

Modified:
   trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb
   trunk/coreboot-v2/src/mainboard/asus/a8n_e/Options.lb
Log:
Enable all available devices on the ASUS A8N-E (trivial).

This is in preparation for actually making the devices work (which needs
some extra code). Also, fix the incorrect mainboard subsystem IDs.

Signed-off-by: Uwe Hermann <uwe <at> hermann-uwe.de>
Acked-by: Uwe Hermann <uwe <at> hermann-uwe.de>

Modified: trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb	2008-10-01 12:52:52 UTC (rev 3624)
+++ trunk/coreboot-v2/src/mainboard/asus/a8n_e/Config.lb	2008-10-01 13:10:39 UTC (rev 3625)
@@ -165,7 +165,7 @@
           device pci 0.0 on end			# HT
           device pci 1.0 on			# LPC
             chip superio/ite/it8712f		# Super I/O
-              device pnp 2e.0 off		# Floppy
+              device pnp 2e.0 on		# Floppy
                 io 0x60 = 0x3f0
                 irq 0x70 = 6
                 drq 0x74 = 2
@@ -174,13 +174,14 @@
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coreboot information | 1 Oct 15:32
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r3624 build service

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "hailfinger" checked in revision 3624 to
the coreboot source repository and caused the following 
changes:

Change Log:
The ARRAY_SIZE macro is convenient, yet mostly unused. Switch lots of
code to use it. That makes the code more readable and also less
error-prone.

Abuild tested.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 <at> gmx.net>
Acked-by: Peter Stuge <peter <at> stuge.se>

Build Log:
Compilation of asus:m2v-mx_se is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3624&device=m2v-mx_se&vendor=asus
Compilation of jetway:j7f24 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3624&device=j7f24&vendor=jetway
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3624&device=epia-cn&vendor=via

If something broke during this checkin please be a pain 
in hailfinger's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should
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coreboot information | 1 Oct 16:19
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r3625 build service

Dear coreboot readers!

This is the automated build check service of coreboot.

The developer "uwe" checked in revision 3625 to
the coreboot source repository and caused the following 
changes:

Change Log:
Enable all available devices on the ASUS A8N-E (trivial).

This is in preparation for actually making the devices work (which needs
some extra code). Also, fix the incorrect mainboard subsystem IDs.

Signed-off-by: Uwe Hermann <uwe <at> hermann-uwe.de>
Acked-by: Uwe Hermann <uwe <at> hermann-uwe.de>

Build Log:
Compilation of asus:m2v-mx_se is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3625&device=m2v-mx_se&vendor=asus
Compilation of jetway:j7f24 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3625&device=j7f24&vendor=jetway
Compilation of via:epia-cn is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3625&device=epia-cn&vendor=via

If something broke during this checkin please be a pain 
in uwe's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.
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Carl-Daniel Hailfinger | 1 Oct 15:23
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[PATCH v2] AMD DBM690T IRQ cleanup

Hi,

I decided to prepare a patch for the stuff I mentioned in the DBM690T
review.

Use easily readable macros to setup interrupt routing.
Change a few PCI bus/dev/fn to use hexadecimal numbers.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 <at> gmx.net>

Index: LinuxBIOSv2-irq_macros/src/mainboard/amd/dbm690t/mptable.c
===================================================================
--- LinuxBIOSv2-irq_macros/src/mainboard/amd/dbm690t/mptable.c	(Revision 3624)
+++ LinuxBIOSv2-irq_macros/src/mainboard/amd/dbm690t/mptable.c	(Arbeitskopie)
@@ -122,94 +122,72 @@
 	smp_write_intsrc(mc, mp_ExtINT,
 			 MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa,
 			 0x0, apicid_sb600, 0x0);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x1, apicid_sb600, 0x1);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x0, apicid_sb600, 0x2);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x3, apicid_sb600, 0x3);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x4, apicid_sb600, 0x4);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x6, apicid_sb600, 0x6);
-	smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH,
-			 bus_isa, 0x7, apicid_sb600, 0x7);
(Continue reading)

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Tiago Marques | 1 Oct 15:35
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Re: Master degree student wanting to give some help.

Hi.

On Tue, Sep 30, 2008 at 3:49 PM, Peter Stuge <peter <at> stuge.se> wrote:
Hi Cedric,

Cedric RIVERA wrote:
> I'm a french master degree student in Free Software ingeneering,
> looking for a year project to join and I really love to be involved
> in Coreboot community to :
>
>    improve AMD690G chipset support, or
>    port coreboot-v3 to Gigabyte M57SLI-S4, I've got one to develop.

I think these two are both great candidates. m57sli in v3 has already
been started, so it is likely to be the simplest task. It would also
be a good way to get familiar with the code and structure.


>    Openmoko coreboot port or

Probably not so useful. Is there a PCI bus in the Openmoko?
Why is this important? Supposedly, the next iteration of Intel's Atom platform won't feature a PCI bus, coreboot won't work with it?
 

> I just need that someone supervise my work and do, monthly, a
> feedback to my teacher at the university to have a note.
>
> Son is someone interested ?

You already have some offers but I'll add myself too. :) I'm
interested in both 690 and m57sli in v3, but even more in K8/Fam10 in
v3 in general because I think we need to make some (relatively) small
design changes to make sure we get the most out of v3.


//Peter

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Mats Erik Andersson | 1 Oct 18:18
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flashrom: [PATCH] Support for AM29F002(N)B[BT]

Support for AM29F002(N)B[BT]. Fully tested on AM29F002NBT.
Probing, reading, and erasing use the Jedec-routines,
whereas writing resort to the recent write_en29f002a(),
since also these chips use a byte wise algorithm.

Signed-off-by: Mats Erik Andersson <mats.andersson <at> gisladisker.se>

---

Index: flashrom/flash.h
===================================================================
--- flashrom/flash.h	(revision 3624)
+++ flashrom/flash.h	(arbetskopia)
@@ -112,6 +112,8 @@
 #define ALLIANCE_ID		0x52	/* Alliance Semiconductor */

 #define AMD_ID			0x01	/* AMD */
+#define AM_29F002BT		0xB0
+#define AM_29F002BB		0x34
 #define AM_29F040B		0xA4
 #define AM_29LV040B		0x4F
 #define AM_29F016D		0xAD
Index: flashrom/flashchips.c
===================================================================
--- flashrom/flashchips.c	(revision 3624)
+++ flashrom/flashchips.c	(arbetskopia)
@@ -32,6 +32,8 @@
 	/**********************************************************************************************************************************************************************************************************************/
 	/* Vendor	Chip			Vendor ID	Chip ID			TODO	TODO		Test status	Probe function		Erase
function			Write function		Read function */
 	/**********************************************************************************************************************************************************************************************************************/
+	{"AMD",	"Am29F002(N)BB",		AMD_ID,		AM_29F002BB,		256,	256,		TEST_UNTESTED,	probe_jedec,		erase_chip_jedec,		write_en29f002a},
+	{"AMD",	"Am29F002(N)BT",		AMD_ID,		AM_29F002BT,		256,	256,		TEST_OK_PREW,	probe_jedec,		erase_chip_jedec,		write_en29f002a},
 	{"AMD",		"Am29F016D",		AMD_ID,		AM_29F016D,		2048,	64 * 1024,	TEST_UNTESTED,	probe_29f040b,		erase_29f040b,			write_29f040b},
 	{"AMD",		"Am29F040B",		AMD_ID,		AM_29F040B,		512,	64 * 1024,	TEST_OK_PREW,	probe_29f040b,		erase_29f040b,			write_29f040b},
 	{"AMD",		"Am29LV040B",		AMD_ID,		AM_29LV040B,		512,	64 * 1024,	TEST_UNTESTED,	probe_29f040b,		erase_29f040b,			write_29f040b},

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Gmane