[PATCH] Disable integrated Intel 3100 devices properly

Setting an integrated southbridge device (like SATA or USB2.0) to
"off" in Config.lb should cause the PCI device not to respond to
configuration requests. The code that takes care of this for the Intel
3100 is in src/southbridge/intel/i3100/i3100.c. Unfortunately I copied
the esb6300 implementation without noticing that it makes no sense at
all on the Intel 3100. The attached patch implements this properly for
the Intel 3100.

--Ed

Index: coreboot-v2-3189/src/southbridge/intel/i3100/i3100.c
===================================================================
--- coreboot-v2-3189.orig/src/southbridge/intel/i3100/i3100.c
+++ coreboot-v2-3189/src/southbridge/intel/i3100/i3100.c
@@ -18,52 +18,43 @@
  *
  */

-/* This code is based on src/southbridge/intel/esb6300/esb6300.c */
-
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <device/pci_ids.h>
 #include "i3100.h"

 void i3100_enable(device_t dev)
 {
 	device_t lpc_dev;

Re: [PATCH] Disable integrated Intel 3100 devices properly

On Mon, Mar 31, 2008 at 04:38:34PM -0700, Ed Swierk wrote:
> Setting an integrated southbridge device (like SATA or USB2.0) to
> "off" in Config.lb should cause the PCI device not to respond to
> configuration requests. The code that takes care of this for the Intel
> 3100 is in src/southbridge/intel/i3100/i3100.c. Unfortunately I copied
> the esb6300 implementation without noticing that it makes no sense at
> all on the Intel 3100. The attached patch implements this properly for
> the Intel 3100.

You forgot the Signed-off-by.

> +	/* Temporarily enable the root complex register block at 0xa0000000 */
> +	lpc_dev = dev_find_slot(0x0, PCI_DEVFN(0x1f, 0x0));
> +	pci_write_config32(lpc_dev, 0xf0, 0xa0000000 | (1 << 0));
> +	disable = (volatile u32 *) 0xa0003418;
> +	func = PCI_FUNC(dev->path.u.pci.devfn);
> +	switch (PCI_SLOT(dev->path.u.pci.devfn)) {
> +	case 0x1f:
> +		*disable |= (1 << (func == 0x0 ? 14 : func));
> +		break;
> +	case 0x1d:
> +		*disable |= (1 << (func + 8));
> +		break;
> +	case 0x1c:
> +		*disable |= (1 << (func + 16));
> +		break;

This part could use a small comment about what exactly is disabled in
each "case".

Re: [PATCH] Disable integrated Intel 3100 devices properly

On Mon, Mar 31, 2008 at 5:41 PM, Uwe Hermann <uwe <at> hermann-uwe.de> wrote:
>  Rest of the patch looks good. Is this build-tested and tested on
>  hardware? If so, I can ack and commit if you resend with a Signed-off-by.

Yes, I tested it on a Mt. Arvon board.

Signed-off-by: Ed Swierk <eswierk <at> arastra.com>

--Ed

Index: coreboot-v2-3189/src/southbridge/intel/i3100/i3100.c
===================================================================
--- coreboot-v2-3189.orig/src/southbridge/intel/i3100/i3100.c
+++ coreboot-v2-3189/src/southbridge/intel/i3100/i3100.c
@@ -18,52 +18,43 @@
  *
  */

-/* This code is based on src/southbridge/intel/esb6300/esb6300.c */
-
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
-#include <device/pci_ids.h>
 #include "i3100.h"

 void i3100_enable(device_t dev)
 {
 	device_t lpc_dev;

r3205 - in trunk/coreboot-v2/src/southbridge/intel: esb6300 i3100 i82801ca i82801db i82801dbm i82801er

Author: eswierk
Date: 2008-04-01 04:36:59 +0200 (Tue, 01 Apr 2008)
New Revision: 3205

Modified:
   trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_early_smbus.c
   trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c
   trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_smbus.c
   trunk/coreboot-v2/src/southbridge/intel/i82801ca/i82801ca_early_smbus.c
   trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_early_smbus.c
   trunk/coreboot-v2/src/southbridge/intel/i82801dbm/i82801dbm_early_smbus.c
   trunk/coreboot-v2/src/southbridge/intel/i82801er/i82801er_early_smbus.c
Log:
The early init code of several Intel southbridge chipsets calls
pci_locate_device() to locate the SMBus controller and LPC bridge
devices on the PCI bus. Since these devices are always located at a
fixed PCI bus:device:function, the code can be simplified by
hardcoding the devices.

Signed-off-by: Ed Swierk <eswierk <at> arastra.com>
Acked-by: Corey Osgood <corey.osgood <at> gmail.com>

Modified: trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_early_smbus.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_early_smbus.c	2008-03-31
21:02:29 UTC (rev 3204)
+++ trunk/coreboot-v2/src/southbridge/intel/esb6300/esb6300_early_smbus.c	2008-04-01
02:36:59 UTC (rev 3205)
@@ -4,12 +4,8 @@

r3206 - trunk/coreboot-v2/src/southbridge/intel/i82801db

Author: eswierk
Date: 2008-04-01 04:42:52 +0200 (Tue, 01 Apr 2008)
New Revision: 3206

Removed:
   trunk/coreboot-v2/src/southbridge/intel/i82801db/Config.lb
   trunk/coreboot-v2/src/southbridge/intel/i82801db/chip.h
   trunk/coreboot-v2/src/southbridge/intel/i82801db/cmos_failover.c
   trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db.c
   trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_ac97.c
   trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_early_smbus.c
Log:
Removal of i82801DB (ICH4)

There are no boards that use the i82801DB (ICH4). The code does NOT work.

Signed-off-by: Joseph Smith <joe <at> smittys.pointclark.net>
Acked-by: Corey Osgood <corey.osgood <at> gmail.com>
Acked-by: Ed Swierk <eswierk <at> arastra.com>

Deleted: trunk/coreboot-v2/src/southbridge/intel/i82801db/Config.lb
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i82801db/Config.lb	2008-04-01 02:36:59 UTC (rev 3205)
+++ trunk/coreboot-v2/src/southbridge/intel/i82801db/Config.lb	2008-04-01 02:42:52 UTC (rev 3206)
@@ -1,11 +0,0 @@
-config chip.h
-driver i82801db.o
-driver i82801db_uhci.o
-driver i82801db_lpc.o
-driver i82801db_ide.o

r3207 - trunk/coreboot-v2/src/southbridge/intel/i3100

Author: eswierk
Date: 2008-04-01 04:48:12 +0200 (Tue, 01 Apr 2008)
New Revision: 3207

Modified:
   trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c
Log:
Tiny style fix for consistency (trivial).

Signed-off-by: Ed Swierk <eswierk <at> arastra.com>
Acked-by: Ed Swierk <eswierk <at> arastra.com>

Modified: trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c	2008-04-01 02:42:52 UTC
(rev 3206)
+++ trunk/coreboot-v2/src/southbridge/intel/i3100/i3100_early_lpc.c	2008-04-01 02:48:12 UTC
(rev 3207)
@@ -28,7 +28,7 @@

 static void i3100_halt_tco_timer(void)
 {
-	device_t dev = PCI_DEV(0, 0x1f, 0);
+	device_t dev = PCI_DEV(0x0, 0x1f, 0x0);

 	/* Temporarily enable the ACPI I/O range at 0x4000 */
 	pci_write_config32(dev, 0x40, 0x4000 | (1 << 0));

--

-- 
coreboot mailing list

Re: [PATCH] Hardcode PCI devices in Intel southbridge early init code

Corey Osgood wrote:

>
> Yep, it's the digitallogic/adl855pc. I think it was Ron that said the 
> 855 never worked, but that was a long time ago, and I can't be sure.  
> Perhaps we should just leave it kicking around, and focus on not 
> letting this happen to v3.

I can confirm that code does nothing good. I have a mostly ready 855 
port sitting somewhere that I wrote from flash. I will look into this 
when/if I get the machine again I was originally writing it for.

-- 
coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br.
      Tel.: +49 761 7668825 • Fax: +49 761 7664613
Email: info <at> coresystems.de  • http://www.coresystems.de/
Registergericht: Amtsgericht Freiburg • HRB 7656
Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

--

-- 
coreboot mailing list
coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

Alix2c3 MB support (Geode LX800)

Hi Guys,

I saw that Alix1.c is supported by Coreboot v3. Is it hard to port the
support for Alix2c3?
The chipset is the same with Alix1.c. Or is it better to port Coreboot
v2 to this board?

The board comes with tinyBIOS but if I couldn't handle the current
problem with tinyBIOS,
I might port coreboot instead.

Regards,

Darmawan Salihun
--------------------------------------------------------------------
-= Human knowledge belongs to the world =-

--

-- 
coreboot mailing list
coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

Re: Device mapping problem

Hi there

At first I can't boot my system with coreboot yet. I changed kernel params
so initrd now will be loaded. Used kernel params are now same as in lilo
of original system.

But I logged booting my system with original bios and coreboot. So I hope
we will find the problem.

There are two differences I think that could be a problem. At first there
are two different size of memory detected:
coreboot: 222822k/229376k
origianl bios: 222384k/229312k

And of course on original bios system DMI 2.2 is started. On coreboot DMI
is not present or is invalid.

Some ideas what seems to be problem at coreboot starting on my system?

Klaus

Here log of coreboot booting out of ttyS0:
-----------------------------------------------------------------------------
0

coreboot-2.0.0.0-Fallback Mo 31. Mär 14:41:14 CEST 2008 starting...
 Enabling mainboard devices
 Enabling shadow ram
vt8623 init starting
Detecting Memory

Re: r3206 - trunk/coreboot-v2/src/southbridge/intel/i82801db

Quoting svn <at> coreboot.org:

> Author: eswierk
> Date: 2008-04-01 04:42:52 +0200 (Tue, 01 Apr 2008)
> New Revision: 3206
>
> Removed:
>    trunk/coreboot-v2/src/southbridge/intel/i82801db/Config.lb
>    trunk/coreboot-v2/src/southbridge/intel/i82801db/chip.h
>    trunk/coreboot-v2/src/southbridge/intel/i82801db/cmos_failover.c
>    trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db.c
>    trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_ac97.c
>    trunk/coreboot-v2/src/southbridge/intel/i82801db/i82801db_early_smbus.c
> Log:
> Removal of i82801DB (ICH4)
>
> There are no boards that use the i82801DB (ICH4). The code does NOT work.
>
> Signed-off-by: Joseph Smith <joe <at> smittys.pointclark.net>
> Acked-by: Corey Osgood <corey.osgood <at> gmail.com>
> Acked-by: Ed Swierk <eswierk <at> arastra.com>
>
>
Thanks Ed 

Thanks - Joe

--

-- 
coreboot mailing list
coreboot <at> coreboot.org