1 Dec 2006 01:05
Re: 440BX progress.
Segher Boessenkool <segher <at> kernel.crashing.org>
2006-12-01 00:05:39 GMT
2006-12-01 00:05:39 GMT
>> Be careful >> to set the enable bit (bit 7 in 0xe7) last. > > Yep. As the last step in sdram_set_registers() or as the last step > in RAM init in general? The last step of setting the registers e0..ef. >> Also, you probably didn't program the MRS on the memory. > > Yes, I'm quite sure I messed that up. Heh, nothing will work then(Continue reading)> In general, in do_ram_command() I > have to set DRAMC bits 7-5 to the respective command and then read32 > () from > some memory location for the change to "take effect", right? Write to that location, instead. It's not that you make "a change take effect" -- it directly sends a command on the memory bus, instead. > If so, which memory location is that? Does it depend on some input > data? 0x1d0 in the rank, typically. There is some tiny documentation in the intel sheet; the idea is to send the correct pattern on the DRAM address pins (use the selected map to figure out what pattern that is).
> In general, in do_ram_command() I
> have to set DRAMC bits 7-5 to the respective command and then read32
> () from
> some memory location for the change to "take effect", right?
Write to that location, instead. It's not that you make
"a change take effect" -- it directly sends a command on
the memory bus, instead.
> If so, which memory location is that? Does it depend on some input
> data?
0x1d0 in the rank, typically. There is some tiny
documentation in the intel sheet; the idea is to send
the correct pattern on the DRAM address pins (use the
selected map to figure out what pattern that is).
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