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Takeshi Sone | 1 Dec 2003 08:51
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Re: Level 2 cache activation code?

On Mon, Dec 01, 2003 at 12:14:14AM +0100, Svante Signell wrote:
> No speed-up seen. Extremely slow as before. Any hints? mtrr is OK, I
> believe. Is it the microcode??

You could try the microcode driver of Linux or code from LinuxBIOS.

> 3. How to create a kernel module consisting of more than one object
> file. Now I include the needed source files into the main one.

ld -o module.o -r obj1.o obj2.o

--

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Niki Waibel | 1 Dec 2003 11:44
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v1: epia-m: irq_tables.c, mainboard.c

i think we need a new thread for the ``intel dual netwokcard problem on epia-m'' topic.

facts (correct me if i am wrong!):
        * intel dual eth nic is not working with linuxbios (2003-10-24).
        * it can be plugged into the pci slot (00:14.0) of the epia-m.
        * the dual nic has a pci-to-pci bridge on the card.
        * that bridge assignes pci bus 2 (0=internal, 1=vga/agp?)
        * the 2 nics on the card assign: 02:04.0 and 02:05.0
        * linuxbios detects the bus/bridge and also sees the 2 nic.
      !!* linuxbios does not assign irqs to the nics.
        * default (2003-10-24) linuxbios src/mainboard/via/epia-m/irq_tables.c:
===
/* This file was generated by getpir.c, do not modify! 
   (but if you do, please run checkpir on it to verify)
   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up

   Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
*/

#include <arch/pirq_routing.h>

const struct irq_routing_table intel_irq_routing_table = {
        PIRQ_SIGNATURE, /* u32 signature */
        PIRQ_VERSION,   /* u16 version   */
        32+16*5,        /* there can be total 5 devices on the bus */
        0,           /* Where the interrupt router lies (bus) */
        0,           /* Where the interrupt router lies (dev) */
        0x1c20,         /* IRQs devoted exclusively to PCI usage */
        0,         /* Vendor */
        0,         /* Device */
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Devi Priya | 1 Dec 2003 13:51
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Re: Linuxbios with Diskonchip?

Hi,

     I have Diskonchip millennium MD2800 (8 MB capacity) and Microns SDRAM 
capacity (256 Mbits).
Then the flash is to be mapped into the physical address 
0xFFFFFFFF-0xFF800000. SDRAM is to mapped into the physical address 
0x00000000-0xFE000000. Is this mapping correct?

>From: ron minnich <rminnich <at> lanl.gov>
>To: Devi Priya <ijpriya <at> hotmail.com>
>CC: gizara <at> cox.net, <linuxbios <at> clustermatic.org>
>Subject: Re: Linuxbios with Diskonchip?
>Date: Sat, 29 Nov 2003 18:35:20 -0700 (MST)
>
>On Fri, 28 Nov 2003, Devi Priya wrote:
>
> > Hi,
> >
> >       I am using Diskonchip millennium with boot capability. I just want 
>to
> > know if diskonchip is mapped to the high order physical address (at 
>reset)
> > and is any remapping is done later?
>
>usually mapped at flash address, right? 0xf0000 and 0xfff00000
>
>ron
>
>_______________________________________________
>Linuxbios mailing list
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Richard Smith | 1 Dec 2003 17:57

Re: v1: epia-m: irq_tables.c, mainboard.c

Niki Waibel wrote:

> ===
> /* This file was generated by getpir.c, do not modify! 
>    (but if you do, please run checkpir on it to verify)
>    Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
> 
>    Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM

Just FYI this link is going stale... MS currently redirects you to its 
new location but who knows how long that will last.  Perhaps someone 
should save the whitepaper and put it at a location more under our 
control.  It is useful info.

Unless the ms copywrite forbids this, of course. :)

--

-- 
Richard A. Smith
rsmith <at> bitworks.com

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Eric W. Biederman | 1 Dec 2003 20:57

Re: automatic power on possible?

<thomas <at> wehrspann.de> writes:

> Most modern motherboards supports the timer based automatic power on
> via BIOS settings. With linuxbios this is not(?) possible. There is a program
> for linux, called nvram-wakeup, to set the wakeup time in nvram or rtc. But
> especially for the K7SEM or EPIA boards a reboot is needed after it, so the
> wakeup settings can take effect.
> Does anyone know what the BIOS is doing what linuxbios does not?
> Perhaps it can be done in a program?

I believe it is just a matter of programming some real-time clock registers
so an alarm will go off at a specified time, and setting up the
appropriate southbridge or superio bits so that the board will wake up
when the alarm is triggered.  I doubt it even requires BIOS support at
all.  Though that can't hurt.

Eric

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ron minnich | 2 Dec 2003 00:28

Re: v1: epia-m: irq_tables.c, mainboard.c

On Mon, 1 Dec 2003, Niki Waibel wrote:

> i think we need a new thread for the ``intel dual netwokcard problem on
> epia-m'' topic.
> 

OK, I'm now looking at this for real :)

> facts (correct me if i am wrong!):
>         * intel dual eth nic is not working with linuxbios (2003-10-24).
>         * it can be plugged into the pci slot (00:14.0) of the epia-m.
>         * the dual nic has a pci-to-pci bridge on the card.
>         * that bridge assignes pci bus 2 (0=internal, 1=vga/agp?)
>         * the 2 nics on the card assign: 02:04.0 and 02:05.0
>         * linuxbios detects the bus/bridge and also sees the 2 nic.
>       !!* linuxbios does not assign irqs to the nics.
>         * default (2003-10-24) linuxbios src/mainboard/via/epia-m/irq_tables.c:

ok so far. 

>                 {0,0xa0, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x1, 0},

That's 0:14.0, or Bus 0, devfn 0xa0. 

>                 {0,0xa0, {{0x2, 0xdeb8}, {0x3, 0xdeb8}, {0x4, 0xdeb8}, {0x1, 0xdeb8}}, 0x1, 0},

Note that linuxbios and the standard bios agree. 

> 
>         * it does not help using the new irq_tables.c.
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mount me | 1 Dec 2003 17:07
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sst28SF040 sst28SF020 flash memories

advantech/pcm-5823 ---> does this use sst28sf040 for
having linux in it ? Or it is going to be
the Etherboot/DOC for booting of the linux ?

Could i get one advantech/pcm-5823 in india ?
Any indians with linuxbios in their board ?

firstboot,
karthik bala guru

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YhLu | 2 Dec 2003 02:05

Re: Tyan S4880

Ron,

Please check in the Tyan s2850/2880/2881/2882/4880 updates into the CVS
Tree.

1. northbridge/amd/amdk8/raminit.h: change uint8_t to uint16_t
2. southbridge/amd/amd8111/amd8111_early_smbus.c: update smbus_write_byte
3. southbridge/amd/amd8131/amd8131_bridge.c: update ioapic_anable to enable
PCI-X MASTER Mode.
4. other in /src/mainboard/tyan/ and /targets/tyan

Stefan,
With update 1 and 2, you can get ride of FAKE_SPD_ROM. You need to change
some lines in auto.c for quartet. 1. I2C HUB address: 0x30 --> 0x18, 2.
RC0-> (1<<1)<<8, RC1-> (1<<2)<<8, RC2-> (1<<3)<<8, RC3-> (1<<4)<<8.

Regards

YH.
Attachment (tyan_1201.change.diff.gz): application/octet-stream, 46 KiB
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ron minnich | 2 Dec 2003 02:43

Re: Tyan S4880

stefan and eric, we will look at these changes tomorrow. If you get a 
chance can you scan them too to make sure no obvious problems exist?

thanks

ron
p.s. Ollie, Greg, and I will be combing linuxbios source this week, 
looking at issues and working on integrating the newest LNXI code in as 
well as this code. 

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ron minnich | 2 Dec 2003 05:10

Re: Tyan S4880

I committed all this except for one thing:

diff -uNr ./freebios2/src/southbridge/amd/amd8111/amd8111_early_smbus.c ../freebios2/src/southbridge/amd/amd8111/amd8111_early_smbus.c
--- ./freebios2/src/southbridge/amd/amd8111/amd8111_early_smbus.c	2003-10-13
06:01:13.000000000 -0400
+++ ../freebios2/src/southbridge/amd/amd8111/amd8111_early_smbus.c	2003-12-01
16:14:18.000000000 -0500
 <at>  <at>  -120,24 +120,19  <at>  <at> 
 		return;
 	}

-	/* setup transaction */
-	/* disable interrupts */
-	outw(inw(SMBUS_IO_BASE + SMBGCTL) & ~((1<<10)|(1<<9)|(1<<8)|(1<<4)),
-			SMBUS_IO_BASE + SMBGCTL);
+//By LYH Begin
+	outb(0x37,SMBUS_IO_BASE + SMBGSTATUS);
 	/* set the device I'm talking too */
-	outw(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADDR);
-	outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
-	/* set up for a byte data write */ /* FIXME */
-	outw((inw(SMBUS_IO_BASE + SMBGCTL) & ~7) | (0x1), SMBUS_IO_BASE + SMBGCTL);
-	/* clear any lingering errors, so the transaction will run */
-	/* Do I need to write the bits to a 1 to clear an error? */
-	outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
+	outw(((device & 0x7f) << 1) | 0, SMBUS_IO_BASE + SMBHSTADDR);
+        
+	/* data to send */
+        outb(val, SMBUS_IO_BASE + SMBHSTDAT);
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Gmane