Zheng Bao | 12 Apr 04:39 2012

Patch set updated for coreboot: 85f52c8 Fix messy code in ALIB

Zheng Bao (zheng.bao <at> amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/885

-gerrit

commit 85f52c8e80831acb0de3898bdfad73081c091a49
Author: zbao <fishbaozi <at> gmail.com>
Date:   Thu Apr 12 11:28:11 2012 +0800

    Fix messy code in ALIB

    The address return from PICK_ALIB is not protected by Coreboot. We
    need to use the "current", which is the correct way to allocate the
    ACPI table.

    Change-Id: I250066eb5f755275f75c37789ce8760de35b046b
    Signed-off-by: Zheng Bao <zheng.bao <at> amd.com>
    Signed-off-by: zbao <fishbaozi <at> gmail.com>
---
 src/mainboard/amd/dinar/acpi_tables.c         |    3 +--
 src/mainboard/amd/inagua/acpi_tables.c        |    6 ++----
 src/mainboard/amd/persimmon/acpi_tables.c     |    6 ++----
 src/mainboard/amd/south_station/acpi_tables.c |    6 ++----
 src/mainboard/amd/union_station/acpi_tables.c |    6 ++----
 src/mainboard/asrock/e350m1/acpi_tables.c     |    6 ++----
 src/mainboard/supermicro/h8qgi/acpi_tables.c  |    3 +--
 7 files changed, 12 insertions(+), 24 deletions(-)

diff --git a/src/mainboard/amd/dinar/acpi_tables.c b/src/mainboard/amd/dinar/acpi_tables.c
index 741ba99..6fa9c6f 100644
--- a/src/mainboard/amd/dinar/acpi_tables.c
(Continue reading)

Zheng Bao | 12 Apr 04:39 2012

Patch set updated for coreboot: a7ae186 Leverage the Pstate table created by AGESA.

Zheng Bao (zheng.bao <at> amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/884

-gerrit

commit a7ae186ed9dcd7edf501c14bde5480fdaff99c2a
Author: zbao <fishbaozi <at> gmail.com>
Date:   Thu Apr 12 11:27:26 2012 +0800

    Leverage the Pstate table created by AGESA.

    The name of processor created by AGESA is P00n, whose P is
    BLDCFG_PROCESSOR_SCOPE_NAME(is 'C' if it is undefined.) and n starts
    from 0. The dsdt should be aligned with that.
    This feature has only been tested on persimmon. The changes on all the
    other boards were propagated.

    Change-Id: I8c3fa4b94406d530d2bed8e9a1f42b433bbec3ec
    Signed-off-by: Zheng Bao <zheng.bao <at> amd.com>
    Signed-off-by: zbao <fishbaozi <at> gmail.com>
---
 src/mainboard/amd/dinar/acpi/cpstate.asl         |   74 --------------
 src/mainboard/amd/dinar/acpi_tables.c            |    8 +-
 src/mainboard/amd/dinar/dsdt.asl                 |   48 +++++++---
 src/mainboard/amd/inagua/acpi/cpstate.asl        |   75 --------------
 src/mainboard/amd/inagua/acpi_tables.c           |    8 +-
 src/mainboard/amd/inagua/dsdt.asl                |   24 ++++-
 src/mainboard/amd/persimmon/acpi/cpstate.asl     |   75 --------------
 src/mainboard/amd/persimmon/acpi_tables.c        |    8 +-
 src/mainboard/amd/persimmon/dsdt.asl             |   24 ++++-
 src/mainboard/amd/south_station/acpi/cpstate.asl |   75 --------------
(Continue reading)

gerrit | 12 Apr 08:39 2012

Patch merged into coreboot/master: 624c4fe Add support for aligned allocation

the following patch was just integrated into master:
commit 624c4fed563e3bc8e8fe900f1b8ad705a1700c37
Author: Ron Minnich <rminnich <at> gmail.com>
Date:   Wed Apr 11 10:30:15 2012 -0700

    Add support for aligned allocation

    Add a memalign function and have malloc use it. Also,
    change the default alignment for malloc to u64-aligned.

    Change-Id: I0788637008f5cb5ac801d8bbdc430ca992c98e81
    Signed-off-by: Ron Minnich <rminnich <at> gmail.com>

See http://review.coreboot.org/887 for details.

-gerrit

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gerrit | 12 Apr 10:27 2012

Patch merged into coreboot/master: 25fcc40 Convert AOpen DXPL Plus mainboard to CAR

the following patch was just integrated into master:
commit 25fcc40db87b15a123d70cf64297a3ed08b31979
Author: Kyösti Mälkki <kyosti.malkki <at> gmail.com>
Date:   Wed Apr 11 12:19:03 2012 +0300

    Convert AOpen DXPL Plus mainboard to CAR

    Tested on real hardware, mainboard with dual Xeon P4 HT CPUs
    requires cache-as-ram init code with AP SIPI protocol.

    Also enable 2nd CPU and PATA and clean-up Kconfig and ACPI.

    Change-Id: I415482f3af22df79d82492c49aed83549f29aa56
    Signed-off-by: Kyösti Mälkki <kyosti.malkki <at> gmail.com>

See http://review.coreboot.org/886 for details.

-gerrit

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Zheng Bao | 12 Apr 11:00 2012

New patch to review for coreboot: 0b8964e ACPI HEST table.

Zheng Bao (zheng.bao <at> amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/888

-gerrit

commit 0b8964e47af35034c60eac1a447605c8c25c1269
Author: zbao <fishbaozi <at> gmail.com>
Date:   Thu Apr 12 17:49:37 2012 +0800

    ACPI HEST table.

    HEST feature starts from ACPI 4.0.

    HEST is one of four kinds of tables of ACPI Platform Error
    Interfaces (APEI). In Windows world, APEI is called Windows Hardware
    Error Architecture (WHEA).

    APEI consists of four separate tables:
    1. Error Record Serialization Table (ERST)
    2. BOOT Error Record Table (BERT)
    3. Hardware Error Source Table (HEST)
    4. Error Injection Table (EINJ)
    All these 4 tables have the same header as FADT, MADT, etc. They are
    pointed by RSDP.

    For the HEST, it contains the error source. The types of them are
    defined as
    type  description
    1.    Machine Check Exception (MCE)
    2.    Corrected Machine Check (CMC)
    3.    NMI Error
(Continue reading)

Denis 'GNUtoo' Carikli | 12 Apr 13:45 2012

Hyper Transport init for M4A785T-M

Hi,

I've still my screen flickering issues(screen flickers for resolutions which are 
superior to 832x624 ) on the M4A785T-M mainboard.

I've been investigating and here's what I found:

In src/southbridge/amd/rs780/early_setup.c there is:
        printk(BIOS_INFO, "rs780_htinit cpu_ht_freq=%x.\n", cpu_ht_freq);
In the rs780_htinit function, which prints 0 as cpu_ht_freq.

Then it assumes the CPU is k8 (I've a fam10h: model name	: AMD Athlon(tm) II 
X2 250 Processor) and it doesn't do the right init for my rs780.

Here is a call graph of the  initialization of the Hyper Transport:

amd_ht_init(src/northbridge/amd/amdht/ht_wrapper.c)
|->amdHtInitialize(northbridge/amd/amdht/h3finit.c)
   |->linkOptimization(northbridge/amd/amdht/h3finit.c)
      |->coherentInit(northbridge/amd/amdht/h3finit.c)
         |->htDiscoveryFloodFill(northbridge/amd/amdht/h3finit.c)
              \-> pDat->nb->verifyLinkIsCoherent always return false and so:
                     the for loop is executed 8 times, but each time the
                     follownig function returns false(and so it runs the
                     continue instruction):
                     if (!pDat->nb->verifyLinkIsCoherent(...)) 
                     and so it doesn't run what's next which prevent
                     TotalLinks from beeing incremented.
               |->verifyLinkIsCoherent(northbridge/amd/amdht/h3ncmn.c)
                     \->max_nodes=8,link goes from 0 to 7,and node is always 0
(Continue reading)

Patrick Georgi | 12 Apr 15:05 2012

New patch to review for coreboot: 42e55bb More portable s3 scratch space creation

Patrick Georgi (patrick <at> georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/889

-gerrit

commit 42e55bbf332c7c5f137c02c40a124237ebad42fb
Author: Patrick Georgi <patrick.georgi <at> secunet.com>
Date:   Thu Apr 12 15:03:22 2012 +0200

    More portable s3 scratch space creation

    echo -n isn't portable. echo -e isn't portable. that bash loop isn't portable.
    So let's try something else.

    Change-Id: Ie73aa1c09d90c11a5c4952a332d4c2058390b5db
    Signed-off-by: Patrick Georgi <patrick.georgi <at> secunet.com>
---
 src/southbridge/amd/Makefile.inc |    5 +++--
 1 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc
index 2cdca29..b4e0982 100644
--- a/src/southbridge/amd/Makefile.inc
+++ b/src/southbridge/amd/Makefile.inc
 <at>  <at>  -17,8 +17,9  <at>  <at>  subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx

 $(obj)/s3.rom:
 	echo "    S3 NVRAM   0xffff0000 (S3 storage area)"
-	echo -ne '\xFF' > $ <at> 
-	for ((i=0;i<20479;i++)) do echo -ne '\xFF' >> $ <at>  ; done
+	# create 20480 bytes of 0xff
(Continue reading)

Patrick Georgi | 12 Apr 15:26 2012

New patch to review for coreboot: cf2748d lint: tighten whitespace check some more

Patrick Georgi (patrick <at> georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/890

-gerrit

commit cf2748dfffc75ca94e5397e59e549c1e451b9dcd
Author: Patrick Georgi <patrick.georgi <at> secunet.com>
Date:   Thu Apr 12 15:23:58 2012 +0200

    lint: tighten whitespace check some more

    Don't test executable files nor object files, even if the former might
    render the test useless on win32 (executable bit isn't well defined there).

    Change-Id: Ifb6fc83243289d266f439316c14b6b009f8da5fc
    Signed-off-by: Patrick Georgi <patrick.georgi <at> secunet.com>
---
 util/lint/lint-stable-003-whitespace |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace
index a5ca540..6869a44 100755
--- a/util/lint/lint-stable-003-whitespace
+++ b/util/lint/lint-stable-003-whitespace
 <at>  <at>  -20,6 +20,7  <at>  <at> 

 LC_ALL=C export LC_ALL
 find src util -name .svn -type d -prune -o \
+	-perm +111 -prune -o \
 	-name .git -type d -prune -o \
 	-name README -prune -o \
(Continue reading)

Patrick Georgi | 12 Apr 15:27 2012

Patch set updated for coreboot: fcb4358 More portable s3 scratch space creation

Patrick Georgi (patrick <at> georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/889

-gerrit

commit fcb4358908704fa31adc3eb051692307fc2a89ce
Author: Patrick Georgi <patrick.georgi <at> secunet.com>
Date:   Thu Apr 12 15:03:22 2012 +0200

    More portable s3 scratch space creation

    echo -n isn't portable. echo -e isn't portable. that bash loop isn't portable.
    So let's try something else.

    Change-Id: Ie73aa1c09d90c11a5c4952a332d4c2058390b5db
    Signed-off-by: Patrick Georgi <patrick.georgi <at> secunet.com>
---
 src/southbridge/amd/Makefile.inc |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/southbridge/amd/Makefile.inc b/src/southbridge/amd/Makefile.inc
index 2cdca29..f4a9cbb 100644
--- a/src/southbridge/amd/Makefile.inc
+++ b/src/southbridge/amd/Makefile.inc
 <at>  <at>  -17,8 +17,8  <at>  <at>  subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx

 $(obj)/s3.rom:
 	echo "    S3 NVRAM   0xffff0000 (S3 storage area)"
-	echo -ne '\xFF' > $ <at> 
-	for ((i=0;i<20479;i++)) do echo -ne '\xFF' >> $ <at>  ; done
+	awk 'BEGIN {for (i=0; i<20480; i++) {printf "%c", 255}}' > $ <at> .tmp
(Continue reading)

Uwe Hermann | 12 Apr 21:44 2012

New patch to review for coreboot: 6967e3f kconfig: Fix 'make gconfig'.

Uwe Hermann (uwe <at> hermann-uwe.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/891

-gerrit

commit 6967e3f7239b3afe9c73ac97c6035c52d828b1a2
Author: Uwe Hermann <uwe <at> hermann-uwe.de>
Date:   Thu Apr 12 21:39:27 2012 +0200

    kconfig: Fix 'make gconfig'.

    Change-Id: Id2d0735d875b40e131fc2aada27435fdcbacc8cb
    Signed-off-by: Uwe Hermann <uwe <at> hermann-uwe.de>
---
 util/kconfig/Makefile |    1 +
 util/kconfig/lkc.h    |    2 +-
 2 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/util/kconfig/Makefile b/util/kconfig/Makefile
index 0e108a3..6cdc845 100644
--- a/util/kconfig/Makefile
+++ b/util/kconfig/Makefile
 <at>  <at>  -16,6 +16,7  <at>  <at>  xconfig: $(objk)/qconf
 	$(objk)/qconf $(Kconfig)

 gconfig: $(objk)/gconf
+	cp -f $(srck)/gconf.glade $(objk)/gconf.glade
 	$(objk)/gconf $(Kconfig)

 menuconfig: $(objk)/mconf
diff --git a/util/kconfig/lkc.h b/util/kconfig/lkc.h
(Continue reading)


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