repository service | 1 Oct 01:15 2010

[commit] r5888 - in trunk/src/cpu: amd/car intel/car via/car

Author: uwe
Date: Fri Oct  1 01:15:36 2010
New Revision: 5888
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5888

Log:
Various cosmetic and coding style fixes in CAR code (trivial).

Also, whitespace fixes, consistency fixes, and drop some of the less
useful comments.

Signed-off-by: Uwe Hermann <uwe <at> hermann-uwe.de>
Acked-by: Uwe Hermann <uwe <at> hermann-uwe.de>

Modified:
   trunk/src/cpu/amd/car/cache_as_ram.inc
   trunk/src/cpu/intel/car/cache_as_ram.inc
   trunk/src/cpu/via/car/cache_as_ram.inc

Modified: trunk/src/cpu/amd/car/cache_as_ram.inc
==============================================================================
--- trunk/src/cpu/amd/car/cache_as_ram.inc	Thu Sep 30 23:22:40 2010	(r5887)
+++ trunk/src/cpu/amd/car/cache_as_ram.inc	Fri Oct  1 01:15:36 2010	(r5888)
 <at>  <at>  -18,76 +18,82  <at>  <at> 
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

-#define CacheSize CONFIG_DCACHE_RAM_SIZE
-#define CacheBase (0xd0000 - CacheSize)
+#include <cpu/x86/mtrr.h>
(Continue reading)

Jonathan A. Kollasch | 1 Oct 01:26 2010
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[patch] spelling fixes for comments in src/northbridge/amd/amdk8/misc_control.c

Fix spelling/typos in comments.

Signed-off-by: Jonathan Kollasch <jakllsch <at> kollasch.net>
---
Index: src/northbridge/amd/amdk8/misc_control.c
===================================================================
--- src/northbridge/amd/amdk8/misc_control.c	(revision 5887)
+++ src/northbridge/amd/amdk8/misc_control.c	(working copy)
 <at>  <at>  -1,6 +1,6  <at>  <at> 
 /* Turn off machine check triggers when reading
- * pci space where there are no devices.
- * This is necessary when scaning the bus for
+ * PCI space where there are no devices.
+ * This is necessary when scanning the bus for
  * devices which is done by the kernel
  *
  * written in 2003 by Eric Biederman
 <at>  <at>  -26,13 +26,13  <at>  <at> 
  *
  *  <at> param
  *
- * There is only one AGP aperture resource needed. The resoruce is added to
+ * There is only one AGP aperture resource needed. The resource is added to
  * the northbridge of BSP.
  *
  * The same trick can be used to augment legacy VGA resources which can
- * be detect by generic pci reousrce allocator for VGA devices.
+ * be detect by generic PCI resource allocator for VGA devices.
(Continue reading)

Peter Stuge | 1 Oct 01:33 2010
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Re: [PATCH] Make hidden configuration flags visible (i945)

Patrick Georgi wrote:
> attached patch moves several config flags that, for historical
> reasons, were put in romstage.c into Kconfig.

In principle I think this is a great improvement!

But some comments..

> +++ src/northbridge/intel/i945/Kconfig	(Arbeitskopie)
>  <at>  <at>  -26,3 +26,43  <at>  <at> 
>  	default "8086,27a2"
>  	depends on NORTHBRIDGE_INTEL_I945
>  
> +choice
> +	prompt "Chipset variant"
> +	default I945GM
> +	depends on NORTHBRIDGE_INTEL_I945
> +	help
> +	  Different i945 variants require slightly different setup.
> +
> +config I945GM
> +	bool "i945GM (Mobile) chipset"
> +
> +config I945GC
> +	bool "i945GC chipset"
> +
> +endchoice

I think GC should come first and maybe even be the default, because
it's the base chipset and C < M.
(Continue reading)

Peter Stuge | 1 Oct 01:35 2010
Picon

Re: [patch] spelling fixes for comments in src/northbridge/amd/amdk8/misc_control.c

Jonathan A. Kollasch wrote:
> Fix spelling/typos in comments.
> 
> Signed-off-by: Jonathan Kollasch <jakllsch <at> kollasch.net>

This is fine to self-ack. Anyway,

Acked-by: Peter Stuge <peter <at> stuge.se>

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Jonathan A. Kollasch | 1 Oct 03:03 2010
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[patch] drop meaningless K8_4RANK_DIMM_SUPPORT define

Don't define K8_4RANK_DIMM_SUPPORT, nothing uses it.
All these boards define QRANK_DIMM_SUPPORT anyway,
which is probably what was meant.

Signed-off-by: Jonathan Kollasch <jakllsch <at> kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch <at> kollasch.net>
---
Index: src/mainboard/msi/ms9282/romstage.c
===================================================================
--- src/mainboard/msi/ms9282/romstage.c	(revision 5888)
+++ src/mainboard/msi/ms9282/romstage.c	(working copy)
 <at>  <at>  -96,8 +96,6  <at>  <at> 
        return smbus_read_byte(device, address);
 }

-//#define K8_4RANK_DIMM_SUPPORT 1
-
 #include "northbridge/amd/amdk8/amdk8_f.h"
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "northbridge/amd/amdk8/coherent_ht.c"
Index: src/mainboard/asus/a8v-e_se/romstage.c
===================================================================
--- src/mainboard/asus/a8v-e_se/romstage.c	(revision 5888)
+++ src/mainboard/asus/a8v-e_se/romstage.c	(working copy)
 <at>  <at>  -100,8 +100,6  <at>  <at> 
 // defines S3_NVRAM_EARLY:
 #include "southbridge/via/k8t890/k8t890_early_car.c"

(Continue reading)

Keith Hui | 1 Oct 06:31 2010
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[PATCH] Drop unneeded header from i82371eb_enable_rom.c

A "I am alive" ping kind of patch while I continue to figure out ACPI
for 440BX boards among other things.

Drops <stdint.h> from the file. My coreboot still compiles fine
without it. abuild tested.

Signed-off-by: Keith Hui <buurin <at> gmail.com>
Attachment (i82371eb_rom_drop_stdint.patch): application/octet-stream, 510 bytes
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repository service | 1 Oct 08:27 2010

[commit] r5889 - in trunk/src/northbridge/amd/amdmct: mct mct_ddr3

Author: zbao
Date: Fri Oct  1 08:27:35 2010
New Revision: 5889
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5889

Log:
Trivial. Re-indent the code.

Signed-off-by: Zheng Bao <zheng.bao <at> amd.com>
Acked-by: Zheng Bao <zheng.bao <at> amd.com>

Modified:
   trunk/src/northbridge/amd/amdmct/mct/mctchi_d.c
   trunk/src/northbridge/amd/amdmct/mct/mctsrc.c
   trunk/src/northbridge/amd/amdmct/mct/mcttmrl.c
   trunk/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c
   trunk/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
   trunk/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c

Modified: trunk/src/northbridge/amd/amdmct/mct/mctchi_d.c
==============================================================================
--- trunk/src/northbridge/amd/amdmct/mct/mctchi_d.c	Fri Oct  1 01:15:36 2010	(r5888)
+++ trunk/src/northbridge/amd/amdmct/mct/mctchi_d.c	Fri Oct  1 08:27:35 2010	(r5889)
 <at>  <at>  -65,9 +65,9  <at>  <at> 
 				DramBase = pDCTstat->NodeSysBase >> 8;
 				dct1_size = ((pDCTstat->NodeSysLimit) + 2) >> 8;
 				dct0_size = Get_NB32(pDCTstat->dev_dct, 0x114);
-					if (dct0_size >= 0x10000) {
-						dct0_size -= HoleSize;
-					}
(Continue reading)

Patrick Georgi | 1 Oct 09:00 2010
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Re: [PATCH] Make hidden configuration flags visible (i945)

Am 01.10.2010 01:33, schrieb Peter Stuge:
> That said, would it work to simply make these options be
> NORTHBRIDGE_INTEL_I945GC and _I945GM, and have both of them then
> select in the common (current) I945 code? That way there only needs
> to be one select for this in mainboards, it's hidden from users, and
> it can't really become incorrect.
Thought about it - why I didn't do that: It significantly changes the
design of that part of the code.
The change above simply moves stuff around.

Patrick

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coreboot | 1 Oct 09:22 2010

Re: #152: v3 Geode cs5536 UART2 wrongly configured

#152: v3 Geode cs5536 UART2 wrongly configured
--------------------------------------------+-------------------------------
    Reporter:  edwin_beasant <at> …              |          Owner:  hailfinger      
        Type:  defect                       |         Status:  closed          
    Priority:  major                        |      Milestone:  Going mainstream
   Component:  coreboot                     |     Resolution:  fixed           
    Keywords:  serial com2 geode cs5536     |   Dependencies:                  
Patch Status:  patch has been committed     |  
--------------------------------------------+-------------------------------
Changes (by uwe):

  * status:  new => closed
  * patchstatus:  patch is ready to be committed => patch has been
                  committed
  * resolution:  => fixed

Comment:

 Patch was comitted for v2, and v3 is obsolete now, so closing the issue.

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coreboot | 1 Oct 09:23 2010

Re: #82: Fix the memory map in coreboot v3

#82: Fix the memory map in coreboot v3
----------------------------------+-----------------------------------------
    Reporter:  oxygene            |          Owner:  hailfinger            
        Type:  defect             |         Status:  closed                
    Priority:  major              |      Milestone:  Setting up coreboot v3
   Component:  coreboot           |     Resolution:  abandoned             
    Keywords:                     |   Dependencies:                        
Patch Status:  there is no patch  |  
----------------------------------+-----------------------------------------
Changes (by uwe):

  * status:  new => closed
  * resolution:  => abandoned

Comment:

 v3 is obsolete, closing issue.

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