stephan.guilloux | 8 May 01:05 2009
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Re: [PATCH] flashrom: Handle one-byte SPI writes

  Hello,

This might work, but, if I can say, I don't like the idea of renaming the
ich_spi_write to ich_spi_write_256.

1) ich_spi_write() looks to be the generic one, then, this one has the good
name.
2) ich_spi_write() should already use something, stored in the relevant
flashchips[] item, to perform byte, page sector or block write operations. If we
come to make it more "generic", all will have to be renamed back again.

  Stephan.

Selon Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 <at> gmx.net>:

> Chips like the SST SST25VF080B can only handle single byte writes
> outside AAI mode.
>
> Change SPI architecture to handle 1-byte chunk chip writing differently
> from 256-byte chunk chip writing.
>
> Convert all flashchips.c entries with SPI programing to the 256-byte
> version by default.
>
> Change the flashchips entry for SST SST25VF080B to 1-byte writing.
>
> Untested.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 <at> gmx.net>
>
(Continue reading)

Carl-Daniel Hailfinger | 8 May 02:12 2009
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Re: [PATCH] flashrom: Handle one-byte SPI writes

Hi,

On 08.05.2009 01:05, stephan.guilloux <at> free.fr wrote:
> This might work, but, if I can say, I don't like the idea of renaming the
> ich_spi_write to ich_spi_write_256.
>
> 1) ich_spi_write() looks to be the generic one, then, this one has the good
> name.
>   

The big problem is that the standard says something about 1-byte writes
being the default. Many vendors extended that to 256-byte writes (or 16
or even full-chip), depending on the exact flash chip model.

> 2) ich_spi_write() should already use something, stored in the relevant
> flashchips[] item, to perform byte, page sector or block write operations. If we
> come to make it more "generic", all will have to be renamed back again.
>   

Indeed. We should add more info to struct flashchip. Realistically, that
will only happen after my dozen pending flashrom patches (cleanup,
bugfixes and architecture iprovements) are merged.

Regards,
Carl-Daniel

> Selon Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 <at> gmx.net>:
>
>   
>> Chips like the SST SST25VF080B can only handle single byte writes
(Continue reading)

svn | 8 May 02:19 2009

[v2] r4258 - trunk/coreboot-v2/src/mainboard/thomson/ip1000

Author: linux_junkie
Date: 2009-05-08 02:19:13 +0200 (Fri, 08 May 2009)
New Revision: 4258

Modified:
   trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c
Log:
Disable the AC97 modem via the ICH4 LPC disable function register early in the boot process.
Signed-off-by: Joseph Smith <joe <at> settoplinux.org>
Acked-by: Myles Watson <mylesgw <at> gmail.com>

Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c	2009-05-07 05:47:05 UTC (rev 4257)
+++ trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c	2009-05-08 00:19:13 UTC (rev 4258)
 <at>  <at>  -43,6 +43,9  <at>  <at> 
 	set_gpio |= 1 << 23;
 	outl(set_gpio, ICH_IO_BASE_ADDR + 0x0c);

+	/* Disable AC97 Modem */
+	pci_write_config8(dev, 0xf2, 0x40);
+
 	/* Super I/O GPIOs. */
 	dev = PME_DEV;
 	port = dev >> 8;

--

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Joseph Smith | 8 May 02:20 2009

Re: [PATCH] Disable AC97 modem early on IP1000


On Thu, 7 May 2009 15:55:11 -0600, "Myles Watson" <mylesgw <at> gmail.com>
wrote:
> 
> 
>> -----Original Message-----
>> From: coreboot-bounces <at> coreboot.org
> [mailto:coreboot-bounces <at> coreboot.org]
>> On Behalf Of Joseph Smith
>> Sent: Thursday, May 07, 2009 12:09 AM
>> To: coreboot
>> Subject: Re: [coreboot] [PATCH] Disable AC97 modem early on IP1000
>>
>>
>>
>> On Thu, 07 May 2009 02:01:18 -0400, Joseph Smith <joe <at> settoplinux.org>
>> wrote:
>> >
>> > This patch disables the AC97 modem via the ICH4 LPC disable function
>> > register early in the boot process. Leaving it enabled was causing
>> > resource
>> > allocation problems, making IO read/writes under 0x200 fail. As I
> found
>> > out
>> > by trail and error it has to be done right after the LAN Enable gpio
> pin
>> > is
>> > driven high.
>> >
>> > Tested on hardware.
(Continue reading)

svn | 8 May 02:24 2009

[v2] r4259 - in trunk/coreboot-v2/src/mainboard: rca/rm4100 thomson/ip1000

Author: linux_junkie
Date: 2009-05-08 02:24:24 +0200 (Fri, 08 May 2009)
New Revision: 4259

Modified:
   trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb
   trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb
Log:
Set up PIRQs in mainboard Config.lb for IP1000 and RM4100 instead of using the ones in i82801xx_lpc.c.
Signed-off-by: Joseph Smith <joe <at> settoplinux.org>
Acked-by: Myles Watson <mylesgw <at> gmail.com>

Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb	2009-05-08 00:19:13 UTC (rev 4258)
+++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb	2009-05-08 00:24:24 UTC (rev 4259)
 <at>  <at>  -80,6 +80,15  <at>  <at> 
       register "rom_address" = "0xfff00000"
     end
     chip southbridge/intel/i82801xx	# Southbridge
+      register "pirqa_routing" = "0x07"
+      register "pirqb_routing" = "0x09"
+      register "pirqc_routing" = "0x0a"
+      register "pirqd_routing" = "0x09"
+      register "pirqe_routing" = "0x05"
+      register "pirqf_routing" = "0x80"
+      register "pirqg_routing" = "0x80"
+      register "pirqh_routing" = "0x0b"
+
       device pci 1d.0 on end		# USB UHCI Controller #1
(Continue reading)

Joseph Smith | 8 May 02:25 2009

Re: [PATCH] Assign PIRQs in mainboard Config.lb for IP1000and RM4100


On Thu, 7 May 2009 15:55:37 -0600, "Myles Watson" <mylesgw <at> gmail.com>
wrote:
> 
> 
>> -----Original Message-----
>> From: coreboot-bounces <at> coreboot.org
> [mailto:coreboot-bounces <at> coreboot.org]
>> On Behalf Of Joseph Smith
>> Sent: Thursday, May 07, 2009 12:12 AM
>> To: coreboot
>> Subject: [coreboot] [PATCH] Assign PIRQs in mainboard Config.lb for
>> IP1000and RM4100
>>
>> This patch sets up PIRQs in mainboard Config.lb for IP1000 and RM4100
>> instead of using the ones in i82801xx_lpc.c
>>
>> Signed-off-by: Joseph Smith <joe <at> settoplinux.org>
> Acked-by: Myles Watson <mylesgw <at> gmail.com>
> 
Thanks Myles, r4259

-- 
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org

--

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(Continue reading)

svn | 8 May 02:45 2009

[v2] r4260 - in trunk/coreboot-v2: src/mainboard/rca/rm4100 src/mainboard/thomson/ip1000 targets/thomson/ip1000

Author: linux_junkie
Date: 2009-05-08 02:45:47 +0200 (Fri, 08 May 2009)
New Revision: 4260

Modified:
   trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb
   trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb
   trunk/coreboot-v2/targets/thomson/ip1000/Config.lb
Log:
Trivial fixup IRQS on IP1000 and RM4100.
Signed-off-by: Joseph Smith <joe <at> settoplinux.org>
Acked-by: Joseph Smith <joe <at> settoplinux.org>

Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb	2009-05-08 00:24:24 UTC (rev 4259)
+++ trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb	2009-05-08 00:45:47 UTC (rev 4260)
 <at>  <at>  -80,11 +80,11  <at>  <at> 
       register "rom_address" = "0xfff00000"
     end
     chip southbridge/intel/i82801xx	# Southbridge
-      register "pirqa_routing" = "0x07"
-      register "pirqb_routing" = "0x09"
-      register "pirqc_routing" = "0x0a"
+      register "pirqa_routing" = "0x05"
+      register "pirqb_routing" = "0x06"
+      register "pirqc_routing" = "0x07"
       register "pirqd_routing" = "0x09"
-      register "pirqe_routing" = "0x05"
+      register "pirqe_routing" = "0x0a"
(Continue reading)

Carl-Daniel Hailfinger | 8 May 02:45 2009
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[PATCH] flashrom: Trim default ICH SPI delay from 1000 to 10 microseconds

Trim default ICH SPI delay from 1000 to 10 microseconds. Since many
commands take around 10 microseconds to complete, it is totally
pointless to wait for 1000 microseconds before checking the status again.

This patch is tested and reduced write time on ICH7 with SST25VF080B
from over one hour to 62 seconds.

Thanks to Ali Nadalizadeh for testing!

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 <at> gmx.net>

Index: flashrom-ichspi_delay/ichspi.c
===================================================================
--- flashrom-ichspi_delay/ichspi.c	(Revision 471)
+++ flashrom-ichspi_delay/ichspi.c	(Arbeitskopie)
 <at>  <at>  -458,9 +458,9  <at>  <at> 
 	REGWRITE16(ICH7_REG_SPIC, temp16);

 	/* wait for cycle complete */
-	timeout = 1000 * 60;	// 60s is a looong timeout.
+	timeout = 100 * 1000 * 60;	// 60s is a looong timeout.
 	while (((REGREAD16(ICH7_REG_SPIS) & SPIS_CDS) == 0) && --timeout) {
-		myusec_delay(1000);
+		myusec_delay(10);
 	}
 	if (!timeout) {
 		printf_debug("timeout\n");
 <at>  <at>  -575,9 +575,9  <at>  <at> 
 	REGWRITE32(ICH9_REG_SSFS, temp32);

(Continue reading)

Carl-Daniel Hailfinger | 8 May 02:57 2009
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[PATCH] flashrom: External flasher support

To prepare flashrom for Paraflasher (or other external flasher) support,
each chip read/write access is either handled as memory mapped access or
external flasher cycle.

External flashers can set the flasher variable to their own ID/number
during startup and handle accesses in the switch statement inside
chip_{read,write}[bwl].

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 <at> gmx.net>

Index: flashrom-external_infrastructure/flash.h
===================================================================
--- flashrom-external_infrastructure/flash.h	(Revision 471)
+++ flashrom-external_infrastructure/flash.h	(Arbeitskopie)
 <at>  <at>  -76,36 +76,6  <at>  <at> 
 #endif
 #endif

-static inline void chip_writeb(uint8_t b, volatile void *addr)
-{
-	*(volatile uint8_t *) addr = b;
-}
-
-static inline void chip_writew(uint16_t b, volatile void *addr)
-{
-	*(volatile uint16_t *) addr = b;
-}
-
-static inline void chip_writel(uint32_t b, volatile void *addr)
-{
(Continue reading)

Kevin O'Connor | 8 May 03:02 2009
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Re: GSoC: Seabios USB Option ROM, small initial planning

On Wed, May 06, 2009 at 10:05:34AM -0400, Leandro Dorileo wrote:
> For now, I have two major questions, #1: I`ve seen other projects like
> FILO including libpayload with svn:external, once seabios is
> maintained with git, how it should be done with seabios? how would we
> manage the source code integration and maintainability between seabios
> and libpayload?. #2: libpayload uses kbuild/kconfig but seabios
> doesn`t, what would be the best approach to integrate their build
> system? (PS: Sorry, it wasn`t two questions, but many questions and
> two areas. ;-) )

As I understand the GSOC project, it is to build an option rom that
provides usb services to applications that use legacy bios functions.
I don't believe the project is specific to SeaBIOS.  That is, the
project is to build an option rom that uses libpayload, not to add
libpayload to SeaBIOS.

-Kevin

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