Daniel Kulesz via coreboot | 1 May 00:55 2016

Lenovo X200 running Coreboot drains 3-4W more power than with Vendor BIOS


I was wondering why my Lenovo X200 had such a short battery lifetime when running Libreboot/Coreboot, so I
did a few measurements using the following hardware configuration:

X200 with P8700 CPU
LED Display (yes, one of the rare ones)
OCZ Trion SSD (unused, just idling)
Wifi and WWAN removed
Battery removed
Ubuntu MATE 16.04 Live running from an USB thumb drive
No tweaking with powertop or such

I kept this configuration unchanged except for the BIOS and waited 5 minutes after booting, so the system
could settle. Then I measured power consumption both at full brightness and at minimum brightness using a
conventional power meter (EKM 365) which was plugged between the AC adapter and the power socket in the wall.

I obtained the following numbers:

Vendor BIOS: 7,5W (lowest) to 10W (highest)
Libreboot 20150518 (using the precompiled binary binary): 13,3W (lowest) to 16,1W (highest)
Latest Coreboot, config attached (80a3df260767a6d9ad34b61572d483579c21476c): 10,4W (lowest) to
13,4W (highest)

While Libreboot performs much worse than Coreboot, Coreboot still eats around 3W extra when compared with
the vendor BIOS. In other words: Coreboot consumes around 30-40% more juice than the vendor BIOS which is a
very sad result for an ultraportable notebook.

Is this a known issue? Has someone else tried the same and obtained different numbers?
(Continue reading)

Alexander Böcken | 28 Apr 10:38 2016

Microcode problem with Braswell CPU

Hi community,

I'm trying to get coreboot running on a Braswell CPU but it hangs when updating the microcode. I'm stuck in
bootblock before CAR and could pin down the problem to the intel_microcode_load_unlocked function in
src/cpu/intel/microcode.c where coreboot writes the microcode base address to the
IA32_BIOS_UPDT_TRIG register (0x79).

    outb(0xF7, 0x80);

    msr.lo = (unsigned long)m + sizeof(struct microcode);
    msr.hi = 0;
    wrmsr(0x79, msr);
    outb(0xF8, 0x80);

The outb calls have been added by me, and F7 is just the last post code I see, a few seconds before the CPU
reboots. It never reaches F8. So I checked the microcode that I've received from Intel and everything
seems fine. The microcode signature matches the CPUID, the platform flags match, the checksum correctly
yields to zero, and the base address is aligned on a 16-byte boundary. Some checks are also done by coreboot
at runtime. I just can't figure out what the problem is here.

Some more Info:

$ build/cbfstool build/coreboot.rom print
Performing operation on 'COREBOOT' region...
Name                           Offset     Type         Size
cbfs master header             0x0        cbfs header  32
fallback/romstage              0x80       stage        30660
fallback/ramstage              0x78c0     stage        63482
fallback/payload               0x17100    payload      61118
(Continue reading)

Martin Roth | 25 Apr 22:55 2016

coreboot conference in SFO

Hi everyone.  I've just sent out an email to everyone who is currently
registered for the coreboot conference.  If you believe that you are
registered and did not get the email, please check with me.

Please remember that fees for registration go up $50 after May 1.
Additionally, because Apple is having their annual developer
conference in San Francisco the same week as the coreboot conference,
we would recommend that anyone who plans on attending book their hotel
rooms as soon as possible.

Sign up here: http://goo.gl/forms/f8uqHHFL2S

The conference schedule: https://goo.gl/WF9al6

All of the information about the conference can be found on the coreboot wiki:



coreboot mailing list: coreboot <at> coreboot.org

Zheng Bao | 26 Apr 09:20 2016

Does ChromeOS-EC have to boot ChromeOS?


Hi, Stafan & All,
I am trying to build a platform which uses AMD APU + EC.

My goal is let EC
1. give the power sequencing logic to APU
2. play as a generic EC which has features like keyboard, UART.

Currently, I don't have plan to boot chrome OS yet.

So I need you guys give me some advice.
Does chromeOS-EC meet my requirement?
Is it OK if I don't boot chromeOS? Is chromeOS-EC hard to master?



coreboot mailing list: coreboot <at> coreboot.org
Daniel Kulesz via coreboot | 25 Apr 19:24 2016

Issue Tracker down?


I just wanted to report bug regarding memory initialization on the F2A85-M, but it looks like the issue
tracker is down:

502 Bad Gateway
nginx/1.4.6 (Ubuntu)

Cheers, Daniel


coreboot mailing list: coreboot <at> coreboot.org

Dylan Staley | 23 Apr 05:44 2016

Building with SeaBIOS and serial debugging

I've been attempting to get coreboot running on my Lenovo ThinkPad x230 (a supported mainboard). From the serial output I'm currently getting, it looks like coreboot is getting to the part where it loads the payload (in my case SeaBIOS), but I guess SeaBIOS isn't configured to output debug information to the serial output. This is my console output: https://gist.github.com/dstaley/73ad18b9a73eb60e5fb100972a690ef1 and my .config file https://gist.github.com/dstaley/cf2d9b2955bcfb9052b33f1b981efeb4

From reading the Makefile in payloads/external/SeaBIOS, both CONFIG_CONSOLE_SERIAL and CONFIG_DRIVERS_UART_8250IO need to be set. However, I can't seem to find which config file I need to modify to properly set these variables. Additionally, CONFIG_TTYS0_BASE needs to be set as well.

I've also attempted to manually build SeaBIOS with serial output enabled, but that didn't seem to have any impact on the result.

So, in short, how do I configure coreboot in such a way so that SeaBIOS is properly set to output debug information to the serial console (in this case via a FTDI FT232H USB cable)?


coreboot mailing list: coreboot <at> coreboot.org
Stefan Reinauer | 21 Apr 21:19 2016

coreboot toolchain update after 4.4 release

Hi folks!

We're planning to update the coreboot reference toolchain very soon now,
right after the coreboot 4.4 release which will roughly happen at the
end of this month.

We have fixed a few issues with the new toolchain already, and I am
building and running coreboot images with the new toolchain daily, but
we need more testing from all of you and for all of your coreboot
systems. So please: Build the new toolchain and build and run coreboot
images with it during the next week!

The patch for updating the toolchain is here:

How to build the new toolchain
$ cd coreboot/
$ git fetch https://review.coreboot.org/coreboot
refs/changes/27/14227/11 && git cherry-pick FETCH_HEAD
$ rm -r util/crossgcc/xgcc
$ make crossgcc CPUS=4 # replace with your number of CPU cores
<wait for a while, have lunch or coffee>
$ rm .xcompile



coreboot mailing list: coreboot <at> coreboot.org
ron minnich | 19 Apr 19:28 2016

coreboot convention update

The coreboot convention is coming along very well. Just today we've been able to schedule a talk which I think you are going to enjoy: Ms. Joanna Rutkowska of the Invisible Things Lab, and one of the inventors of Qubes, will be presenting her ideas on the Stateless Laptop on Monday, June 13. Put simply, she is advocating for removable firmware modules to create a truly stateless system. I am hoping we can also discuss using Qubes as a coreboot payload.

If you are coming, you should start looking at hotels. There are deals to be found. I just booked a pretty nice hotel not far from Google SF for about 225 a night. But, warning! Apple has just announced that their big developer week is the same as our convention. So, if you're going to come out, move fast before the hotels all evaporate!

If you want to give a talk, please let us know soon. The talk slots are getting filled quickly. If you have a short talk, of a practical nature, we have 30 minute slots still open on the first two days, and will have room for such talks on Wednesday and Thursday.

If you want to see the Long Now, it's also a good idea to register soon; that event is space-limited due to city regulations.

Thanks,if you have questions please get in touch.


coreboot mailing list: coreboot <at> coreboot.org
Adrian Perez Resa | 19 Apr 16:27 2016

Using High Speed UART1 as Serial port on CoreBoot (MinnowBoard)

Hello everybody,


I am newby with minnow board and CoreBoot.

I am trying to use HIGH Speed UART1 as Serial port on CoreBoot (SIO_UART 1 pins) with no success.


I have tried to configure CoreBoot with the following options:

-          Console > Index for UART port to use for console -> ‘0’

o   Baud rate 115200


But I don’t know exactly what serial port I am using…


High speed UART 1 (SIO UART 1) is connected to JP1 Header in minnow Board.

However, Serial port seems to be always on the default debug UART (connector J4 on Minnow Board).

This Debug UART is attached at ATOM GPIOS GPIO_S0_SC_57 and GPIO_S0_SC_61 pins.


Does anybody know what options are necessary to change for using a different uart than the default one…?


Thanks in advance!


Best regards



Adrian Perez Resa
Innovación y Desarrollo
Telnet Redes Inteligentes S.A.
Tel: (+34)976 141 800   -   Fax: (+34)976 141 810


coreboot mailing list: coreboot <at> coreboot.org
daoud yessine | 19 Apr 02:07 2016

Coreboot on ARM


Is coreboot a replacement of x-oader (MLO) on arm systems  ?
So coreboot will be placed in the boot partition on the SD/card (e.g ) and it will be named MLO to be called by the rom code ??


coreboot mailing list: coreboot <at> coreboot.org
Daniel Kulesz via coreboot | 18 Apr 23:54 2016

F2A85-M: A10-6800k (Richland) supported?


is or was someone able to run the A10-6800k on the F2A85-M successfully? If yes, are any extra patches required?

Cheers, Daniel


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