WordPress | 11 Feb 20:08 2016

New on blogs.coreboot.org: coreboot changelog Feb 3 - Feb 9

A new post titled "coreboot changelog Feb 3 - Feb 9" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2016/02/11/coreboot-changelog-feb-3-feb-9/

This changelog covers 107 commits in the week between February 3, 2016 and February 9, 2016. (2cc2ff6f – c285b30b)

This week, it looks like the biggest set of changes were the changes directly supporting chrome verified boot, adding options for the GBB flags and supporting VBNV (vboot non-volatile storage) in cmos, flash, and the EC. The verified boot (vboot) submodule included by coreboot was also updated, bringing in another 26 patches. These changes included a variety of work committed to the chromium vboot repo over the past several months. Another submodule was added this week to bring the Chrome EC codebase into the coreboot tree. There were several additional commits to update the build to use the new submodule.

The Intel Skylake and associated boards continued to get updates including more GPIO fixes, disabling the PM timer in ACPI, and unconditionally setting up the BAR for the SPI controller.

Intel continued adding documentation in the Documentation/Intel directory. This is mostly targeting the newly added Galileo mainboard, the newly added Quark X1000 Soc, and version 1.1 of the Intel FSP.

The AMD Family 10h / Family 15h directory and mainboard got some more patches, updating the RDIMM memory training code to work around some failures. The other main feature added was a CMOS option to enable/disable core boost.

There were a number of ACPI ASL changes this week. Several were bugfixes, some were to get rid of unused variables causing warning, and others worked around different warnings generated by new versions of the IASL ACPI compiler. These will help the effort to upgrade the IASL ACPI compiler to the latest version.

The native memory initialization code for the Intel Sandybridge/Ivybridge platforms had a fix for using two DIMMs per channel, and there were a few changes working towards switching the MRC based Sandybridge/Ivybridge implementations over to using native graphics and memory initialization. The goal is that the boards that currently use the Intel MRC should be able to build with either path. More of these changes will be merged in the coming weeks.

The toolchain builder, buildgcc, had several changes to clean up and reorganize the makefiles, and to add a toolchain build for the nds32le architecture in support of the chrome EC builds.

coreboot’s site-local directory was extended to use a Kconfig file and adds a make target which gets run at the end of the rest of the build. Documentation on how to use this should be completed and released next week.

Miscellaneous other fixes include a new lint test ensuring assembly is in AT&T syntax, an update to the QT version for the ‘xconfig’ Kconfig front end, adding PS/2 Aux presence detect to the nuvoton nct5572d SuperIO, and adding a new ARM SoC, Marvell’s Armada 38x.

Thank you to everyone who contributes to the coreboot community.

New issues that we saw this week

– The toolchain build seems to be broken for some people as of commit 8e68aff51 – “buildgcc: enable multilib for gcc”
– There were issues with make gitconfig on a newly cloned repo caused by commit ec0b586 – “3rdparty/chromeec: Add Chrome EC firmware sources”.
– Commit ec0b586 – “3rdparty/chromeec: Add Chrome EC firmware sources” also causes issues pulling down the blobs submodule.

New bugs filed this week

– board-status allows invalid uploads
– Windows doesn’t like ToString() calls in ACPI
– [Haswell/Broadwell] LPC power optimizer RCBA instructions break eDP display with Intel VBIOS
– cbmem utility fails on newer linux kernels “Failed to mmap /dev/mem: Resource temporarily unavailable”
– Provide and use enums for SerialIoI2cVoltage

coreboot statistics for the past week

- Total commits: 107 - New authors: 3 - Total authors: 24 - Reviewers on submitted patches: 11 - Total lines added: 13759 - Total lines removed: -1974 - Total difference: 11785 Added 2 mainboards: asus/kcma-d8 & intel/galileo Added 1 mainboard variant: lenovo/X220i Added 2 SoCs: intel/quark & marvell/armada38x === Top Authors - Number of commits === Leroy P Leahy 15 (14.019%) Patrick Georgi 15 (14.019%) Aaron Durbin 14 (13.084%) Vladimir Serbinenko 10 (9.346%) Timothy Pearson 8 (7.477%) Duncan Laurie 7 (6.542%) Martin Roth 6 (5.607%) Stefan Reinauer 6 (5.607%) Ruilin Hao 5 (4.673%) Total Authors: 25 === Top Authors - Lines added === Timothy Pearson 3956 (28.752%) Ruilin Hao 2964 (21.542%) Leroy P Leahy 2780 (20.205%) Duncan Laurie 1091 (7.929%) Zheng Bao 463 (3.365%) Dhaval Sharma 450 (3.271%) Patrick Georgi 397 (2.885%) Aaron Durbin 397 (2.885%) Lee Leahy 346 (2.515%) Edward O'Callaghan 236 (1.715%) === Top Authors - Lines removed === Zheng Bao 426 (21.581%) Edward O'Callaghan 393 (19.909%) Duncan Laurie 323 (16.363%) Timothy Pearson 223 (11.297%) Vladimir Serbinenko 108 (5.471%) Stefan Reinauer 106 (5.370%) Aaron Durbin 84 (4.255%) Pratik Prajapati 79 (4.002%) Martin Roth 62 (3.141%) Patrick Georgi 49 (2.482%) === Top Reviewers - Number of patches reviewed === Martin Roth 55 (51.402%) Stefan Reinauer 44 (41.121%) Aaron Durbin 8 (7.477%) FEI WANG 6 (5.607%) Patrick Georgi 6 (5.607%) Paul Menzel 5 (4.673%) Timothy Pearson 2 (1.869%) Leroy P Leahy 2 (1.869%) Alexander Couzens 2 (1.869%) Felix Held 2 (1.869%) Total Reviewers: 14 === Submitters - Number of patches submitted === Patrick Georgi 44 (41.121%) Martin Roth 37 (34.579%) Stefan Reinauer 13 (12.150%) Leroy P Leahy 11 (10.280%) Vladimir Serbinenko 2 (1.869%) Total Submitters: 5
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benoit | 10 Feb 22:00 2016
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Can not have IRQ from ethernet device connected to the PCIe #4 in legacy mode

Hi all,

I am facing a legacy IRQ under OS.
I am currently using Coreboot + FSP on baytrail.
My OS is running with IRQ in legacy using PIRQ described in
coreboot/src/mainboard/intel/bayleybay_fsp/irqroute.h .
Under the OS USB, SATA, SMBus are working well using legacy interrupt.
Nevertheless I have an ethernet device connected on the PCIe root #4 and
no IRQs are received.

I tried to change the IRQ in the interrupt line register without success.

I can compare also with a Phoenix BIOS, and with the same OS binary the
ethernet is working.

I check out also the ilb registers + 0x4d0 and 0x4d1 registers (ECL).
Everything is correctly initalized.

Do I need to activate/deactivate something in the PCIe root #4 to
forward legacy interrupt to the 8259 PIC ?

Many thanks in advance
Benoit

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Google Summer of Code 2016

Hi all,

so Google just announced[0] that they're running their Summer of Code
program again.
I'm preparing to be the project admin this year, but to make this real
we'll need contributors that are willing to step up as mentors. I need
to know the number of candidates by Feb 19th, and we're told by end of
February if we participate in the program this year.

If so, students will apply in March and we'll try to find mentors for
them (ideally two per student).

We expect mentors to help students get comfortable in the community
and to support them with their project.
The "active" time for students (and thus also mentors) begins late
April with the "community bonding period" and ends late August with
the end of the "coding" phase of the program. Mentors should be
available for their students in that time frame, although one reason
for planning for two mentors per students is to allow for vacation and
the like.

If you're still interested in mentoring, please tell me so I can
update the number of mentor candidates (which I need to state in the
project's application to GSoC).

If you have ideas that are possible to work through with ~3 months of
effort by a new contributor, please add them to our project ideas wiki
page[1] (that I still need to clean up a bit).

Thanks,
Patrick

[0] https://summerofcode.withgoogle.com/
[1] https://www.coreboot.org/Project_Ideas
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Denis 'GNUtoo' Carikli | 8 Feb 23:19 2016

Removed boards list.

Hi,

When boards are removed, they are also automatically removed from the
supported boards page[1] in the wiki.

The unfortunate downside is that, assuming that coreboot worked fine on
such boards in the past (and may still do), they don't show up in any
list.

A place where to put the list of such boards already exist in the
wiki[2].

Would it be possible to get such page updated (for instance by the
commit author) when the commit has been pushed to master?

A pointer to the commit would also be very appreciated, like I did in
"Graveyard (v4, - v4.2)" status.

The use case I had in mind was to make it easier to check if a given
board was supported, and how (by pointing to its commit).

References:
-----------
[1]https://www.coreboot.org/Supported_Motherboards
[2]https://www.coreboot.org/Graveyard

Denis.
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Christopher Grossarth | 5 Feb 20:00 2016
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Lenovo Thinkpad Yoga 11e (Windows Version)

I would like to build coreboot for the Thinkpad Yoga 11e (Model 20DAS02N00). It is the Windows version of the hardware, with a 2.5" HDD, ethernet port, and removable RAM chips (currently 2x4GB).

I do not know the best procedure for this; should I attempt to edit the GLIMMER board config to more closely match the differences in the hardwares, or start with a RAMBI config and build off that?

I have succesfully built and flashed libreboot for the Macbook 2,1, but libreboot is limited to a few models and the documentation is vague for building for new boards.

Any help will be greatly appreciated.

Best,

-nobodyweird
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ASUS KGPE-D16 Automated Test Failure

The ASUS KGPE-D16 fails verification as of commit 4af905ac95685500e71fb32cf5cec430d1a75447

The following tests failed:
BOOT_FAILURE

Commits since last successful test:
4af905a skylake boards: disable ACPI PM Timer
6c1bf27 intel/skylake: disable ACPI PM Timer to enable XTAL OSC shutdown
50c3ba2 intel/skylake: unconditionally set SPI controller BAR
4121f9e google/chromeos/vboot2: honor boot region device size
f52fb2f google/lars: perform early init for CAR *stage

<10 commits skipped>

87c9fae chromeos/vboot: provide support for x86 memory init verification
43e6d6a 3rdparty/vboot: update to current master
9dca83c intel/skylake: Display ME firmware status before os boot
e2cea4f google/chromeec: Add temporary storage interface
eb31685 google/chromeec: Update EC command header

See attached log for details

This message was automatically generated from Raptor Engineering's ASUS KGPE-D16 test stand
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Raptor Engineering also offers coreboot consulting services!  Please visit
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RFC: coding style: "standard" defines

Hi all,

during the review of some commits that are in the process of being
upstreamed from Chrome OS, people noticed that chipset drivers like to
define their own TRUE/FALSE defines (sometimes prefixed to), and I
have seen a bunch of #define BIT{0-31} ..., too, because that seems to
be the house rules in some firmware communities.

I think we should seek uniformity here: decide on some style,
recommend it, clean up the tree to match, and help people stay
consistent through lint tests. What I don't know however is what that
style should look like.

So, two topics:

1. TRUE/FALSE
Do we want such defines? If so, TRUE/FALSE, or true/false, or
True/False, or ...?

2. BIT16 vs BIT(16) vs (1 << 16) vs 0x10000
I don't think it makes sense to go for a single one of these (0x3ff is
certainly more readable than BIT11 | BIT10 | BIT9 | BIT8 | BIT7 | BIT8
| BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT 0), but I doubt we need both
BIT16 and BIT(16).

Patrick
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ASUS KGPE-D16 Automated Test Failure

The ASUS KGPE-D16 fails verification as of commit e3f47eada383defcc31b41cc4931c3cf3234c37d

The following tests failed:
BOOT_FAILURE

Commits since last successful test:
e3f47ea vendorcode/amd/agesa/f1{4,2,0} Sync Include directory
c389635 vendorcode/amd/agesa/f15?tn: Strip false/redudant AMD ver tag
11a262c util/kconfig:xconf(QT): Update QT version of xconf
420caaf include/device: Move inline functions from pci_def.h to pci.h

See attached log for details

This message was automatically generated from Raptor Engineering's ASUS KGPE-D16 test stand
Want to test on your own equipment?  Check out https://www.raptorengineeringinc.com/content/REACTS/intro.html

Raptor Engineering also offers coreboot consulting services!  Please visit
https://www.raptorengineeringinc.com for more information

Please contact Timothy Pearson at Raptor Engineering <tpearson <at> raptorengineeringinc.com> regarding
any issues stemming from this notification
Attachment (1454470983-3-automaster.log.bz2): application/octet-stream, 49 KiB
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김유석 | 2 Feb 08:40 2016
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bootfail on my Mohon Peak CRB.

Dear sir.

My ENV is see below.

  EVB : Intel rangeley Mohon Peak CRB


This time, I was download the coreboot from git.
  
  poplinux <at> raw work $ > git clone http://review.coreboot.org/coreboot.git ./
  poplinux <at> raw work $ > cd coreboot
  poplinux <at> raw coreboot $ > git submodule update --init --checkout
 
Next, run make menuconfig and set-up to mohon peak CRB and save & exit

  Mainboard
       Mainboard vendor (Intel)  --->
       Mainboard model (Mohon Peak CRB)  --->
   [ ] Configure defaults for the Intel FSP package 
       ROM chip size (2048 KB (2 MB))  ---> 
   (0x00200000) Size of CBFS filesystem in ROM  
   ()  fmap description file in fmd format

Next, I'm try to build core boot.

  poplinux <at> raw coreboot $ > make
    GEN        generated/bootblock.ld
    CP         bootblock/arch/x86/bootblock.ld
    LINK       cbfs/fallback/bootblock.debug
    OBJCOPY    cbfs/fallback/bootblock.elf
    OBJCOPY    bootblock.raw.bin
    Checking out SeaBIOS revision 01a84bea2d28a19d2405c1ecac4bdef17683cc0c
Switched to branch 'master'

  Performing operation on 'COREBOOT' region...
  Name                           Offset     Type         Size
  cbfs master header             0x0        cbfs header  32
  fallback/romstage              0x80       stage        22684
  cpu_microcode_blob.bin         0x5980     microcode    0
  config                         0x5a00     raw          127
  revision                       0x5ac0     raw          570
  cmos_layout.bin                0x5d40     cmos_layout  1316
  fallback/dsdt.aml              0x62c0     raw          7952
  payload_config                 0x8240     raw          1574
  payload_revision               0x88c0     raw          237
  (empty)                        0x8a00     null         29848
  mrc.cache                      0xfec0     mrc_cache    65536
  fallback/ramstage              0x1ff00    stage        46922
  fallback/payload               0x2b6c0    payload      61122
  (empty)                        0x3a5c0    null         1856216
  bootblock                      0x1ff8c0   bootblock    1528

Finally, I'm got a coreboot image.


  poplinux <at> raw build $ > ls build/coreboot.rom
  build/coreboot.rom
  poplinux <at> raw build $ > ./build/cbfstool build/coreboot.rom print
  Performing operation on 'COREBOOT' region...
  Name                           Offset     Type         Size
  cbfs master header             0x0        cbfs header  32
  fallback/romstage              0x80       stage        22684
  cpu_microcode_blob.bin         0x5980     microcode    0
  config                         0x5a00     raw          127
  revision                       0x5ac0     raw          570
  cmos_layout.bin                0x5d40     cmos_layout  1316
  fallback/dsdt.aml              0x62c0     raw          7952
  payload_config                 0x8240     raw          1574
  payload_revision               0x88c0     raw          237
  (empty)                        0x8a00     null         29848
  mrc.cache                      0xfec0     mrc_cache    65536
  fallback/ramstage              0x1ff00    stage        46922
  fallback/payload               0x2b6c0    payload      61122
  (empty)                        0x3a5c0    null         1856216
  bootblock                      0x1ff8c0   bootblock    1528


And I'm write image to my EVB using ALL-100 Gang-writer.
spi flash's write start address is set 0x00000000. write it success.

And I'm attach the flash memory to my EVB.

And power-up the my EVB. But can't see any message on my monitor and serial port both.


Why did not display any message?
And could you support correct configuration file for my EVB?

Thank you.






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ASUS KGPE-D16 Automated Test Failure

The ASUS KGPE-D16 fails verification as of commit 68e3f6dd371ced6963802295e1e176dca5729d2f

The following tests failed:
BOOT_FAILURE

Commits since last successful test:
68e3f6d util/release: extend release script

See attached log for details

This message was automatically generated from Raptor Engineering's ASUS KGPE-D16 test stand
Want to test on your own equipment?  Check out https://www.raptorengineeringinc.com/content/REACTS/intro.html

Raptor Engineering also offers coreboot consulting services!  Please visit
https://www.raptorengineeringinc.com for more information

Please contact Timothy Pearson at Raptor Engineering <tpearson <at> raptorengineeringinc.com> regarding
any issues stemming from this notification
Attachment (1454315580-3-automaster.log.bz2): application/octet-stream, 51 KiB
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Alexander Couzens | 31 Jan 20:15 2016
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berlin coreboot user group meeting 17.02.2016 18:00

hey,

the next coreboot user group meeting is on 17.02. at 1800 as usual at
club discordia / cccb.

everybody is welcome. I'll take some flasher with me, but it's still a
good idea to send me an email so everything is prepared for your
coreboot installation ;)

best,
lynxis
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Gmane