Gailu Singh | 26 Nov 13:45 2014
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Baytrail How to enable PM1_STS_EN.PCIEXP_WAKE_EN register bit

Hi Experts,

I need to enable power management register bit (PM1_STS_EN.PCIEXP_WAKE_EN) of baytrail. I searched for PM1_STS_EN in the source but didn't find anything related to that. Any suggestion how to do it?

Best Regards
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scan-admin | 24 Nov 19:58 2014

New Defects reported by Coverity Scan for coreboot


Hi,

Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan.

5 new defect(s) introduced to coreboot found with Coverity Scan.
9 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan.

New defect(s) Reported-by: Coverity Scan
Showing 5 of 5 defect(s)

** CID 1255946:  Out-of-bounds access  (ARRAY_VS_SINGLETON)
/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c: 155 in ConfigureDefaultUpdData()

** CID 1255945:  Dereference null return value  (NULL_RETURNS)
/coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 98 in LocateModule()

** CID 1255944:  Dereference null return value  (NULL_RETURNS)
/src/northbridge/amd/pi/00730F01/dimmSpd.c: 37 in AmdMemoryReadSPD()

** CID 1255943:  Dereference null return value  (NULL_RETURNS)
/src/cpu/amd/pi/s3_resume.c: 164 in move_stack_high_mem()

** CID 1255942:  Unused value  (UNUSED_VALUE)
/src/drivers/usb/ehci_debug.c: 573 in usbdebug_init_()

________________________________________________________________________________________________________
*** CID 1255946:  Out-of-bounds access  (ARRAY_VS_SINGLETON)
/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c: 155 in ConfigureDefaultUpdData()
149     			case MIPI_DEV_FUNC:	/* Camera / Image Signal Processing */
150     				if (FspInfo->ImageRevision >= FSP_GOLD3_REV_ID) {
151     					UpdData->ISPEnable = dev->enabled;
152     				} else {
153     					/* Gold2 and earlier FSP: ISPEnable is the filed	*/
154     					/* next to PcdGttSize in UPD_DATA_REGION struct		*/
>>>     CID 1255946:  Out-of-bounds access  (ARRAY_VS_SINGLETON)
>>>     Using "&UpdData->PcdGttSize" as an array.  This might corrupt or misinterpret adjacent memory locations.
155     					*(&(UpdData->PcdGttSize)+sizeof(UINT8)) = dev->enabled;
156     					printk (BIOS_DEBUG,
157     						"Baytrail Gold2 or earlier FSP, adjust ISPEnable offset.\n");
158     				}
159     				printk(BIOS_DEBUG, "MIPI/ISP:\t\t%s\n",
160     						UpdData->PcdEnableSdio?"Enabled":"Disabled");

________________________________________________________________________________________________________
*** CID 1255945:  Dereference null return value  (NULL_RETURNS)
/coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 98 in LocateModule()
92     	file = cbfs_get_file(&media, (const char*)CONFIG_CBFS_AGESA_NAME);
93     	if (!file) return NULL;
94     	agesa = cbfs_get_file_content(&media, (const char*)CONFIG_CBFS_AGESA_NAME,
ntohl(file->type), &file_size);
95     	if (!agesa) return NULL;
96     
97     	image =  LibAmdLocateImage(agesa, agesa + ntohl(file->len) - 1, 4096, name);
>>>     CID 1255945:  Dereference null return value  (NULL_RETURNS)
>>>     Dereferencing a null pointer "image".
98     	module = (AMD_MODULE_HEADER*)image->ModuleInfoOffset;
99     
100     	return module;
101     }
102     
103     /**********************************************************************

________________________________________________________________________________________________________
*** CID 1255944:  Dereference null return value  (NULL_RETURNS)
/src/northbridge/amd/pi/00730F01/dimmSpd.c: 37 in AmdMemoryReadSPD()
31     #define DIMENSION(array)(sizeof (array)/ sizeof (array [0]))
32     
33     AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
34     {
35     	int spdAddress;
36     	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
>>>     CID 1255944:  Dereference null return value  (NULL_RETURNS)
>>>     Dereferencing a null pointer "dev".
37     	ROMSTAGE_CONST struct northbridge_amd_pi_00730F01_config *config = dev->chip_info;
38     
39     	if ((dev == 0) || (config == 0))
40     		return AGESA_ERROR;
41     
42     	if (info->SocketId     >= DIMENSION(config->spdAddrLookup      ))

________________________________________________________________________________________________________
*** CID 1255943:  Dereference null return value  (NULL_RETURNS)
/src/cpu/amd/pi/s3_resume.c: 164 in move_stack_high_mem()
158     
159     static void move_stack_high_mem(void)
160     {
161     	void *high_stack;
162     
163     	high_stack = cbmem_find(CBMEM_ID_RESUME_SCRATCH);
>>>     CID 1255943:  Dereference null return value  (NULL_RETURNS)
>>>     Dereferencing a pointer that might be null "high_stack" when calling "memcpy". [Note: The source code
implementation of the function has been overridden by a builtin model.]
164     	memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR,
165     		(CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE));
166     
167     	__asm__
168     	    volatile ("add	%0, %%esp; add %0, %%ebp; invd"::"g"
169     		      (high_stack - BSP_STACK_BASE_ADDR)

________________________________________________________________________________________________________
*** CID 1255942:  Unused value  (UNUSED_VALUE)
/src/drivers/usb/ehci_debug.c: 573 in usbdebug_init_()
567     
568     	dbgp_mdelay(100);
569     
570     	ret = dbgp_probe_gadget(info->ehci_debug, &info->ep_pipe[0]);
571     	if (ret < 0) {
572     		dprintk(BIOS_INFO, "Could not probe gadget on debug port.\n");
>>>     CID 1255942:  Unused value  (UNUSED_VALUE)
>>>     Value "-6" is assigned to "ret" here, but that stored value is not used before it is overwritten.
573     		ret = -6;
574     		goto err;
575     	}
576     
577     	return 0;
578     err:

________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, http://scan.coverity.com/projects/1016?tab=overview

To unsubscribe from the email notification for new defects, http://scan5.coverity.com/cgi-bin/unsubscribe.py

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Gailu Singh | 24 Nov 13:59 2014
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How to get coreboot debug prints during suspend resume

Hi Experts,

Is it possible to get coreboot debug prints during suspend/resume?

Best Regards

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Gailu Singh | 24 Nov 12:34 2014
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WOL/PCI PME wakeup from S3 Baytrail SoC (Bayleybay CRB)

Hi Experts,

I have PCIe card that supports wake on lan and it works fine with BIOS. On sending magic packet System wakes up from S3.

However If I use same Linux image with coreboot wake from PCI device does not wake the system. System wakes up from S3 using power button only.

I suspected the problem with dsdt and took dsdt binary from bios setup, disassembled it and replaced dsdt.asl in coreboot with the one from bios to match dsdt configuration. Now my dsdt and linux image are same but still system does not wake from PCI PME (WOL) in coreboot but works fine with bios.

In both cases wakeup is enabled in /sys/bus/pci/devices/0000\:01\:00.0/power/wakeup

Can you please advise what else could be the problem?

PME signal is connected to GPIOS5 on the SoC.

Best Regards

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Antoine PLANTY | 22 Nov 18:15 2014

Coreboot on a thinkpad x300

Hi,

Since I saw on the product list that the thinkpad x300 wasn't  supported and you advised to send an e-mail here it :

-Thinkpad X300 :
CPU : Intel C2D SL7100 (merom)
North Bridge: Crestline_SFF
South Bridge: ICH8M SFF

I've included the output of lscpi, flashrom, superiotool aswell as the X300 schematics in the archive.

Best regards,
Antoine
Attachment (x300.tar.gz): application/gzip, 1196 KiB
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Vincent Pelletier | 23 Nov 17:35 2014
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Donating hardware

Hi.

(please keep me CC'ed, I'm not subscribed)

I am getting rid of two old motherboards and would like to donate them
to coreboot.

Both cards are ASUS:
- M2N32-SLI deluxe
  http://www.asus.com/Motherboards/M2N32SLI_DeluxeWireless_Edition/
- M5A88-V EVO
  http://www.asus.com/Motherboards/M5A88V_EVO/

Any dev interested ?
Questions welcome.

Regards,
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Infrastructure work

Hello, all. I know I've signed up to fix board-status and cmos but I
don't want to go through painful reviews, so I'm not going to do this,
even though maintaining current CMOS stuff is a pain in itself.

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The Gluglug | 21 Nov 06:03 2014
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cbfstool build issue in gcc 4.6.3


Hi,

cbfs-mkstage.c: In function ‘is_phdr_ignored’:
cbfs-mkstage.c:45:84: error: cast to pointer from integer of different
size [-Werror=int-to-pointer-cast]

The fix was made in http://review.coreboot.org/#/c/7545/ but some
people were unhappy about the use of extra type casting.

One possible solution is to simply upgrade GCC, which I will, but I
would also like to get cbfstool to build again for this version of
GCC. The patch in the gerrit link works, but is not accepted for
upstream.

Does anyone know a better way of doing it?

Regards,
Francis Rowe.
Gailu Singh | 19 Nov 20:36 2014
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Memory corruption on Resume from S3 Baytrail

Hi Experts,

I am using Baytrail SoC board (Bayleybay CRB) and testing suspend/resume from Linux (kernel 3.10). I can suspend with pm-suspend and resume with power button; however after resuming I get following logs in Linux
Corrupted low memory at c0001004 (1004 phys) = 0008eaea
Corrupted low memory at c0001008 (1008 phys) = b0606600
...
Corrupted low memory at c00018fc (18fc phys) = 000008ea

This seems to be caused by coreboot as I do not see these logs if I use BIOS instead of coreboot.
Is it true that during resume coreboot uses RAM portion already mapped by Linux and thus corrupting it. How to I avoid the RAM conflict?


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The Gluglug | 19 Nov 10:42 2014
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ME4/5


What systems in coreboot use intel ME 4 and which ones use ME 5?
(I know X200 uses ME4 already.)

ROSA MARIA LOPEZ ROBLES | 17 Nov 12:08 2014

Re: coreboot Digest, Vol 117, Issue 28


________________________________________
De: coreboot [coreboot-bounces <at> coreboot.org] en nom de coreboot-request <at> coreboot.org [coreboot-request <at> coreboot.org]
Enviat el: dilluns, 17 / novembre / 2014 12:00
Per a: coreboot <at> coreboot.org
Tema: coreboot Digest, Vol 117, Issue 28

Send coreboot mailing list submissions to
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To subscribe or unsubscribe via the World Wide Web, visit
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When replying, please edit your Subject line so it is more specific
than "Re: Contents of coreboot digest..."


Today's Topics:

   1. vortex86ex (The Gluglug)


----------------------------------------------------------------------

Message: 1
Date: Sun, 16 Nov 2014 23:38:41 +0000
From: The Gluglug <info <at> gluglug.org.uk>
To: coreboot <at> coreboot.org
Subject: [coreboot] vortex86ex
Message-ID: <54693581.4060205 <at> gluglug.org.uk>
Content-Type: text/plain; charset=utf-8

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Does anyone have a vortex86ex board with coreboot?
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)

iQEcBAEBAgAGBQJUaTV4AAoJEP9Ft0z50c+UgzwH/3/Jx914Y6e0pFTaSE256oxs
eKHigGpiMVpjseYCtMTK8ZulAIydvumY+jclwAzydY0P8IlcTW9teKF5JNxvnf0D
EyaOel/pbxhIexOzs/ei8ALSil3+fPIhC2rqVs00l0MrO5DvBwa/fxF4qjWbnuuW
KS+k68z2sLbD7UI+LDlJaj/ecZ1lzS/YaN1a7r2Wem1ZPda3ATjV0xMjFChvBkbo
kFauxuLeVlBxqJfhkRZijpFrD0cpljCL6LWn/738HZbzXGVlqqKsCQcMBtcUsiEq
o8yEI97BesJfXvFGXPsw05swoWxrVF/yJDR8ALM9Dy7Uabqumg/vhRK95EHbtF0=
=g3MX
-----END PGP SIGNATURE-----



------------------------------

Subject: Digest Footer

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End of coreboot Digest, Vol 117, Issue 28
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