coreboot conference | 5 Sep 01:55 2015
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coreboot conference 2015 invitation

Dear vendors, developers and interested parties,

on behalf of the Federal Office for Information Security (BSI) Germany I would 
like to invite you to the coreboot conference and developer meeting on 
October 9-11 2015 in Bonn, Germany.

This conference and developer meeting is geared towards manufacturers of 
hardware (processors, chipsets, mainboards and servers/ laptops/ tablets/ 
desktops/ appliances) as well as developers of firmware with an interest in 
coreboot and the possibilities it offers.

The Federal Office for Information Security (BSI) in Germany will host the 
conference in Bonn, Germany. As the national cyber security authority, the 
goal of the BSI is to promote IT security in Germany. For this reason, the 
BSI has funded coreboot development in the past for security reasons.

The date of the coreboot conference is Friday October 9 to Sunday October 11, 
2015. This is scheduled directly after Embedded Linux Conference Europe to 
make travel arrangements easier for people attending both events.

If your main interest is forging business relationships and/or strategic 
coordination and you want to skip the technical workshops, Friday (and 
possibly Saturday) will be the outreach day of talks, presentations and 
discussions.
If your main interest is doing development, you can use the separate developer 
room next to the during all three days of the conference.

Call for presentations:
We are looking for interesting talks/presentations about coreboot related 
topics for the first (and possibly second) day of the conference. Please note 
(Continue reading)

Iru Cai | 4 Sep 14:12 2015
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build fails when CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT is set

Hi,

I was trying to build coreboot with the latest git code and build failed when CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT is set. Some of the error message is:

$ make
    CREATE     build/mainboard/lenovo/x220/cbfs-file.c7KD3B.out (from src/mainboard/lenovo/x220/cmos.default)
Created CBFS (capacity = 1046552 bytes)
E: Input file size (68464) greater than page size (65536).
    GEN        generated/romstage.ld
    LINK       cbfs/fallback/romstage.debug
    OBJCOPY    cbfs/fallback/romstage.elf
    CBFS       coreboot.pre
    CC         northbridge/intel/sandybridge/gma_sandybridge_lvds.ramstage.o
src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c: In function 'i915lightup_sandy':
src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c:195:21: error: 'struct edid' has no member named 'hborder'
  right_border = edid.hborder;
                     ^

After I searched the git log, I found this commit cause the error:
commit 7dbf9c6747ccdfa8b993d3843a22722742957611
Author: David Hendricks <dhendrix <at> chromium.org>
Date:   Thu Jul 30 18:49:48 2015 -0700

    edid: Use edid_mode struct to reduce redundancy
   
    This replaces various timing mode parameters parameters with
    an edid_mode struct within the edid struct.
   
I hope someone will fix the error soon.

Iru Cai

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Paul Menzel | 3 Sep 22:09 2015
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coreboot meeting 2015: SerialICE workshop?

Dear coreboot folks,

the coreboot meeting 2015 is taking place soon from October 9th to 11th
[1].

Reading so much about SerialICE [2] and never having really used it,
would there be one of the experts be willing to do some kind of
workshop. That’d be really awesome!

I am looking forward to seeing you all.

Thanks,

Paul

[1] http://blogs.coreboot.org/blog/2015/08/04/coreboot-conference-in-europe-october-2015
[2] http://www.serialice.com
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Torsten Duwe | 3 Sep 12:53 2015
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Linux 4.0.x iomem regression

JFYI, I got stuck with kernel 3.19 this spring, and Linux-4.0 didn't work
properly on my coreboot machine. Only now I've had time to look into this.

To make it short: the fault is in the Linux PCI/ACPI code; see mainline
commit 2c62e8492, which fixes this in 4.1-rc3. You may want to skim through
https://lkml.org/lkml/2015/4/3/608 to get an idea of this mess.

" I did it because Windows apparently does that ..."

I'm not sure if and why proprietary BIOSes are unaffected.
Just to let you all know in case you're bisecting across 4.0 linux kernels.

	Torsten

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Keith Emery | 30 Aug 22:43 2015
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Openbiosprog-spi

G,day all

I just made an order on PCB cart for the OpenBiosprog_spi.
As a result of mild brain damage on my part; I went ahead and ordered 200 boards.

So in light of the above I am happy to mail out as many boards as anyone might want for the low low price of $1.20 AUD plus postage.  Spread the word!

http://keithtronics.tictail.com/
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John Lewis | 30 Aug 20:43 2015
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Acer Chromebook 15 debug

Hi Guys,

Coolstar Organisation wants to do his Windows thang with one of the 
Broadwell Chromebooks, so I'm trying to build a working ROM with 
chromium.googlesource.com/chromiumos/third_party/coreboot/+/firmware-yuna-6301.59.B 
to give him a hand. Luckily USB debug works with this, so here is what 
I'm getting. What could I do next?

Incidentally, if I flash back my backup, it goes into recovery mode now 
every time I boot (flags are 0x489), I've tried pulling the battery to 
no avail. If anyone has a trick to get around that, I'd appreciate it, 
as the Acer is my main machine.

-⁠John.

coreboot-⁠5cbe3a8-⁠dirty romstage Sun Aug 23 12:18:55 BST 2015 
starting...

PM1_STS:   8910

PM1_EN:    0000

PM1_CNT:   00000000

TCO_STS:   0000 0000

GPE0_STS:  1ef82df0 187d4fdf 0005f240 00000000

GPE0_EN:   00000000 00000000 00000000 00000000

GEN_PMCON: 0200 2024 520b

Previous Sleep State: S5

CPU: Intel(R) Core(TM) i3-⁠5005U CPU  <at>  2.00GHz

CPU: ID 306d4, Broadwell E0 or F0, ucode: 0000001d

CPU: AES supported, TXT NOT supported, VT supported

MCH: device id 1604 (rev 09) is Broadwell F0

PCH: device id 9cc5 (rev 03) is Broadwell U Base

IGD: device id 1616 (rev 09) is Broadwell U GT2

CPU: frequency set to 2000 MHz

SPD: index 1 (GPIO47=0 GPIO9=0 GPIO13=1)

SPD: module type is DDR3

SPD: module part is HMT425S6AFR6A-⁠PB

SPD: banks 8, ranks 1, rows 15, columns 10, density 4096 Mb

SPD: device width 16 bits, bus width 64 bits

SPD: module size is 2048 MB (per channel)

Boot Count incremented to 8

ME: FW Partition Table      : OK

ME: Bringup Loader Failure  : NO

ME: Firmware Init Complete  : NO

ME: Manufacturing Mode      : NO

ME: Boot Options Present    : NO

ME: Update In Progress      : NO

ME: Current Working State   : Normal

ME: Current Operation State : Bring up

ME: Current Operation Mode  : Normal

ME: Error Code              : No Error

ME: Progress Phase          : BUP Phase

ME: Power Management Event  : Pseudo-⁠global reset

ME: Progress Phase State    : Waiting for DID BIOS message

ME: HSIO Version            : 8705 (CRC 0xfbc2)

No FMAP found at ffe10000.

FMAP: area RW_MRC_CACHE not found

No MRC cache found.

Starting Memory Reference Code

Initializing Policy

Installing common PPI

MRC: Starting...

Initializing Memory

MRC: Done.

MRC Version 2.6.0 Build 0

memcfg DDR3 clock 1600 MHz

memcfg channel assignment: A: 0, B  1, C  2

memcfg channel[0] config (00780008):

    enhanced interleave mode on

    rank interleave on

    DIMMA 2048 MB width x16 single rank, selected

    DIMMB 0 MB width x16 single rank

memcfg channel[1] config (00780008):

    enhanced interleave mode on

    rank interleave on

    DIMMA 2048 MB width x16 single rank, selected

    DIMMB 0 MB width x16 single rank

CBMEM: root  <at>  7cfff000 254 entries.

MRC data at ff7d0d9c 6246 bytes

Relocate MRC DATA from ff7d0d9c to 7cfeb000 (6246 bytes)

create cbmem for dimm information

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蝈蝈 | 30 Aug 08:11 2015

sincerely consult about Gerrit plugin

Dear Mr/Ms,

    I am very excited to read the slide "Gerrit: how to cook a plugin in only 10 mins". Now I have a problem about how to build a gerrit plugin to display all the projects' name. Could you help me?

    Firstly, I built the gerrit platform and achieved the servertime gerrit plugin (the example in the slide). In the attachment, you can find the achievement of this step (servertime.png). 

    Secondly, I followed the flow of the servertime gerrit plugin, I build a new java file (ProjectList.java), and I want to get the list of all the projects' name in the Gerrit through this projectlist gerrit plugin. In the attachment,I just write the head of class ProjectList (projectlist.png), I don't know whether it is right. Could you tell me how to write the class ProjectList to get all the projects' name?
 
I am looking forward to hearing from you.
 

Best Wishes,
Zhaoguo Liu
National Key Laboratory of Cognitive Neuroscience and Learning
No. 19, XinJieKouWai St., HaiDian District, 
Beijing 100875, P. R. China


夏日畅销榜大牌美妆只要1元



夏日畅销榜大牌美妆只要1元



夏日畅销榜大牌美妆只要1元

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蝈蝈 | 30 Aug 07:49 2015

sincerely consult about Gerrit plugin

Dear Mr/Ms,

    I am very excited to read the slide "Gerrit: how to cook a plugin in only 10 mins". Now I have a problem about how to build a gerrit plugin to display all the projects' name. Could you help me?

    Firstly, I built the gerrit platform and achieved the servertime gerrit plugin (the example in the slide). In the attachment, you can find the achievement of this step (servertime.png). 

    Secondly, I followed the flow of the servertime gerrit plugin, I build a new java file (ProjectList.java), and I want to get the list of all the projects' name in the Gerrit through this projectlist gerrit plugin. In the attachment,I just write the head of class ProjectList (projectlist.png), I don't know whether it is right. Could you tell me how to write the class ProjectList to get all the projects' name?
 
I am looking forward to hearing from you.
 

Best Wishes,
Zhaoguo Liu
National Key Laboratory of Cognitive Neuroscience and Learning
No. 19, XinJieKouWai St., HaiDian District, 
Beijing 100875, P. R. China


夏日畅销榜大牌美妆只要1元



夏日畅销榜大牌美妆只要1元



夏日畅销榜大牌美妆只要1元

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John Lewis | 29 Aug 22:20 2015
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Acer Chromebook 15 debug

Hi Guys,

Coolstar Organisation wants to do his Windows thang with one of the 
Broadwell Chromebooks, so I'm trying to build a working ROM with

https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/firmware-yuna-6301.59.B 
to give him a hand. Luckily USB debug works with this, so here is what 
I'm getting. What could I do next?

-John.

coreboot-5cbe3a8-dirty romstage Sun Aug 23 12:18:55 BST 2015 starting...

PM1_STS:   8910

PM1_EN:    0000

PM1_CNT:   00000000

TCO_STS:   0000 0000

GPE0_STS:  1ef82df0 187d4fdf 0005f240 00000000

GPE0_EN:   00000000 00000000 00000000 00000000

GEN_PMCON: 0200 2024 520b

Previous Sleep State: S5

CPU: Intel(R) Core(TM) i3-5005U CPU  <at>  2.00GHz

CPU: ID 306d4, Broadwell E0 or F0, ucode: 0000001d

CPU: AES supported, TXT NOT supported, VT supported

MCH: device id 1604 (rev 09) is Broadwell F0

PCH: device id 9cc5 (rev 03) is Broadwell U Base

IGD: device id 1616 (rev 09) is Broadwell U GT2

CPU: frequency set to 2000 MHz

SPD: index 1 (GPIO47=0 GPIO9=0 GPIO13=1)

SPD: module type is DDR3

SPD: module part is HMT425S6AFR6A-PB

SPD: banks 8, ranks 1, rows 15, columns 10, density 4096 Mb

SPD: device width 16 bits, bus width 64 bits

SPD: module size is 2048 MB (per channel)

Boot Count incremented to 8

ME: FW Partition Table      : OK

ME: Bringup Loader Failure  : NO

ME: Firmware Init Complete  : NO

ME: Manufacturing Mode      : NO

ME: Boot Options Present    : NO

ME: Update In Progress      : NO

ME: Current Working State   : Normal

ME: Current Operation State : Bring up

ME: Current Operation Mode  : Normal

ME: Error Code              : No Error

ME: Progress Phase          : BUP Phase

ME: Power Management Event  : Pseudo-global reset

ME: Progress Phase State    : Waiting for DID BIOS message

ME: HSIO Version            : 8705 (CRC 0xfbc2)

No FMAP found at ffe10000.

FMAP: area RW_MRC_CACHE not found

No MRC cache found.

Starting Memory Reference Code

Initializing Policy

Installing common PPI

MRC: Starting...

Initializing Memory

MRC: Done.

MRC Version 2.6.0 Build 0

memcfg DDR3 clock 1600 MHz

memcfg channel assignment: A: 0, B  1, C  2

memcfg channel[0] config (00780008):

    enhanced interleave mode on

    rank interleave on

    DIMMA 2048 MB width x16 single rank, selected

    DIMMB 0 MB width x16 single rank

memcfg channel[1] config (00780008):

    enhanced interleave mode on

    rank interleave on

    DIMMA 2048 MB width x16 single rank, selected

    DIMMB 0 MB width x16 single rank

CBMEM: root  <at>  7cfff000 254 entries.

MRC data at ff7d0d9c 6246 bytes

Relocate MRC DATA from ff7d0d9c to 7cfeb000 (6246 bytes)

create cbmem for dimm information

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WordPress | 29 Aug 12:25 2015

New on blogs.coreboot.org: coreboot changelog – Weeks of 2015-08-10 and 2015-08-17

A new post titled "coreboot changelog – Weeks of 2015-08-10 and 2015-08-17" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2015/08/29/coreboot-changelog-weeks-of-2015-08-10-and-2015-08-17/

this report covers commits 1cbef1c to 410f9ad

The vast majority of changes in these two weeks were upstreamed from Chrome OS and cover work on the Intel Skylake chipset and two mainboards based on it.

QEmu and Getac P470 saw a couple of improvements.
On AMD, there were some bugfixes to Fam10h concerning VGA memory and SMM initialization. The latter was in response to the Memory Sinkhole vulnerability, although it is as yet unclear if it even affects AMD.
Finally, an important memory structure used on pre-AGESA AMD code is now also usable outside Cache-as-RAM.
There was more progress on fixing 64bit issues across the codebase.

Our reference compiler was updated to gcc 5.2. This became necessary to support an update to the RISC-V specification.

Our other tools also saw a couple of improvements: ifdtool now works for descriptors on Skylake and newer platforms. cbfstool saw some refactorings that allow us to extend the format. cbmem now emits the accumulated boot time.

In our configuration system, the Kconfig definitions were cleaned up, so that boards don’t define symbols that their code never uses, that Chrome OS capable boards define “MAINBOARD_HAS_CHROMEOS” (which defines the capability) instead of “CHROMEOS” (which defines that this mode should be
used) and that dependencies between Kconfig options become more consistent.
There is a pending commit on gerrit to enforce clean dependencies by making errors out of kconfig’s warnings, that the latter changes prepare for.

On the build system side, it is now possible to build SeaBIOS as part of our build system even with an enabled ccache. The payload config and revision can also be stored in CBFS for better reproducibility. Finally, it’s possible to override the location from where the vboot source code for Chrome OS-style verified boot is taken from.

In libpayload, the non-accelerated memmove implementation now also works with size == 0 (instead of trying to move 4GB), and there were a couple of bug fixes to the DWC2 (some ARM) and XHCI (USB3) controller drivers, including support for the newer XHCI 1.1 specification.

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Gregg Levine | 29 Aug 03:51 2015
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coreboot as a system startup device

Hello!
Is Google using coreboot as a method to start and manage its systems?
Especially since the open source gang at Facebook of all places is
realizing that the bottleneck towards getting their systems to run
capably happens to be its low level firmware.

Of course the chap at the NYLUG meeting for Wednesday 8/26 all but
admitted that they were using Intel based servers back there, so I did
not mention what goes on here.

The presentation should be up on the NYLUG Youtube channel in a matter of weeks.
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"This signature fought the Time Wars, time and again."

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Gmane