Mohan | 18 Sep 07:35 2014
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Re: 回复: Could not find a bounce buffer tested in minnowmax

On 09/18/14 14:01, DM365 wrote:
Thanks for your help.
Where can I change the IFD (Intel Flash Desciptor) ?



I took 4M from original BIOS image and attached the 4M coreboot.rom to
the end of the file.

eg.
$ dd if=original_minnowmax_BIOS.bin of=BIOS.bin bs=1M count=4
$ dd if=coreboot.rom >> BIOS.bin

 
- Mohan
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DM365 | 17 Sep 11:29 2014

Could not find a bounce buffer tested in minnowmax

I'm trying to investigate Coreboot and intel FSP in minnowmax board ,followed by "http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=e6df041b8bf8e37debc0d6a871080b64eea7a372". But ,the uart log show : Payload being loaded below 1MiB without region being marked as RAM usable. Could not find a bounce buffer... Could not load payload The whole debug log is:
POST: 0x4a romstage_main_continue status: 0 hob_list_ptr: 7bb20000 FSP Status: 0x0 Baytrail Chip Variant: Bay Trail-I (ISG/embedded) MRC v0.90 1 channels of DDR3 <at> 1066MHz POST: 0x4b POST: 0x4c POST: 0x4d CBMEM: root <at> 7baff000 254 entries. POST: 0x4e POST: 0x4f Trying CBFS ramstage loader. CBFS: loading stage fallback/ramstage <at> 0x100000 (270384 bytes), entry <at> 0x100000 POST: 0x80 POST: 0x39 coreboot-4.0-6880-ga4a44a7 Tue Sep 16 23:46:12 PDT 2014 booting... POST: 0x40 clocks_per_usec: 1333 CBMEM: recovering 3/254 entries from root <at> 7baff000 Moving GDT to 7bafc000...ok POST: 0x70 BS: BS_PRE_DEVICE times (us): entry 8070 run 1170 exit 0 POST: 0x71 CPUID: 00030673 Cores: 2 Revision ID: 0c Stepping: B3 msr(17) = 0000000c90040a38 msr(ce) = 0000040000000a00 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 12482 exit 0 POST: 0x72 Enumerating buses... enable_dev(Intel BayTrail SoC, 7) CPU_CLUSTER: 0 enabled enable_dev(Intel BayTrail SoC, 6) DOMAIN: 0000 enabled PCI: pci_scan_bus for bus 00 POST: 0x24 enable_dev(Intel BayTrail SoC, 2) PCI: 00:00.0 [8086/0000] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:02.0 [8086/0031] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:03.0: Disabling device: 03.0 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:10.0: Disabling device: 10.0 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:11.0: Disabling device: 11.0 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:12.0 [8086/0f16] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:13.0 [8086/0f23] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:14.0 [8086/0f35] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:15.0 [8086/0f28] enabled PCI: 00:16.0 [8086/0f37] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:17.0: Disabling device: 17.0 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.0 [8086/0f40] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.1: Disabling device: 18.1 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.2: Disabling device: 18.2 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.3: Disabling device: 18.3 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.4: Disabling device: 18.4 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.5: Disabling device: 18.5 Power management CAP offset 0x80. enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.6 [8086/0f46] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:18.7 [8086/0f47] enabled enable_dev(Intel BayTrail SoC, 2) PCI: Static device PCI: 00:1a.0 not found, disabling it. enable_dev(Intel BayTrail SoC, 2) PCI: 00:1b.0: Disabling device: 1b.0 PCI: 00:1b.0 [8086/0f04] disabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1c.0: Disabling device: 1c.0 Power management CAP offset 0xa0. PCI: 00:1c.0 subordinate bus PCI Express PCI: 00:1c.0 [8086/0f48] disabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1c.1: Disabling device: 1c.1 Power management CAP offset 0xa0. enable_dev(Intel BayTrail SoC, 2) PCI: 00:1c.2 subordinate bus PCI Express PCI: 00:1c.2 [8086/0f4c] enabled enable_dev(Intel BayTrail SoC, 2) PCI: Static device PCI: 00:1c.3 not found, disabling it. enable_dev(Intel BayTrail SoC, 2) PCI: 00:1d.0: Disabling device: 1d.0 Power management CAP offset 0x70. enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.0 [8086/0f06] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.1 [8086/0f08] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.2 [8086/0f09] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.3 [8086/0f0a] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.4 [8086/0f0c] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1e.5 [8086/0f0e] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1f.0 [8086/0f1c] enabled enable_dev(Intel BayTrail SoC, 2) PCI: 00:1f.3 [8086/0f12] enabled POST: 0x25 PCI: pci_scan_bus for bus 01 POST: 0x24 PCI: 01:00.0 [10ec/8168] enabled POST: 0x25 PCI: pci_scan_bus returning with max=001 POST: 0x55 PCI: pci_scan_bus returning with max=001 POST: 0x55 done BS: BS_DEV_ENUMERATE times (us): entry 0 run 329939 exit 0 POST: 0x73 found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... APIC: 00 missing read_resources Done reading resources. Setting resources... PCI: 00:02.0 10 <- [0x00f0000000 - 0x00f03fffff] size 0x00400000 gran 0x16 mem PCI: 00:02.0 18 <- [0x00e0000000 - 0x00efffffff] size 0x10000000 gran 0x1c prefmem PCI: 00:02.0 20 <- [0x0000002040 - 0x0000002047] size 0x00000008 gran 0x03 io PCI: 00:12.0 10 <- [0x00f0a18000 - 0x00f0a18fff] size 0x00001000 gran 0x0c mem PCI: 00:12.0 14 <- [0x00f0a19000 - 0x00f0a19fff] size 0x00001000 gran 0x0c mem PCI: 00:13.0 10 <- [0x0000002048 - 0x000000204f] size 0x00000008 gran 0x03 io PCI: 00:13.0 14 <- [0x0000002058 - 0x000000205b] size 0x00000004 gran 0x02 io PCI: 00:13.0 18 <- [0x0000002050 - 0x0000002057] size 0x00000008 gran 0x03 io PCI: 00:13.0 1c <- [0x000000205c - 0x000000205f] size 0x00000004 gran 0x02 io PCI: 00:13.0 20 <- [0x0000002000 - 0x000000201f] size 0x00000020 gran 0x05 io PCI: 00:13.0 24 <- [0x00f0a2c000 - 0x00f0a2c7ff] size 0x00000800 gran 0x0b mem PCI: 00:14.0 10 <- [0x00f0a00000 - 0x00f0a0ffff] size 0x00010000 gran 0x10 mem64 PCI: 00:15.0 10 <- [0x00f0400000 - 0x00f05fffff] size 0x00200000 gran 0x15 mem PCI: 00:15.0 14 <- [0x00f0a1a000 - 0x00f0a1afff] size 0x00001000 gran 0x0c mem PCI: 00:16.0 10 <- [0x00f0600000 - 0x00f07fffff] size 0x00200000 gran 0x15 mem PCI: 00:16.0 14 <- [0x00f0a1b000 - 0x00f0a1bfff] size 0x00001000 gran 0x0c mem PCI: 00:18.0 10 <- [0x00f0a10000 - 0x00f0a13fff] size 0x00004000 gran 0x0e mem PCI: 00:18.0 14 <- [0x00f0a1c000 - 0x00f0a1cfff] size 0x00001000 gran 0x0c mem PCI: 00:18.6 10 <- [0x00f0a1d000 - 0x00f0a1dfff] size 0x00001000 gran 0x0c mem PCI: 00:18.6 14 <- [0x00f0a1e000 - 0x00f0a1efff] size 0x00001000 gran 0x0c mem PCI: 00:18.7 10 <- [0x00f0a1f000 - 0x00f0a1ffff] size 0x00001000 gran 0x0c mem PCI: 00:18.7 14 <- [0x00f0a20000 - 0x00f0a20fff] size 0x00001000 gran 0x0c mem PCI: 00:1c.2 1c <- [0x0000001000 - 0x0000001fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:1c.2 24 <- [0x00f0800000 - 0x00f08fffff] size 0x00100000 gran 0x14 bus 01 prefmem PCI: 00:1c.2 20 <- [0x00f0900000 - 0x00f09fffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 01:00.0 10 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 01:00.0 18 <- [0x00f0900000 - 0x00f0900fff] size 0x00001000 gran 0x0c mem64 PCI: 01:00.0 20 <- [0x00f0800000 - 0x00f0803fff] size 0x00004000 gran 0x0e prefmem64 PCI: 00:1e.0 10 <- [0x00f0a14000 - 0x00f0a17fff] size 0x00004000 gran 0x0e mem PCI: 00:1e.0 14 <- [0x00f0a21000 - 0x00f0a21fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.1 10 <- [0x00f0a22000 - 0x00f0a22fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.1 14 <- [0x00f0a23000 - 0x00f0a23fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.2 10 <- [0x00f0a24000 - 0x00f0a24fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.2 14 <- [0x00f0a25000 - 0x00f0a25fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.3 10 <- [0x00f0a26000 - 0x00f0a26fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.3 14 <- [0x00f0a27000 - 0x00f0a27fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.4 10 <- [0x00f0a28000 - 0x00f0a28fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.4 14 <- [0x00f0a29000 - 0x00f0a29fff] size 0x00001000 gran 0x0c mem PCI: 00:1e.5 10 <- [0x00f0a2a000 - 0x00f0a2afff] size 0x00001000 gran 0x0c mem PCI: 00:1e.5 14 <- [0x00f0a2b000 - 0x00f0a2bfff] size 0x00001000 gran 0x0c mem PCI: 00:1f.3 10 <- [0x00f0a2c800 - 0x00f0a2c81f] size 0x00000020 gran 0x05 mem PCI: 00:1f.3 20 <- [0x0000002020 - 0x000000203f] size 0x00000020 gran 0x05 io Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 365032 exit 0 POST: 0x74 Enabling resources... PCI: 00:00.0 subsystem <- 0000/0000 PCI: 00:00.0 cmd <- 07 PCI: 00:02.0 subsystem <- 0000/0000 PCI: 00:02.0 cmd <- 07 PCI: 00:12.0 subsystem <- 0000/0000 PCI: 00:12.0 cmd <- 106 PCI: 00:13.0 subsystem <- 0000/0000 PCI: 00:13.0 cmd <- 107 PCI: 00:14.0 subsystem <- 0000/0000 PCI: 00:14.0 cmd <- 102 PCI: 00:15.0 subsystem <- 0000/0000 PCI: 00:15.0 cmd <- 102 PCI: 00:16.0 cmd <- 02 PCI: 00:18.0 subsystem <- 0000/0000 PCI: 00:18.0 cmd <- 106 PCI: 00:18.6 subsystem <- 0000/0000 PCI: 00:18.6 cmd <- 102 PCI: 00:18.7 subsystem <- 0000/0000 PCI: 00:18.7 cmd <- 102 PCI: 00:1c.2 bridge ctrl <- 0003 PCI: 00:1c.2 cmd <- 107 PCI: 00:1e.0 subsystem <- 0000/0000 PCI: 00:1e.0 cmd <- 106 PCI: 00:1e.1 subsystem <- 0000/0000 PCI: 00:1e.1 cmd <- 102 PCI: 00:1e.2 subsystem <- 0000/0000 PCI: 00:1e.2 cmd <- 102 PCI: 00:1e.3 subsystem <- 0000/0000 PCI: 00:1e.3 cmd <- 102 PCI: 00:1e.4 subsystem <- 0000/0000 PCI: 00:1e.4 cmd <- 102 PCI: 00:1e.5 subsystem <- 0000/0000 PCI: 00:1e.5 cmd <- 102 PCI: 00:1f.3 subsystem <- 0000/0000 PCI: 00:1f.3 cmd <- 103 PCI: 01:00.0 cmd <- 03 done. BS: BS_DEV_ENABLE times (us): entry 0 run 110777 exit 0 POST: 0x75 Initializing devices... Root Device init Root Device init 1750 usecs POST: 0x75 CPU_CLUSTER: 0 init MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Setting up local apic... apic_id: 0x00 done. POST: 0x9b CPU: Intel(R) Atom(TM) CPU E3825 <at> 1.33GHz. Loading module at 00030000 with entry 00030000. filesize: 0x130 memsize: 0x130 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...done. AP: slot 1 apic_id 4. Waiting for 2nd SIPI to complete...done. Initializing CPU #0 CPU: vendor Intel device 30673 CPU: family 06, model 37, stepping 03 Init BayTrail core. CPU #0 initialized Initializing CPU #1 CPU_CLUSTER: 0 init 72229 usecs POST: 0x75 CPU: vendor Intel device 30673 CPU: family 06, model 37, stepping 03 POST: 0x75 POST: 0x75 Init BayTrail core. POST: 0x75 Turbo is unavailable PCI: 00:00.0 init CPU #1 initialized PCI: 00:00.0 init 3986 usecs POST: 0x75 PCI: 00:02.0 init PCI: 00:02.0 init 1847 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:12.0 init PCI: 00:12.0 init 1848 usecs POST: 0x75 PCI: 00:13.0 init PCI: 00:13.0 init 1848 usecs POST: 0x75 PCI: 00:14.0 init PCI: 00:14.0 init 1848 usecs POST: 0x75 PCI: 00:15.0 init PCI: 00:15.0 init 1848 usecs POST: 0x75 PCI: 00:16.0 init PCI: 00:16.0 init 1848 usecs POST: 0x75 POST: 0x75 PCI: 00:18.0 init PCI: 00:18.0 init 1848 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:18.6 init PCI: 00:18.6 init 1848 usecs POST: 0x75 PCI: 00:18.7 init PCI: 00:18.7 init 1848 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:1e.0 init PCI: 00:1e.0 init 1848 usecs POST: 0x75 PCI: 00:1e.1 init PCI: 00:1e.1 init 1848 usecs POST: 0x75 PCI: 00:1e.2 init PCI: 00:1e.2 init 1848 usecs POST: 0x75 PCI: 00:1e.3 init PCI: 00:1e.3 init 1848 usecs POST: 0x75 PCI: 00:1e.4 init PCI: 00:1e.4 init 1848 usecs POST: 0x75 PCI: 00:1e.5 init PCI: 00:1e.5 init 1847 usecs POST: 0x75 PCI: 00:1f.0 init soc: southcluster_init Southbridge APIC ID = 2 PCI_CFG IRQ: Write PCI config space IRQ assignments Warning: PCI Device 2 does not have an IRQ entry, skipping it Warning: PCI Device 22 does not have an IRQ entry, skipping it PCI_CFG IRQ: Finished writing PCI config space IRQ assignments PCI: 00:1f.0 init 30475 usecs POST: 0x75 PCI: 00:1f.3 init PCI: 00:1f.3 init 1848 usecs POST: 0x75 PCI: 01:00.0 init PCI: 01:00.0 init 1848 usecs Devices initialized BS: BS_DEV_INIT times (us): entry 0 run 265585 exit 0 POST: 0x76 Finalize devices... DOMAIN: 0000 final FspNotify(EnumInitPhaseAfterPciEnumeration) Devices finalized BS: BS_POST_DEVICE times (us): entry 0 run 11909 exit 0 POST: 0x77 BS: BS_OS_RESUME_CHECK times (us): entry 0 run 1170 exit 0 === FSP HOB Data Structure === FSP Hoblistptr: 0x7bb20000 HOB 0x7bb20000 is an EFI_HOB_TYPE_HANDOFF (type 0x1) HOB 0x7bb20038 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x7bb200b0 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x7bb201a8 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x7bb21838 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) HOB 0x7bb21868 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) HOB 0x7bb21898 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) HOB 0x7bb218c8 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) HOB 0x7bb218f8 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) HOB 0x7bb21928 is an EFI_HOB_TYPE_RESOURCE_DESCRIPTOR (type 0x3) HOB 0x7bb21958 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x7bb22fe8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb23018 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb23048 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb23078 is an EFI_HOB_TYPE_GUID_EXTENSION (type 0x4) HOB 0x7bb27090 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb270c8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb270f8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb27128 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb27158 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb27188 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb271b8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb271e8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb27218 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb27248 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb27278 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb272a8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb272d8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb27308 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb27338 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb27368 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb27398 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb273c8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb273f8 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb27428 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb27458 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb27488 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb274b8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb274d0 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb27510 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb27528 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb27570 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb27580 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb27598 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb275a8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb275b8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb275c8 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb277d0 is an EFI_HOB_TYPE_MEMORY_ALLOCATION (type 0x2) HOB 0x7bb27800 is an EFI_HOB_TYPE_MEMORY_POOL (type 0x7) HOB 0x7bb27910 is an EFI_HOB_TYPE_END_OF_HOB_LIST (type 0xffff) === End of FSP HOB Data Structure === Memory Configure Data Hob at 7bb21970 (size = 0x1690). Copy FSP MRC DATA to HOB (source addr 7bb21970, dest addr 7bafa000, 5776 bytes) Updating fast boot cache data. find_current_mrc_cache_local: No valid fast boot cache found. SF: Detected W25Q64DW with page size 1000, total 800000 Need to erase the MRC cache region of 65536 bytes at fff50000 SF: Successfully erased 65536 bytes <at> 0x750000 Write MRC cache update to flash at fff50000 POST: 0x79 POST: 0x9c ACPI: Writing ACPI tables at 7baee000. ACPI: * FACS <at> 7baee210 Length 40ACPI: * DSDT <at> 7baee250 Length 2a89SCI is IRQ9 ACPI: added table 1/32, length now 40 ACPI: * FADT <at> 7baf0ce0 Length f4ACPI: added table 2/32, length now 44 ACPI: * HPET <at> 7baf0de0 Length 38 ACPI: added table 3/32, length now 48 ACPI: * MADT <at> 7baf0e20 Length 5c ACPI: added table 4/32, length now 52 ACPI: * MCFG <at> 7baf0e80 Length 3c ACPI: Could not find CBMEM GNVS ACPI: Patching up global NVS in DSDT at offset 0x009f -> 7baf0ec0 ACPI Updated DSDT <at> 7baee250 Length 2a89 PSS: 1333MHz power 151000 control 0xa38 status 0xa38 PSS: 1199MHz power 134269 control 0x936 status 0x936 PSS: 1066MHz power 118021 control 0x833 status 0x833 PSS: 933MHz power 102106 control 0x731 status 0x731 PSS: 799MHz power 86432 control 0x62e status 0x62e PSS: 666MHz power 71196 control 0x52c status 0x52c PSS: 533MHz power 56292 control 0x429 status 0x429 PSS: 1333MHz power 151000 control 0xa38 status 0xa38 PSS: 1199MHz power 134269 control 0x936 status 0x936 PSS: 1066MHz power 118021 control 0x833 status 0x833 PSS: 933MHz power 102106 control 0x731 status 0x731 PSS: 799MHz power 86432 control 0x62e status 0x62e PSS: 666MHz power 71196 control 0x52c status 0x52c PSS: 533MHz power 56292 control 0x429 status 0x429 ACPI: added table 5/32, length now 56 ACPI: * SSDT <at> 7baf1070 Length 6bc ACPI: * SSDT2 not generated. current = 7baf1730 ACPI: done. ACPI tables: 14128 bytes. smbios_write_tables: 7baec000 Root Device (Intel Minnow Max 2GB) CPU_CLUSTER: 0 (Intel BayTrail SoC) APIC: 00 (Intel BayTrail SoC) DOMAIN: 0000 (Intel BayTrail SoC) PCI: 00:00.0 (Intel BayTrail SoC) PCI: 00:02.0 (Intel BayTrail SoC) PCI: 00:03.0 (Intel BayTrail SoC) PCI: 00:10.0 (Intel BayTrail SoC) PCI: 00:11.0 (Intel BayTrail SoC) PCI: 00:12.0 (Intel BayTrail SoC) PCI: 00:13.0 (Intel BayTrail SoC) PCI: 00:14.0 (Intel BayTrail SoC) PCI: 00:15.0 (Intel BayTrail SoC) PCI: 00:17.0 (Intel BayTrail SoC) PCI: 00:18.0 (Intel BayTrail SoC) PCI: 00:18.1 (Intel BayTrail SoC) PCI: 00:18.2 (Intel BayTrail SoC) PCI: 00:18.3 (Intel BayTrail SoC) PCI: 00:18.4 (Intel BayTrail SoC) PCI: 00:18.5 (Intel BayTrail SoC) PCI: 00:18.6 (Intel BayTrail SoC) PCI: 00:18.7 (Intel BayTrail SoC) PCI: 00:1a.0 (Intel BayTrail SoC) PCI: 00:1b.0 (Intel BayTrail SoC) PCI: 00:1c.0 (Intel BayTrail SoC) PCI: 00:1c.1 (Intel BayTrail SoC) PCI: 00:1c.2 (Intel BayTrail SoC) PCI: 00:1c.3 (Intel BayTrail SoC) PCI: 00:1d.0 (Intel BayTrail SoC) PCI: 00:1e.0 (Intel BayTrail SoC) PCI: 00:1e.1 (Intel BayTrail SoC) PCI: 00:1e.2 (Intel BayTrail SoC) PCI: 00:1e.3 (Intel BayTrail SoC) PCI: 00:1e.4 (Intel BayTrail SoC) PCI: 00:1e.5 (Intel BayTrail SoC) PCI: 00:1f.0 (Intel BayTrail SoC) PCI: 00:1f.3 (Intel BayTrail SoC) PCI: 00:16.0 (unknown) PCI: 01:00.0 (unknown) APIC: 04 (unknown) SMBIOS tables: 353 bytes. POST: 0x9e POST: 0x9d Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4430 Table forward entry ends at 0x00000528. ... aligned to 0x00001000 Writing coreboot table at 0x7bae4000 rom_table_end = 0x7bae4000 ... aligned to 0x7baf0000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 000000007bae4000-000000007bafffff: CONFIGURATION TABLES 2. 00000000feb00000-00000000fec00fff: RESERVED 3. 00000000fed01000-00000000fed01fff: RESERVED 4. 00000000fed03000-00000000fed03fff: RESERVED 5. 00000000fed05000-00000000fed05fff: RESERVED 6. 00000000fed08000-00000000fed08fff: RESERVED 7. 00000000fed0c000-00000000fed0ffff: RESERVED 8. 00000000fed1c000-00000000fed1cfff: RESERVED 9. 00000000fef00000-00000000feffffff: RESERVED 10. 00000000ff800000-00000000ffffffff: RESERVED Wrote coreboot table at: 7bae4000, 0x1b8 bytes, checksum d393 coreboot table: 464 bytes. CBMEM ROOT 0. 7baff000 00001000 484f4221 1. 7bafe000 00001000 ROMSTAGE 2. 7bafd000 00001000 GDT 3. 7bafc000 00001000 MRC DATA 4. 7bafa000 00002000 ACPI 5. 7baee000 0000c000 GNVS PTR 6. 7baed000 00001000 SMBIOS 7. 7baec000 00001000 COREBOOT 8. 7bae4000 00008000 FspNotify(EnumInitPhaseReadyToBoot) BS: BS_WRITE_TABLES times (us): entry 913322 run 411522 exit 0 POST: 0x7a CBFS: located payload <at> ffd26078, 52965 bytes. Loading segment from rom address 0xffd26078 code (compression=1) New segment dstaddr 0xe7170 memsize 0x18e90 srcaddr 0xffd260b0 filesize 0xcead (cleaned up) New segment addr 0xe7170 size 0x18e90 offset 0xffd260b0 filesize 0xcead Loading segment from rom address 0xffd26094 Entry Point 0x000fd53e Payload being loaded below 1MiB without region being marked as RAM usable. Could not find a bounce buffer... Could not load payload
--

-- 
coreboot mailing list: coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Himanshu Chauhan | 17 Sep 05:28 2014

[PATCH] Adding Virtio block device support

Coreboot+Filo can be used in virtualized environments
where the Virtio support is needed sometimes.

Signed-off-by: Himanshu Chauhan <hschauhan <at> nulltrace.org>
---
 Config.in             |  13 +++
 drivers/Makefile.inc  |   2 +
 drivers/virtio-blk.c  | 266 ++++++++++++++++++++++++++++++++++++++++++++++++++
 drivers/virtio-blk.h  |  46 +++++++++
 drivers/virtio-pci.c  | 125 ++++++++++++++++++++++++
 drivers/virtio-pci.h  | 110 +++++++++++++++++++++
 drivers/virtio-ring.c | 158 ++++++++++++++++++++++++++++++
 drivers/virtio-ring.h | 130 ++++++++++++++++++++++++
 fs/blockdev.c         |  30 +++++-
 include/fs.h          |   6 ++
 10 files changed, 885 insertions(+), 1 deletion(-)
 create mode 100644 drivers/virtio-blk.c
 create mode 100644 drivers/virtio-blk.h
 create mode 100644 drivers/virtio-pci.c
 create mode 100644 drivers/virtio-pci.h
 create mode 100644 drivers/virtio-ring.c
 create mode 100644 drivers/virtio-ring.h

diff --git a/Config.in b/Config.in
index cc48bd3..6f13b96 100644
--- a/Config.in
+++ b/Config.in
 <at>  <at>  -143,6 +143,19  <at>  <at>  config IDE_NEW_DISK
 	help
 	  Jens Axboe's fine IDE driver

+config SUPPORT_VIRTIO
+	bool "Support Virtio Drivers"
+	default n
+	help
+		Enable the support for Virtio devices.
+
+config VIRTIO_DISK
+	bool "Support virtio block device"
+	default n
+	depends on SUPPORT_VIRTIO
+	help
+		Enable support for virtio block devices
+
 config LIBPAYLOAD_STORAGE
 	bool "Use libpayload's storage drivers"
 	default n
diff --git a/drivers/Makefile.inc b/drivers/Makefile.inc
index 941c151..a407baf 100644
--- a/drivers/Makefile.inc
+++ b/drivers/Makefile.inc
 <at>  <at>  -24,3 +24,5  <at>  <at>  TARGETS-$(CONFIG_VIA_SOUND) += drivers/via-sound.o
 TARGETS-$(CONFIG_USB_DISK) += drivers/usb.o
 TARGETS-$(CONFIG_TARGET_I386) += drivers/intel.o
 TARGETS-$(CONFIG_TARGET_I386) += drivers/amd.o drivers/sb600.o
+TARGETS-$(CONFIG_SUPPORT_VIRTIO) += drivers/virtio-pci.o drivers/virtio-ring.o
+TARGETS-$(CONFIG_VIRTIO_DISK) += drivers/virtio-blk.o
\ No newline at end of file
diff --git a/drivers/virtio-blk.c b/drivers/virtio-blk.c
new file mode 100644
index 0000000..f31758d
--- /dev/null
+++ b/drivers/virtio-blk.c
 <at>  <at>  -0,0 +1,266  <at>  <at> 
+// Virtio block boot support.
+//
+// Copyright (C) 2010 Red Hat Inc.
+// Copyright (c) 2014 Himanshu chauhan <hschauhan <at> nulltrace.org>
+//
+// Authors:
+//  Gleb Natapov <gnatapov <at> redhat.com>
+//
+// This file may be distributed under the terms of the GNU LGPLv3 license.
+//
+// Himanshu: Ported from seabios virtio.
+//
+
+#include <libpayload.h>
+#include <config.h>
+#include <lib.h>
+#include <fs.h>
+#include <arch/timer.h>
+#include <arch/virtual.h>
+#include <arch/io.h>
+#ifdef CONFIG_SUPPORT_PCI
+#include <pci.h>
+#endif
+
+#define DEBUG_THIS CONFIG_DEBUG_VIRTIO_PCI
+#include <debug.h>
+
+#include "virtio-pci.h"
+#include "virtio-ring.h"
+#include "virtio-blk.h"
+
+struct disk_info {
+	uint16_t type;
+	uint16_t heads;
+	uint16_t cylinders;
+	uint16_t sectors_per_track;
+	uint8_t  model_number[41];
+	uint8_t  slave;
+	sector_t sectors;
+	int  address_mode;
+#define ADDRESS_MODE_CHS    0
+#define ADDRESS_MODE_LBA    1
+#define ADDRESS_MODE_LBA48  2
+#define ADDRESS_MODE_PACKET 3
+	uint32_t blksize;
+	unsigned present : 1;
+};
+
+struct virtiodrive_s {
+	struct disk_info drive;
+	struct vring_virtqueue *vq;
+	pcidev_t bdf;
+	uint16_t ioaddr;
+	int init_done;
+};
+
+#define MAX_VIRTIO_DEVICES	4
+
+struct virtio_drives {
+	int scan_done;
+	int found;
+	struct virtiodrive_s disks[MAX_VIRTIO_DEVICES];
+} vdrives = { .scan_done = 0, .found = 0 };
+
+static int
+virtio_blk_op(struct virtiodrive_s *vdrive_g, sector_t sector, void *buf_fl,
+	      int write)
+{
+	struct vring_virtqueue *vq = vdrive_g->vq;
+	struct virtio_blk_outhdr hdr = {
+		.type = write ? VIRTIO_BLK_T_OUT : VIRTIO_BLK_T_IN,
+		.ioprio = 0,
+		.sector = sector,
+	};
+
+	u8 status = VIRTIO_BLK_S_UNSUPP;
+	struct vring_list sg[] = {
+		{
+			.addr       = (char *)&hdr,
+			.length     = sizeof(hdr),
+		},
+		{
+			.addr       = buf_fl,
+			.length     = vdrive_g->drive.blksize,
+		},
+		{
+			.addr       = (char *)&status,
+			.length     = sizeof(status),
+		},
+	};
+
+	/* Add to virtqueue and kick host */
+	if (write) {
+		vring_add_buf(vq, sg, 2, 1, 0, 0);
+	} else {
+		vring_add_buf(vq, sg, 1, 2, 0, 0);
+	}
+
+	vring_kick(vdrive_g->ioaddr, vq, 1);
+
+	/* Wait for reply */
+	while (!vring_more_used(vq))
+		mdelay(5);
+
+	barrier();
+
+	/* Reclaim virtqueue element */
+	vring_get_buf(vq, NULL);
+
+	/* Clear interrupt status register.  Avoid leaving interrupts stuck if
+	 * VRING_AVAIL_F_NO_INTERRUPT was ignored and interrupts were raised.
+	 */
+	vp_get_isr(vdrive_g->ioaddr);
+
+	if (status != VIRTIO_BLK_S_OK)
+		return -1;
+
+	return 0;
+}
+
+int virtio_blk_read(int drive, sector_t sector, void *buffer)
+{
+	int ret;
+
+	if (drive > MAX_VIRTIO_DEVICES || drive >= vdrives.found)
+		return 0;
+
+	ret = virtio_blk_op(&vdrives.disks[drive], sector, buffer, 0);
+	return ret;
+}
+
+/**/
+/* FIXME: FILO Will Never Write it seems, if it does later add write routine */
+/**/
+static int init_virtio_blk(struct virtiodrive_s *vdisk)
+{
+	u16 bdf = vdisk->bdf;
+	debug("found virtio-blk at %x:%x\n", PCI_BUS(bdf), PCI_SLOT(bdf));
+
+	if (vdisk->init_done) return 0;
+
+	memset(vdisk, 0, sizeof(struct virtiodrive_s));
+	vdisk->drive.type = DTYPE_VIRTIO_BLK;
+
+	u16 ioaddr = vp_init_simple(bdf);
+	vdisk->ioaddr = ioaddr;
+	if (vp_find_vq(ioaddr, 0, &vdisk->vq) < 0 ) {
+		printf("fail to find vq for virtio-blk %x:%x\n",
+		       PCI_BUS(bdf), PCI_SLOT(bdf));
+		goto fail;
+	}
+
+	struct virtio_blk_config cfg;
+	vp_get(ioaddr, 0, &cfg, sizeof(cfg));
+
+	u32 f = vp_get_features(ioaddr);
+	vdisk->drive.blksize = (f & (1 << VIRTIO_BLK_F_BLK_SIZE)) ?
+		cfg.blk_size : DISK_SECTOR_SIZE;
+
+	vdisk->drive.sectors = cfg.capacity;
+	printf("virtio-blk %x:%x blksize=%d sectors=%u\n",
+	       PCI_BUS(bdf), PCI_SLOT(bdf),
+	       vdisk->drive.blksize, (u32)vdisk->drive.sectors);
+
+	if (vdisk->drive.blksize != DISK_SECTOR_SIZE) {
+		printf("virtio-blk %x:%x block size %d is unsupported\n",
+		       PCI_BUS(bdf), PCI_SLOT(bdf),
+		       vdisk->drive.blksize);
+		goto fail;
+	}
+
+	vdisk->drive.cylinders = cfg.cylinders;
+	vdisk->drive.heads = cfg.heads;
+	vdisk->drive.sectors = cfg.sectors;
+	vdisk->drive.present = 1;
+	vdisk->init_done = 1;
+
+	vp_set_status(ioaddr, VIRTIO_CONFIG_S_ACKNOWLEDGE |
+		      VIRTIO_CONFIG_S_DRIVER | VIRTIO_CONFIG_S_DRIVER_OK);
+
+	return 0;
+
+fail:
+	free(vdisk->vq);
+
+	return -1;
+}
+
+#ifdef CONFIG_SUPPORT_PCI
+static int pci_find_virtio_disk_on_bus(int bus)
+{
+	int device, func;
+	u32 vendor, devid;
+	u32 val;
+
+        for (device = 0; device < 32; device++) {
+		for (func = 0; func < 8; func++) {
+			pcidev_t currdev = PCI_DEV(bus, device, func);
+
+			val = pci_read_config32(currdev, REG_VENDOR_ID);
+			vendor = val & 0xFFFF;
+			devid = val >> 16;
+
+			if (vendor == PCI_VENDOR_ID_REDHAT_QUMRANET
+			    && devid == PCI_DEVICE_ID_VIRTIO_BLK) {
+				if (vdrives.found < MAX_VIRTIO_DEVICES) {
+					vdrives.disks[vdrives.found].bdf = currdev;
+					vdrives.found++;
+				}
+			}
+		}
+	}
+
+	vdrives.scan_done = 1;
+
+	if (vdrives.found)
+		return vdrives.found;
+
+	return -1;
+}
+
+int pci_find_virtio_disks(int bus)
+{
+	debug(" Scanning for Virtio Disks on Bus %d\n", bus);
+	return pci_find_virtio_disk_on_bus(bus);
+}
+
+static int find_virtio_disks(void)
+{
+	/* Find a Virtio storage device */
+	if (!pci_find_virtio_disks(0)) {
+		debug("PCI Virtio Disks not found\n");
+		return -1;
+	}
+	
+	return 0;
+}
+#else /* !CONFIG_SUPPORT_PCI */
+# define find_virtio_disks()	(-1)
+#endif
+
+int virtio_disk_probe(int drive)
+{
+	if (drive >= MAX_VIRTIO_DEVICES) {
+		printf("Unsupported drive number\n");
+		return -1;
+	}
+
+	if (!vdrives.scan_done) {
+		if (find_virtio_disks() != 0) {
+			return -1;
+		}
+	}
+
+	if (drive >= vdrives.found) {
+		printf("No drive at number %d\n", drive);
+		return -1;
+	}
+
+	if (init_virtio_blk(&vdrives.disks[drive]) != 0) {
+		printf("No drive detected at virtio index %d\n", drive);
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/drivers/virtio-blk.h b/drivers/virtio-blk.h
new file mode 100644
index 0000000..626c4c0
--- /dev/null
+++ b/drivers/virtio-blk.h
 <at>  <at>  -0,0 +1,46  <at>  <at> 
+#ifndef _VIRTIO_BLK_H
+#define _VIRTIO_BLK_H
+
+struct virtio_blk_config
+{
+    u64 capacity;
+    u32 size_max;
+    u32 seg_max;
+    u16 cylinders;
+    u8 heads;
+    u8 sectors;
+    u32 blk_size;
+    u8 physical_block_exp;
+    u8 alignment_offset;
+    u16 min_io_size;
+    u32 opt_io_size;
+} __attribute__((packed));
+
+#define VIRTIO_BLK_F_BLK_SIZE 6
+
+/* These two define direction. */
+#define VIRTIO_BLK_T_IN         0
+#define VIRTIO_BLK_T_OUT        1
+
+/* This is the first element of the read scatter-gather list. */
+struct virtio_blk_outhdr {
+    /* VIRTIO_BLK_T* */
+    u32 type;
+    /* io priority. */
+    u32 ioprio;
+    /* Sector (ie. 512 byte offset) */
+    u64 sector;
+};
+
+#define VIRTIO_BLK_S_OK         0
+#define VIRTIO_BLK_S_IOERR      1
+#define VIRTIO_BLK_S_UNSUPP     2
+
+#define DTYPE_VIRTIO_BLK	0x09
+#define DISK_SECTOR_SIZE	512
+
+struct disk_op_s;
+int process_virtio_blk_op(struct disk_op_s *op);
+void virtio_blk_setup(void);
+
+#endif /* _VIRTIO_BLK_H */
diff --git a/drivers/virtio-pci.c b/drivers/virtio-pci.c
new file mode 100644
index 0000000..e61c959
--- /dev/null
+++ b/drivers/virtio-pci.c
 <at>  <at>  -0,0 +1,125  <at>  <at> 
+/* virtio-pci.c - pci interface for virtio interface
+ *
+ * (c) Copyright 2008 Bull S.A.S.
+ *
+ *  Author: Laurent Vivier <Laurent.Vivier <at> bull.net>
+ *
+ * some parts from Linux Virtio PCI driver
+ *
+ *  Copyright IBM Corp. 2007
+ *  Authors: Anthony Liguori  <aliguori <at> us.ibm.com>
+ *
+ *  Adopted for Seabios: Gleb Natapov <gleb <at> redhat.com>
+ *
+ *  Further adopted to FILO: Himanshu Chauhan <hschauhan <at> nulltrace.org>
+ *
+ * This work is licensed under the terms of the GNU LGPLv3
+ * See the COPYING file in the top-level directory.
+ */
+
+#include <libpayload.h>
+#include <config.h>
+#include <lib.h>
+#include <fs.h>
+#include <arch/timer.h>
+#include <arch/virtual.h>
+#include <arch/io.h>
+#ifdef CONFIG_SUPPORT_PCI
+#include <pci.h>
+#endif
+
+#define DEBUG_THIS CONFIG_DEBUG_VIRTIO_PCI
+#include <debug.h>
+
+#include "virtio-ring.h"
+#include "virtio-pci.h"
+
+/* 
+ * Base addresses specify locations in memory or I/O space.
+ * Decoded size can be determined by writing a value of
+ * 0xffffffff to the register, and reading it back.  Only
+ * 1 bits are decoded.
+ */
+#define PCI_BASE_ADDRESS_0      0x10    /* 32 bits */
+#define PCI_BASE_ADDRESS_1      0x14    /* 32 bits [htype 0,1 only] */
+#define PCI_BASE_ADDRESS_2      0x18    /* 32 bits [htype 0 only] */
+#define PCI_BASE_ADDRESS_3      0x1c    /* 32 bits */
+#define PCI_BASE_ADDRESS_4      0x20    /* 32 bits */
+#define PCI_BASE_ADDRESS_5      0x24    /* 32 bits */
+#define  PCI_BASE_ADDRESS_SPACE         0x01    /* 0 = memory, 1 = I/O */
+#define  PCI_BASE_ADDRESS_SPACE_IO      0x01
+#define  PCI_BASE_ADDRESS_SPACE_MEMORY  0x00
+#define  PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
+#define  PCI_BASE_ADDRESS_MEM_TYPE_32   0x00    /* 32 bit address */
+#define  PCI_BASE_ADDRESS_MEM_TYPE_1M   0x02    /* Below 1M [obsolete] */
+#define  PCI_BASE_ADDRESS_MEM_TYPE_64   0x04    /* 64 bit address */
+#define  PCI_BASE_ADDRESS_MEM_PREFETCH  0x08    /* prefetchable? */
+#define  PCI_BASE_ADDRESS_MEM_MASK      (~0x0fUL)
+#define  PCI_BASE_ADDRESS_IO_MASK       (~0x03UL)
+
+int vp_find_vq(unsigned int ioaddr, int queue_index,
+               struct vring_virtqueue **p_vq)
+{
+	uint16_t num;
+
+	struct vring_virtqueue *vq = *p_vq = malloc(sizeof(*vq));
+	if (!vq) {
+		goto fail;
+	}
+	memset(vq, 0, sizeof(*vq));
+
+	/* select the queue */
+	outw(queue_index, ioaddr + VIRTIO_PCI_QUEUE_SEL);
+
+	/* check if the queue is available */
+	num = inw(ioaddr + VIRTIO_PCI_QUEUE_NUM);
+	if (!num) {
+		debug("ERROR: queue size is 0\n");
+		goto fail;
+	}
+
+	if (num > MAX_QUEUE_NUM) {
+		debug("ERROR: queue size %d > %d\n", num, MAX_QUEUE_NUM);
+		goto fail;
+	}
+
+	/* check if the queue is already active */
+	if (inl(ioaddr + VIRTIO_PCI_QUEUE_PFN)) {
+		debug("ERROR: queue already active\n");
+		goto fail;
+	}
+
+	vq->queue_index = queue_index;
+
+	/* initialize the queue */
+
+	struct vring * vr = &vq->vring;
+	vring_init(vr, num, (unsigned char*)&vq->queue);
+
+	/* activate the queue
+	 *
+	 * NOTE: vr->desc is initialized by vring_init()
+	 */
+
+	outl((unsigned long)virt_to_phys(vr->desc) >> PAGE_SHIFT,
+	     ioaddr + VIRTIO_PCI_QUEUE_PFN);
+
+	return num;
+
+fail:
+	free(vq);
+	*p_vq = NULL;
+	return -1;
+}
+
+uint16_t vp_init_simple(uint16_t bdf)
+{
+	uint16_t ioaddr = pci_read_config32((0x80000000 | bdf), PCI_BASE_ADDRESS_0) &
+		PCI_BASE_ADDRESS_IO_MASK;
+
+	debug("%s: ioaddr: 0x%x\n", __func__, ioaddr);
+	vp_reset(ioaddr);
+	vp_set_status(ioaddr, VIRTIO_CONFIG_S_ACKNOWLEDGE |
+		      VIRTIO_CONFIG_S_DRIVER );
+	return ioaddr;
+}
diff --git a/drivers/virtio-pci.h b/drivers/virtio-pci.h
new file mode 100644
index 0000000..19966b4
--- /dev/null
+++ b/drivers/virtio-pci.h
 <at>  <at>  -0,0 +1,110  <at>  <at> 
+#ifndef _VIRTIO_PCI_H
+#define _VIRTIO_PCI_H
+
+#include <arch/types.h>
+#include <arch/virtual.h>
+#include <arch/io.h>
+
+/* A 32-bit r/o bitmask of the features supported by the host */
+#define VIRTIO_PCI_HOST_FEATURES        0
+
+/* A 32-bit r/w bitmask of features activated by the guest */
+#define VIRTIO_PCI_GUEST_FEATURES       4
+
+/* A 32-bit r/w PFN for the currently selected queue */
+#define VIRTIO_PCI_QUEUE_PFN            8
+
+/* A 16-bit r/o queue size for the currently selected queue */
+#define VIRTIO_PCI_QUEUE_NUM            12
+
+/* A 16-bit r/w queue selector */
+#define VIRTIO_PCI_QUEUE_SEL            14
+
+/* A 16-bit r/w queue notifier */
+#define VIRTIO_PCI_QUEUE_NOTIFY         16
+
+/* An 8-bit device status register.  */
+#define VIRTIO_PCI_STATUS               18
+
+/* An 8-bit r/o interrupt status register.  Reading the value will return the
+ * current contents of the ISR and will also clear it.  This is effectively
+ * a read-and-acknowledge. */
+#define VIRTIO_PCI_ISR                  19
+
+/* The bit of the ISR which indicates a device configuration change. */
+#define VIRTIO_PCI_ISR_CONFIG           0x2
+
+/* The remaining space is defined by each driver as the per-driver
+ * configuration space */
+#define VIRTIO_PCI_CONFIG               20
+
+/* Virtio ABI version, this must match exactly */
+#define VIRTIO_PCI_ABI_VERSION          0
+
+#define PCI_VENDOR_ID_REDHAT_QUMRANET   0x1af4
+#define PCI_DEVICE_ID_VIRTIO_BLK        0x1001
+
+static inline uint32_t vp_get_features(unsigned int ioaddr)
+{
+	return inl(ioaddr + VIRTIO_PCI_HOST_FEATURES);
+}
+
+static inline void vp_set_features(unsigned int ioaddr, uint32_t features)
+{
+        outl(features, ioaddr + VIRTIO_PCI_GUEST_FEATURES);
+}
+
+static inline void vp_get(unsigned int ioaddr, unsigned offset,
+			  void *buf, unsigned len)
+{
+	uint8_t *ptr = buf;
+	unsigned i;
+
+	for (i = 0; i < len; i++)
+		ptr[i] = inb(ioaddr + VIRTIO_PCI_CONFIG + offset + i);
+}
+
+static inline uint8_t vp_get_status(unsigned int ioaddr)
+{
+	return inb(ioaddr + VIRTIO_PCI_STATUS);
+}
+
+static inline void vp_set_status(unsigned int ioaddr, uint8_t status)
+{
+	if (status == 0)        /* reset */
+		return;
+	outb(status, ioaddr + VIRTIO_PCI_STATUS);
+}
+
+static inline uint8_t vp_get_isr(unsigned int ioaddr)
+{
+	return inb(ioaddr + VIRTIO_PCI_ISR);
+}
+
+static inline void vp_reset(unsigned int ioaddr)
+{
+	outb(0, ioaddr + VIRTIO_PCI_STATUS);
+	(void)inb(ioaddr + VIRTIO_PCI_ISR);
+}
+
+static inline void vp_notify(unsigned int ioaddr, int queue_index)
+{
+	outw(queue_index, ioaddr + VIRTIO_PCI_QUEUE_NOTIFY);
+}
+
+static inline void vp_del_vq(unsigned int ioaddr, int queue_index)
+{
+	/* select the queue */
+
+	outw(queue_index, ioaddr + VIRTIO_PCI_QUEUE_SEL);
+
+	/* deactivate the queue */
+
+	outl(0, ioaddr + VIRTIO_PCI_QUEUE_PFN);
+}
+
+struct vring_virtqueue;
+uint16_t vp_init_simple(uint16_t bdf);
+int vp_find_vq(unsigned int ioaddr, int queue_index,
+               struct vring_virtqueue **p_vq);
+#endif /* _VIRTIO_PCI_H_ */
diff --git a/drivers/virtio-ring.c b/drivers/virtio-ring.c
new file mode 100644
index 0000000..2edaa06
--- /dev/null
+++ b/drivers/virtio-ring.c
 <at>  <at>  -0,0 +1,158  <at>  <at> 
+/* virtio-pci.c - virtio ring management
+ *
+ * (c) Copyright 2008 Bull S.A.S.
+ *
+ *  Author: Laurent Vivier <Laurent.Vivier <at> bull.net>
+ *
+ *  some parts from Linux Virtio Ring
+ *
+ *  Copyright Rusty Russell IBM Corporation 2007
+ *
+ *  Adopted for Seabios: Gleb Natapov <gleb <at> redhat.com>
+ *
+ *  Further adopted to FILO: Himanshu Chauhan <hschauhan <at> nulltrace.org>
+ *
+ * This work is licensed under the terms of the GNU LGPLv3
+ * See the COPYING file in the top-level directory.
+ */
+
+#include <libpayload.h>
+#include <config.h>
+#include <lib.h>
+#include <fs.h>
+#include <arch/timer.h>
+#include <arch/virtual.h>
+#include <arch/io.h>
+
+#include "virtio-ring.h"
+#include "virtio-pci.h"
+
+#define barrier() asm volatile("":::"memory");
+
+#define BUG() do {                                                      \
+		printf("BUG: failure at %d/%s()!\n", __LINE__, __func__); \
+		while(1);						\
+        } while (0)
+#define BUG_ON(condition) do { if (condition) BUG(); } while (0)
+
+/*
+ * vring_more_used
+ *
+ * is there some used buffers ?
+ *
+ */
+
+int vring_more_used(struct vring_virtqueue *vq)
+{
+	struct vring_used *used = vq->vring.used;
+	int more = vq->last_used_idx != used->idx;
+	/* Make sure ring reads are done after idx read above. */
+	smp_rmb();
+	return more;
+}
+
+/*
+ * vring_free
+ *
+ * put at the begin of the free list the current desc[head]
+ */
+
+void vring_detach(struct vring_virtqueue *vq, unsigned int head)
+{
+	struct vring *vr = &vq->vring;
+	struct vring_desc *desc = vr->desc;
+	unsigned int i;
+
+	/* find end of given descriptor */
+
+	i = head;
+	while (desc[i].flags & VRING_DESC_F_NEXT)
+		i = desc[i].next;
+
+	/* link it with free list and point to it */
+
+	desc[i].next = vq->free_head;
+	vq->free_head = head;
+}
+
+/*
+ * vring_get_buf
+ *
+ * get a buffer from the used list
+ *
+ */
+
+int vring_get_buf(struct vring_virtqueue *vq, unsigned int *len)
+{
+	struct vring *vr = &vq->vring;
+	struct vring_used_elem *elem;
+	struct vring_used *used = vq->vring.used;
+	uint32_t id;
+	int ret;
+
+	BUG_ON(!vring_more_used(vq));
+
+	elem = &used->ring[vq->last_used_idx % vr->num];
+	id = elem->id;
+	if (len != NULL)
+		*len = elem->len;
+
+	ret = vq->vdata[id];
+
+	vring_detach(vq, id);
+
+	vq->last_used_idx = vq->last_used_idx + 1;
+
+	return ret;
+}
+
+void vring_add_buf(struct vring_virtqueue *vq,
+                   struct vring_list list[],
+                   unsigned int out, unsigned int in,
+                   int index, int num_added)
+{
+	struct vring *vr = &vq->vring;
+	int i, av, head, prev; //, j;
+	struct vring_desc *desc = vr->desc;
+	struct vring_avail *avail = vr->avail;
+
+	BUG_ON(out + in == 0);
+
+	prev = 0;
+	head = vq->free_head;
+	for (i = head; out; i = desc[i].next, out--) {
+		desc[i].flags = VRING_DESC_F_NEXT;
+		desc[i].addr = (uint64_t)virt_to_phys(list->addr);
+		desc[i].len = list->length;
+		prev = i;
+		list++;
+	}
+	for ( ; in; i = desc[i].next, in--) {
+		desc[i].flags = (VRING_DESC_F_NEXT|VRING_DESC_F_WRITE);
+		desc[i].addr = (u64)virt_to_phys(list->addr);
+		desc[i].len = list->length;
+		prev = i;
+		list++;
+	}
+	desc[prev].flags =
+		(desc[prev].flags & ~VRING_DESC_F_NEXT);
+
+	vq->free_head = i;
+
+	vq->vdata[head] = index;
+
+	av = (avail->idx + num_added) % (vr->num);
+	avail->ring[av] = head;
+}
+
+void vring_kick(unsigned int ioaddr, struct vring_virtqueue *vq, int num_added)
+{
+	struct vring *vr = &vq->vring;
+	struct vring_avail *avail = vr->avail;
+
+	/* Make sure idx update is done after ring write. */
+	smp_wmb();
+	avail->idx = (avail->idx + num_added);
+
+	vp_notify(ioaddr, vq->queue_index);
+}
diff --git a/drivers/virtio-ring.h b/drivers/virtio-ring.h
new file mode 100644
index 0000000..bef7926
--- /dev/null
+++ b/drivers/virtio-ring.h
 <at>  <at>  -0,0 +1,130  <at>  <at> 
+#ifndef _VIRTIO_RING_H
+#define _VIRTIO_RING_H
+
+#include <arch/types.h>
+#include <arch/virtual.h>
+#include <arch/io.h>
+
+#define PAGE_SIZE	4096
+#define PAGE_SHIFT 12
+#define PAGE_MASK  (PAGE_SIZE-1)
+
+#define barrier()	asm volatile("":::"memory");
+
+/* Compiler barrier is enough as an x86 CPU does not reorder reads or writes */
+#define smp_rmb() barrier()
+#define smp_wmb() barrier()
+
+/* Status byte for guest to report progress, and synchronize features. */
+/* We have seen device and processed generic fields (VIRTIO_CONFIG_F_VIRTIO) */
+#define VIRTIO_CONFIG_S_ACKNOWLEDGE     1
+/* We have found a driver for the device. */
+#define VIRTIO_CONFIG_S_DRIVER          2
+/* Driver has used its parts of the config, and is happy */
+#define VIRTIO_CONFIG_S_DRIVER_OK       4
+/* We've given up on this device. */
+#define VIRTIO_CONFIG_S_FAILED          0x80
+
+#define MAX_QUEUE_NUM      (128)
+
+#define VRING_DESC_F_NEXT  1
+#define VRING_DESC_F_WRITE 2
+
+#define VRING_AVAIL_F_NO_INTERRUPT 1
+
+#define VRING_USED_F_NO_NOTIFY     1
+
+struct vring_desc
+{
+	uint64_t addr;
+	uint32_t len;
+	uint16_t flags;
+	uint16_t next;
+};
+
+struct vring_avail
+{
+	uint16_t flags;
+	uint16_t idx;
+	uint16_t ring[0];
+};
+
+struct vring_used_elem
+{
+	uint32_t id;
+	uint32_t len;
+};
+
+struct vring_used
+{
+	uint16_t flags;
+	uint16_t idx;
+	struct vring_used_elem ring[];
+};
+
+struct vring {
+	unsigned int num;
+	struct vring_desc *desc;
+	struct vring_avail *avail;
+	struct vring_used *used;
+};
+
+#define vring_size(num)			   \
+	(((((sizeof(struct vring_desc) * num) +		\
+	    (sizeof(struct vring_avail) + sizeof(u16) * num))	\
+	   + PAGE_MASK) & ~PAGE_MASK) +					\
+         (sizeof(struct vring_used) + sizeof(struct vring_used_elem) * num))
+
+typedef unsigned char virtio_queue_t[vring_size(MAX_QUEUE_NUM)];
+
+struct vring_virtqueue {
+	struct vring vring;
+	uint16_t free_head;
+	uint16_t last_used_idx;
+	uint16_t vdata[MAX_QUEUE_NUM];
+	/* PCI */
+	int queue_index;
+	virtio_queue_t queue;
+};
+
+struct vring_list {
+	char *addr;
+	unsigned int length;
+};
+
+static inline void vring_init(struct vring *vr,
+			      unsigned int num, unsigned char *queue)
+{
+	unsigned int i;
+	unsigned long pa;
+
+	vr->num = num;
+
+	/* physical address of desc must be page aligned */
+	pa = virt_to_phys(queue);
+	pa = (pa + PAGE_MASK) & ~PAGE_MASK;
+	vr->desc = phys_to_virt(pa);
+
+	vr->avail = (struct vring_avail *)&vr->desc[num];
+	/* disable interrupts */
+	vr->avail->flags |= VRING_AVAIL_F_NO_INTERRUPT;
+
+	/* physical address of used must be page aligned */
+	pa = virt_to_phys(&vr->avail->ring[num]);
+	pa = (pa + PAGE_MASK) & ~PAGE_MASK;
+	vr->used = phys_to_virt(pa);
+
+	for (i = 0; i < num - 1; i++)
+		vr->desc[i].next = i + 1;
+	vr->desc[i].next = 0;
+}
+
+int vring_more_used(struct vring_virtqueue *vq);
+void vring_detach(struct vring_virtqueue *vq, unsigned int head);
+int vring_get_buf(struct vring_virtqueue *vq, unsigned int *len);
+void vring_add_buf(struct vring_virtqueue *vq, struct vring_list list[],
+                   unsigned int out, unsigned int in,
+                   int index, int num_added);
+void vring_kick(unsigned int ioaddr, struct vring_virtqueue *vq, int num_added);
+
+#endif /* _VIRTIO_RING_H_ */
diff --git a/fs/blockdev.c b/fs/blockdev.c
index 0105712..be5719e 100644
--- a/fs/blockdev.c
+++ b/fs/blockdev.c
 <at>  <at>  -190,7 +190,16  <at>  <at>  static int parse_device_name(const char *name, int *type, int *drive,
 		*type = DISK_MEM;
 		name += 3;
 		*drive = 0;
-	} else {
+	} else if (memcmp(name, "vd", 2) == 0) {
+		*type = DISK_VIRTIO;
+		name += 2;
+		if (*name < 'a' || *name > 'z') {
+			printf("Invalid drive\n");
+			return 0;
+		}
+		*drive = *name - 'a';
+		name++;
+	}else {
 		printf("Unknown device type: %s\n", name);
 		return 0;
 	}
 <at>  <at>  -283,6 +292,16  <at>  <at>  int devopen(const char *name, int *reopen)
 		break;
 #endif

+#ifdef CONFIG_VIRTIO_DISK
+	case DISK_VIRTIO:
+		if (virtio_disk_probe(drive) != 0) {
+			debug("Failed to open virtio disk.\n");
+			return 0;
+		}
+		disk_size = (uint32_t) -1;
+		break;
+#endif
+
 #ifdef CONFIG_FLASH_DISK
 	case DISK_FLASH:
 		if (flash_probe(drive) != 0) {
 <at>  <at>  -447,6 +466,15  <at>  <at>  static void *read_sector(unsigned long sector)
 		}
 #endif

+#ifdef CONFIG_VIRTIO_DISK
+		case DISK_VIRTIO:
+		{
+			if (virtio_blk_read(dev_drive, sector, buf) != 0)
+				goto readerr;
+			break;
+		}
+#endif
+
 #ifdef CONFIG_FLASH_DISK
 		case DISK_FLASH:
 			if (flash_read(dev_drive, sector, buf) != 0)
diff --git a/include/fs.h b/include/fs.h
index c91ace7..9b35ca7 100644
--- a/include/fs.h
+++ b/include/fs.h
 <at>  <at>  -48,10 +48,16  <at>  <at>  int flash_read(int drive, sector_t sector, void *buffer);
 void NAND_close(void);
 #endif

+#ifdef CONFIG_VIRTIO_DISK
+int virtio_disk_probe(int drive);
+int virtio_blk_read(int drive, sector_t sector, void *buffer);
+#endif
+
 #define DISK_IDE 1
 #define DISK_MEM 2
 #define DISK_USB 3
 #define DISK_FLASH 4
+#define DISK_VIRTIO 5

 int devopen(const char *name, int *reopen);
 void devclose(void);
-- 
1.9.1

--

-- 
coreboot mailing list: coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

Shawn C | 16 Sep 22:50 2014

desktop build w/ coreboot

Just curious if anybody could put me in touch with someone in the USA who would be willing to build me a desktop pc with coreboot, upon which I could install my own Linux OS?

Thanks,
Sean
--

-- 
coreboot mailing list: coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
John Lewis | 15 Sep 22:35 2014
Picon

Lenovo N20p Chromebook

Hello,

I've purchased the subject Chromebook with a view to getting some sort 
of custom ROM going for Baytrail based Chromebooks, and I have my first 
brick of the day.

I'm using ChromeOS coreboot and the firmware-clapper-5218.B branch. As 
per the advice Aaron gave me regarding the ASUS C200 some time ago, I 
extracted the reference code binary and changed line 111 in 
src/arch/x86/Makefile.inc as follows:

         $(CBFSTOOL) $ <at> .tmp add -f $(CONFIG_REFCODE_BLOB_FILE) -n 
$(CONFIG_CBFS_PREFIX)/refcode -t raw

Other than that I had to place vboot_api.h from the same branch of 
ChromeOS vboot_reference in the src directory to get compile to 
complete, but have left the ChromeOS stuff in for the time being. My 
.config is attached. Any pointers?

Thanks,

John.
#
# Automatically generated make config: don't edit
# coreboot version: 03c0168-dirty
# Mon Sep 15 19:53:08 2014
#

#
# General setup
#
# CONFIG_EXPERT is not set
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
# CONFIG_ALT_CBFS_LOAD_PAYLOAD is not set
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
# CONFIG_SCANBUILD_ENABLE is not set
# CONFIG_CCACHE is not set
# CONFIG_USE_OPTION_TABLE is not set
CONFIG_COMPRESS_RAMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
# CONFIG_EARLY_CBMEM_INIT is not set
CONFIG_DYNAMIC_CBMEM=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_USE_BLOBS is not set
# CONFIG_COVERAGE is not set

#
# Mainboard
#
# CONFIG_VENDOR_AAEON is not set
# CONFIG_VENDOR_ABIT is not set
# CONFIG_VENDOR_ADVANSUS is not set
# CONFIG_VENDOR_ADVANTECH is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_ARIMA is not set
# CONFIG_VENDOR_ARTECGROUP is not set
# CONFIG_VENDOR_ASI is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_A_TREND is not set
# CONFIG_VENDOR_AVALUE is not set
# CONFIG_VENDOR_AXUS is not set
# CONFIG_VENDOR_AZZA is not set
# CONFIG_VENDOR_BACHMANN is not set
# CONFIG_VENDOR_BCOM is not set
# CONFIG_VENDOR_BIFFEROS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BROADCOM is not set
# CONFIG_VENDOR_COMPAQ is not set
# CONFIG_VENDOR_DIGITALLOGIC is not set
# CONFIG_VENDOR_EAGLELION is not set
# CONFIG_VENDOR_ECS is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
CONFIG_VENDOR_GOOGLE=y
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
# CONFIG_VENDOR_IEI is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_IWAVE is not set
# CONFIG_VENDOR_IWILL is not set
# CONFIG_VENDOR_JETWAY is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LANNER is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIPPERT is not set
# CONFIG_VENDOR_MITAC is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NEC is not set
# CONFIG_VENDOR_NEWISYS is not set
# CONFIG_VENDOR_NOKIA is not set
# CONFIG_VENDOR_NVIDIA is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_RCA is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SOYO is not set
# CONFIG_VENDOR_SUNW is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_TECHNEXION is not set
# CONFIG_VENDOR_TECHNOLOGIC is not set
# CONFIG_VENDOR_TELEVIDEO is not set
# CONFIG_VENDOR_THOMSON is not set
# CONFIG_VENDOR_TRAVERSE is not set
# CONFIG_VENDOR_TYAN is not set
# CONFIG_VENDOR_VIA is not set
# CONFIG_VENDOR_WINENT is not set
# CONFIG_VENDOR_WYSE is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_DIR="google/clapper"
CONFIG_MAINBOARD_PART_NUMBER="Clapper"
CONFIG_MAINBOARD_VENDOR="GOOGLE"
CONFIG_MAX_CPUS=4
CONFIG_RAMTOP=0x200000
CONFIG_HEAP_SIZE=0x4000
CONFIG_RAMBASE=0x100000
CONFIG_VGA_BIOS_ID="8086,0f31"
CONFIG_STACK_SIZE=0x1000
CONFIG_DRIVERS_PS2_KEYBOARD=y
CONFIG_WARNINGS_ARE_ERRORS=y
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_VGA_BIOS=y
# CONFIG_PCI_ROM_RUN is not set
# CONFIG_UDELAY_IO is not set
CONFIG_DCACHE_RAM_BASE=0xff800000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_SERIAL_CPU_INIT=y
CONFIG_ACPI_SSDTX_NUM=0
CONFIG_VGA_BIOS_FILE="3rdparty/mainboard/$(MAINBOARDDIR)/pci8086,0f31.rom"
# CONFIG_PCI_64BIT_PREF_MEM is not set
CONFIG_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_VENDOR_SPECIFIC_OPTIONS=y
# CONFIG_BOARD_GOOGLE_BELTINO is not set
# CONFIG_BOARD_GOOGLE_BOLT is not set
# CONFIG_BOARD_GOOGLE_BUTTERFLY is not set
CONFIG_BOARD_GOOGLE_CLAPPER=y
# CONFIG_BOARD_GOOGLE_FALCO is not set
# CONFIG_BOARD_GOOGLE_LINK is not set
# CONFIG_BOARD_GOOGLE_NYAN is not set
# CONFIG_BOARD_GOOGLE_PANTHER is not set
# CONFIG_BOARD_GOOGLE_PARROT is not set
# CONFIG_BOARD_GOOGLE_PEPPY is not set
# CONFIG_BOARD_GOOGLE_PIT is not set
# CONFIG_BOARD_GOOGLE_RAMBI is not set
# CONFIG_BOARD_GOOGLE_SAMUS is not set
# CONFIG_BOARD_GOOGLE_SLIPPY is not set
# CONFIG_BOARD_GOOGLE_SNOW is not set
# CONFIG_BOARD_GOOGLE_STOUT is not set
CONFIG_VBOOT_RAMSTAGE_INDEX=0x2
CONFIG_VBOOT_REFCODE_INDEX=0x3
CONFIG_SPD_CBFS_ADDRESS=0xfffec000
CONFIG_MMCONF_SUPPORT_DEFAULT=y
# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
CONFIG_LOGICAL_CPUS=y
# CONFIG_IOAPIC is not set
CONFIG_SMP=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
# CONFIG_USBDEBUG is not set
# CONFIG_K8_REV_F_SUPPORT is not set
CONFIG_CPU_ADDR_BITS=36
CONFIG_BOARD_ROMSIZE_KB_8192=y
# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
CONFIG_COREBOOT_ROMSIZE_KB_8192=y
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
CONFIG_COREBOOT_ROMSIZE_KB=8192
CONFIG_ROM_SIZE=0x800000
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_ARCH_X86=y
# CONFIG_ARCH_ARM is not set
# CONFIG_ARCH_AARCH64 is not set

#
# Architecture (x86)
#
CONFIG_X86_ARCH_OPTIONS=y
# CONFIG_MARK_GRAPHICS_MEM_WRCOMB is not set
# CONFIG_AP_IN_SIPI_WAIT is not set
# CONFIG_SIPI_VECTOR_IN_ROM is not set
CONFIG_MAX_REBOOT_CNT=3
CONFIG_X86_BOOTBLOCK_SIMPLE=y
# CONFIG_X86_BOOTBLOCK_NORMAL is not set
CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_ROMCC is not set
CONFIG_PC80_SYSTEM=y
# CONFIG_HAVE_CMOS_DEFAULT is not set
CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set
CONFIG_HPET_ADDRESS=0xfed00000
CONFIG_ID_SECTION_OFFSET=0x80
CONFIG_HAVE_ARCH_MEMSET=y
CONFIG_HAVE_ARCH_MEMCPY=y
CONFIG_HAVE_ARCH_MEMMOVE=y

#
# Chipset
#

#
# CPU
#
CONFIG_BOOTBLOCK_CPU_INIT="soc/intel/baytrail/bootblock/bootblock.c"
CONFIG_XIP_ROM_SIZE=0x10000
CONFIG_CPU_SPECIFIC_OPTIONS=y
# CONFIG_CPU_AMD_AGESA is not set
CONFIG_HAVE_INIT_TIMER=y
CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0
CONFIG_SMM_TSEG_SIZE=0
CONFIG_MICROCODE_INCLUDE_PATH="src/soc/intel/baytrail"
CONFIG_SMM_RESERVED_SIZE=0x100000
# CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE is not set
CONFIG_SSE2=y
# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set
# CONFIG_UDELAY_LAPIC is not set
CONFIG_UDELAY_TSC=y
CONFIG_TSC_CONSTANT_RATE=y
CONFIG_TSC_MONOTONIC_TIMER=y
# CONFIG_UDELAY_TIMER2 is not set
# CONFIG_TSC_CALIBRATE_WITH_IO is not set
# CONFIG_TSC_SYNC_LFENCE is not set
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_CACHE_ROM=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_MODULES=y
CONFIG_SMM_MODULE_HEAP_SIZE=0x4000
# CONFIG_X86_AMD_FIXED_MTRRS is not set
CONFIG_PARALLEL_MP=y
CONFIG_CACHE_AS_RAM=y
CONFIG_AP_SIPI_VECTOR=0xfffff000
CONFIG_CPU_MICROCODE_IN_CBFS=y
CONFIG_CPU_MICROCODE_CBFS_GENERATE=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
CONFIG_CAR_MIGRATION=y

#
# Northbridge
#
CONFIG_VIDEO_MB=0
# CONFIG_NORTHBRIDGE_AMD_AGESA is not set
# CONFIG_AMD_NB_CIMX is not set
# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x8000
CONFIG_HAVE_MRC=y
CONFIG_MRC_FILE="3rdparty/mainboard/$(MAINBOARDDIR)/mrc.bin"
CONFIG_CBFS_SIZE=0x400000
CONFIG_DCACHE_RAM_ROMSTAGE_STACK_SIZE=0x800

#
# Southbridge
#
# CONFIG_AMD_SB_CIMX is not set
# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set
# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set
CONFIG_SPI_FLASH=y
CONFIG_SERIRQ_CONTINUOUS_MODE=y
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set

#
# Super I/O
#

#
# Embedded Controllers
#
CONFIG_EC_GOOGLE_CHROMEEC=y
# CONFIG_EC_GOOGLE_CHROMEEC_I2C is not set
CONFIG_EC_GOOGLE_CHROMEEC_LPC=y
# CONFIG_EC_GOOGLE_CHROMEEC_SPI is not set

#
# SoC
#
CONFIG_SOC_INTEL_BAYTRAIL=y
CONFIG_MRC_BIN_ADDRESS=0xfffa0000
# CONFIG_MRC_RMT is not set
CONFIG_CACHE_MRC_SETTINGS=y
CONFIG_MRC_SETTINGS_CACHE_BASE=0xffb00000
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
CONFIG_ENABLE_BUILTIN_COM1=y

#
# Devices
#
# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set
# CONFIG_VGA_ROM_RUN is not set
# CONFIG_ON_DEVICE_ROM_RUN is not set
# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
CONFIG_PCI=y
# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_AGP_PLUGIN_SUPPORT=y
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
# CONFIG_PCIEXP_COMMON_CLOCK is not set
# CONFIG_PCIEXP_ASPM is not set
CONFIG_PCI_BUS_SEGN_BITS=0

#
# VGA BIOS
#

#
# PXE ROM
#
# CONFIG_PXE_ROM is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000

#
# Generic Drivers
#
# CONFIG_ELOG is not set
# CONFIG_DRIVERS_I2C_RTD2132 is not set
# CONFIG_I2C_TPM is not set
# CONFIG_INTEL_DP is not set
# CONFIG_INTEL_DDI is not set
# CONFIG_IPMI_KCS is not set
# CONFIG_DRIVER_MAXIM_MAX77686 is not set
# CONFIG_DRIVERS_OXFORD_OXPCIE is not set
# CONFIG_DRIVER_PARADE_PS8625 is not set
CONFIG_LPC_TPM=y
# CONFIG_RTL8168_ROM_DISABLE is not set
# CONFIG_DRIVERS_SIL_3114 is not set
# CONFIG_SPI_FLASH_SMM is not set
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_SPI_FLASH_GIGADEVICE=y
# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set
# CONFIG_DRIVER_TI_TPS65090 is not set
CONFIG_TPM=y
CONFIG_MMCONF_SUPPORT=y

#
# Console
#
CONFIG_EARLY_CONSOLE=y
# CONFIG_CONSOLE_SERIAL is not set
# CONFIG_HAVE_USBDEBUG is not set
# CONFIG_CONSOLE_NE2K is not set
# CONFIG_CONSOLE_CBMEM is not set
CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y
# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_7 is not set
# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_1 is not set
# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_0 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
CONFIG_NO_POST=y
# CONFIG_IO_POST is not set
CONFIG_HAVE_UART_IO_MAPPED=y
# CONFIG_HAVE_UART_MEMORY_MAPPED is not set
# CONFIG_HAVE_UART_SPECIAL is not set
CONFIG_HAVE_ACPI_RESUME=y
# CONFIG_HAVE_ACPI_SLIC is not set
CONFIG_HAVE_HARD_RESET=y
CONFIG_HAVE_MONOTONIC_TIMER=y
# CONFIG_TIMER_QUEUE is not set
CONFIG_HAVE_OPTION_TABLE=y
# CONFIG_PIRQ_ROUTE is not set
CONFIG_HAVE_SMI_HANDLER=y
# CONFIG_PCI_IO_CFG_EXT is not set
CONFIG_CACHE_ROM_SIZE=0x400000
# CONFIG_USE_WATCHDOG_ON_BOOT is not set
# CONFIG_VGA is not set
# CONFIG_GFXUMA is not set
CONFIG_RELOCATABLE_MODULES=y
CONFIG_RELOCATABLE_RAMSTAGE=y
CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM=y
CONFIG_HAVE_REFCODE_BLOB=y
CONFIG_REFCODE_BLOB_FILE="3rdparty/mainboard/google/clapper/refcode.bin"
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_MAX_PIRQ_LINKS=4

#
# System tables
#
# CONFIG_MULTIBOOT is not set
CONFIG_GENERATE_ACPI_TABLES=y
# CONFIG_GENERATE_MP_TABLE is not set
# CONFIG_GENERATE_PIRQ_TABLE is not set
CONFIG_GENERATE_SMBIOS_TABLES=y

#
# Payload
#
# CONFIG_PAYLOAD_NONE is not set
CONFIG_PAYLOAD_ELF=y
# CONFIG_PAYLOAD_SEABIOS is not set
# CONFIG_PAYLOAD_FILO is not set
# CONFIG_PAYLOAD_TIANOCORE is not set
CONFIG_PAYLOAD_FILE="../seabios-1.7.5/out/bios.bin.elf"
CONFIG_COMPRESSED_PAYLOAD_LZMA=y
# CONFIG_COMPRESSED_PAYLOAD_NRV2B is not set

#
# Debugging
#
# CONFIG_GDB_STUB is not set
# CONFIG_DEBUG_CBFS is not set
# CONFIG_HAVE_DEBUG_RAM_SETUP is not set
# CONFIG_HAVE_DEBUG_CAR is not set
# CONFIG_HAVE_DEBUG_SMBUS is not set
# CONFIG_DEBUG_SMI is not set
# CONFIG_DEBUG_SMM_RELOCATION is not set
# CONFIG_DEBUG_MALLOC is not set
# CONFIG_DEBUG_ACPI is not set
# CONFIG_DEBUG_TPM is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_LLSHELL is not set
# CONFIG_TRACE is not set
# CONFIG_RAMINIT_SYSINFO is not set
# CONFIG_ENABLE_APIC_EXT_ID is not set
# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
CONFIG_REG_SCRIPT=y
CONFIG_CHROMEOS=y

#
# ChromeOS
#
CONFIG_VBNV_OFFSET=0x26
CONFIG_VBNV_SIZE=0x10
# CONFIG_CHROMEOS_RAMOOPS is not set
CONFIG_FLASHMAP_OFFSET=0x00610000
# CONFIG_VBOOT_VERIFY_FIRMWARE is not set
CONFIG_EC_SOFTWARE_SYNC=y
CONFIG_VIRTUAL_DEV_SWITCH=y
# CONFIG_NO_TPM_RESUME is not set
--

-- 
coreboot mailing list: coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
The Gluglug | 15 Sep 05:01 2014
Picon

fully encrypted install: Parabola/Arch with GRUB payload


http://libreboot.org/docs/howtos/encrypted_parabola.html
Can also be done with Arch, with coreboot and grub payload.

Paul Menzel | 14 Sep 10:10 2014
Picon
Picon

i945: AHCI timeout with Crucial m4 SSD 2.5 in SeaBIOS on cold boot

Dear coreboot and SeaBIOS folks,

testing the SSD Crucial m4 SSD 2.5 256 GB SATA 6 Gb/s on the Lenovo
X60t, the payload SeaBIOS 1.7.5-40-g5109366 does not detect the drive.

        […]
        32.705: |7f673000| WARNING - Timeout at ahci_port_setup:466!
        32.705: |7f673000| AHCI/0: device not ready (tf 0x80)
        33.205: |7f673000| WARNING - Timeout at ahci_port_reset:336!
        […]

Hitting Ctrl + Alt + Delete, the drive is detected.

It is also reproducible on the Lenovo T60 with coreboot from four years
ago and SeaBIOS 1.7.0-91-g7a39e72.

The drive is detected correctly on the ASRock E350M1 with coreboot and
SeaBIOS 1.7.5.

Please find the whole serial log from SeaBIOS below.

Does that look like a coreboot or SeaBIOS problem?

Thanks,

Paul

$ ./scripts/readserial.py /dev/ttyUSB0 115200

======= Sun Sep 14 09:54:52 2014 (adjust=86.8us)
00.000: <00>
01.376: Changing serial settings was 0/0 now 3/0
01.376: SeaBIOS (version rel-1.7.5-40-g5109366-20140715_011246-my-lenovo-x60t)
01.376: Attempting to find coreboot table
01.376: Found coreboot table forwarder.
01.376: Now attempting to find coreboot memory map
01.376: SeaBIOS (version rel-1.7.5-40-g5109366-20140715_011246-my-lenovo-x60t)
01.376: Found coreboot cbmem console  <at>  7f7de000
01.376: Found mainboard Lenovo ThinkPad X60 / X60s
01.376: malloc preinit
01.376: Relocating init from 0x000e6c20 to 0x7f679220 (size 44320)
01.376: malloc init
01.376: Found CBFS header at 0xfffffa50
01.376: Add romfile: cmos_layout.bin (size=1828)
01.376: Add romfile: pci8086,27a2.rom (size=65536)
01.376: Add romfile: cmos.default (size=256)
01.376: Add romfile: cpu_microcode_blob.bin (size=94208)
01.377: Add romfile: etc/ps2-keyboard-spinup (size=8)
01.377: Add romfile: config (size=4221)
01.377: Add romfile:  (size=29976)
01.377: Add romfile: fallback/romstage (size=50939)
01.377: Add romfile: fallback/ramstage (size=68308)
01.377: Add romfile: fallback/payload (size=55644)
01.377: Add romfile:  (size=1723928)
01.377: init ivt
01.377: init bda
01.377: init bios32
01.377: init PMM
01.377: init PNPBIOS table
01.377: init keyboard
01.377: init mouse
01.377: init pic
01.377: math cp init
01.378: CPU Mhz=1663
01.379: init timer
01.379: PCI probe
01.379: PCI device 00:00.0 (vd=8086:27a0 c=0600)
01.379: PCI device 00:02.0 (vd=8086:27a2 c=0300)
01.379: PCI device 00:02.1 (vd=8086:27a6 c=0380)
01.379: PCI device 00:1b.0 (vd=8086:27d8 c=0403)
01.379: PCI device 00:1c.0 (vd=8086:27d0 c=0604)
01.379: PCI device 00:1c.1 (vd=8086:27d2 c=0604)
01.379: PCI device 00:1c.2 (vd=8086:27d4 c=0604)
01.379: PCI device 00:1c.3 (vd=8086:27d6 c=0604)
01.379: PCI device 00:1d.0 (vd=8086:27c8 c=0c03)
01.379: PCI device 00:1d.1 (vd=8086:27c9 c=0c03)
01.379: PCI device 00:1d.2 (vd=8086:27ca c=0c03)
01.379: PCI device 00:1d.3 (vd=8086:27cb c=0c03)
01.379: PCI device 00:1d.7 (vd=8086:27cc c=0c03)
01.379: PCI device 00:1e.0 (vd=8086:2448 c=0604)
01.379: PCI device 00:1f.0 (vd=8086:27b9 c=0601)
01.379: PCI device 00:1f.1 (vd=8086:27df c=0101)
01.379: PCI device 00:1f.2 (vd=8086:27c5 c=0106)
01.379: PCI device 00:1f.3 (vd=8086:27da c=0c05)
01.379: PCI device 01:00.0 (vd=8086:109a c=0200)
01.379: PCI device 02:00.0 (vd=8086:4227 c=0280)
01.380: PCI device 05:00.0 (vd=1180:0476 c=0607)
01.379: PCI device 05:00.1 (vd=1180:0552 c=0c00)
01.380: PCI device 05:00.2 (vd=1180:0822 c=0805)
01.380: Found 23 PCI devices (max PCI bus is 06)
01.380: Relocating coreboot bios tables
01.380: Copying SMBIOS entry point from 0x7f7cc000 to 0x000f1920
01.381: Copying ACPI RSDP from 0x7f7cd000 to 0x000f18f0
01.381: Copying MPTABLE from 0x7f7d9000/7f7d9010 to 0x000f1720
01.381: rsdp=0x000f18f0
01.381: rsdt=0x7f7cd030
01.381: fadt=0x7f7d0510
01.381: pm_tmr_blk=508
01.381: Using pmtimer, ioport 0x508
01.381: Scan for VGA option rom
01.381: Attempting to init PCI bdf 00:02.0 (vd 8086:27a2)
01.381: Copying data 65536 <at> 0xffe007b8 to 65536 <at> 0x000c0000
01.415: Running option rom at c000:0003
01.462: unimplemented handle_155fXX:26:
01.462:    a=80005f34  b=0000078f  c=00000002  d=00000002 ds=0000 es=c000 ss=e000
01.462:   si=00000994 di=00000080 bp=50a06e0c sp=0000ffe8 cs=c000 ip=4a6e  f=0046
01.509: Turning on vga text mode console
01.540: SeaBIOS (version rel-1.7.5-40-g5109366-20140715_011246-my-lenovo-x60t)
01.540: Machine UUID c09ecb7b-2a1f-dc11-b88a-942d40962902
01.540: /7f677000\ Start thread
01.541: |7f677000| init usb
01.541: |7f677000| EHCI init on dev 00:1d.7 (regs=0xe4444020)
01.541: /7f676000\ Start thread
01.541: init ps2port
01.541: /7f674000\ Start thread
01.542: |7f674000| Copying data 8 <at> 0xffe27978 to 8 <at> 0x7f674fc8
01.542: /7f673000\ Start thread
01.542: init lpt
01.542: Found 0 lpt ports
01.542: init serial
01.542: Found 1 serial ports
01.542: init hard drives
01.542: ATA controller 1 at 1f0/3f4/0 (irq 14 dev f9)
01.542: /7f672000\ Start thread
01.542: /7f671000\ Start thread
01.542: ATA controller 2 at 170/374/0 (irq 15 dev f9)
01.542: /7f670000\ Start thread
01.542: |7f670000| powerup IDE floating
01.542: |7f670000| powerup IDE floating
01.542: |7f670000| powerup IDE floating
01.542: |7f670000| powerup IDE floating
01.542: \7f670000/ End thread
01.543: /7f670000\ Start thread
01.543: \7f671000/ End thread
01.543: \7f673000/ End thread
01.543: init ahci
01.542: AHCI controller at 1f.2, iobase e4444400, irq 0
01.543: AHCI: cap 0xdf12ff03, ports_impl 0x1
01.543: /7f673000\ Start thread
01.543: |7f673000| AHCI/0: probing
01.543: /7f671000\ Start thread
01.543: |7f673000| AHCI/0: link up
01.543: |7f672000| DVD/CD [ata0-0: DVD/CDRW UJDA775 ATAPI-5 DVD/CD]
01.543: |7f672000| Searching bootorder for: /pci <at> i0cf8/* <at> 1f,1/drive <at> 0/disk <at> 0
01.543: |7f672000| Registering bootable: DVD/CD [ata0-0: DVD/CDRW UJDA775 ATAPI-5 DVD/CD] (type:3
prio:102 data:f16b0)
01.543: \7f672000/ End thread
01.543: |7f674000| Got ps2 nak (status=51)
01.543: |7f674000| ps2 command 2ff failed (aux=0)
01.543: /7f672000\ Start thread
01.544: \7f671000/ End thread
01.544: \7f670000/ End thread
01.544: /7f671000\ Start thread
01.544: /7f670000\ Start thread
01.544: |7f674000| Got ps2 nak (status=51)
01.544: |7f674000| ps2 command 2ff failed (aux=0)
01.544: /7f66f000\ Start thread
01.546: \7f672000/ End thread
01.546: |7f674000| Got ps2 nak (status=51)
01.546: |7f674000| ps2 command 2ff failed (aux=0)
01.546: \7f670000/ End thread
01.549: |7f674000| Got ps2 nak (status=51)
01.549: |7f674000| ps2 command 2ff failed (aux=0)
01.549: \7f66f000/ End thread
01.551: |7f674000| Got ps2 nak (status=51)
01.551: |7f674000| ps2 command 2ff failed (aux=0)
01.553: |7f674000| Got ps2 nak (status=51)
01.553: |7f674000| ps2 command 2ff failed (aux=0)
01.555: |7f674000| Got ps2 nak (status=51)
01.555: |7f674000| ps2 command 2ff failed (aux=0)
01.557: |7f674000| Got ps2 nak (status=51)
01.557: |7f674000| ps2 command 2ff failed (aux=0)
01.559: |7f674000| Got ps2 nak (status=51)
01.559: |7f674000| ps2 command 2ff failed (aux=0)
01.561: |7f671000| set_address 0x7f678090
01.561: |7f674000| Got ps2 nak (status=51)
01.561: |7f674000| ps2 command 2ff failed (aux=0)
01.561: |7f677000| UHCI init on dev 00:1d.0 (io=5000)
01.561: /7f672000\ Start thread
01.561: /7f670000\ Start thread
01.561: \7f670000/ End thread
01.562: |7f671000| ehci_control 0x7f675450 (dir=0 cmd=8 data=0)
01.562: |7f677000| UHCI init on dev 00:1d.1 (io=5020)
01.562: /7f670000\ Start thread
01.562: /7f66f000\ Start thread
01.562: \7f66f000/ End thread
01.562: /7f66f000\ Start thread
01.562: \7f66f000/ End thread
01.562: |7f677000| UHCI init on dev 00:1d.2 (io=5040)
01.562: /7f66f000\ Start thread
01.562: /7f66e000\ Start thread
01.562: \7f66e000/ End thread
01.562: /7f66e000\ Start thread
01.562: \7f66e000/ End thread
01.562: |7f671000| config_usb: 0x7f675450
01.562: |7f671000| ehci_control 0x7f675450 (dir=128 cmd=8 data=8)
01.562: |7f674000| Got ps2 nak (status=51)
01.562: |7f674000| ps2 command 2ff failed (aux=0)
01.562: |7f677000| UHCI init on dev 00:1d.3 (io=5060)
01.562: /7f66e000\ Start thread
01.562: /7f66c000\ Start thread
01.563: \7f66c000/ End thread
01.562: /7f66c000\ Start thread
01.562: \7f66c000/ End thread
01.563: \7f672000/ End thread
01.563: |7f671000| device rev=0200 cls=09 sub=00 proto=02 size=64
01.563: |7f671000| ehci_control 0x7f675450 (dir=128 cmd=8 data=9)
01.563: \7f677000/ End thread
01.563: /7f672000\ Start thread
01.563: \7f672000/ End thread
01.563: \7f670000/ End thread
01.563: |7f671000| ehci_control 0x7f675450 (dir=128 cmd=8 data=41)
01.563: \7f66f000/ End thread
01.563: |7f671000| ehci_control 0x7f675450 (dir=0 cmd=8 data=0)
01.563: |7f674000| Got ps2 nak (status=51)
01.563: |7f674000| ps2 command 2ff failed (aux=0)
01.563: \7f66e000/ End thread
01.563: |7f671000| ehci_control 0x7f675450 (dir=128 cmd=8 data=7)
01.563: /7f672000\ Start thread
01.563: |7f672000| ehci_control 0x7f675450 (dir=0 cmd=8 data=0)
01.564: /7f670000\ Start thread
01.564: |7f674000| Got ps2 nak (status=51)
01.564: |7f674000| ps2 command 2ff failed (aux=0)
01.564: /7f66f000\ Start thread
01.564: |7f66f000| ehci_control 0x7f675450 (dir=0 cmd=8 data=0)
01.564: /7f66e000\ Start thread
01.564: |7f670000| ehci_control 0x7f675450 (dir=0 cmd=8 data=0)
01.565: |7f66e000| ehci_control 0x7f675450 (dir=0 cmd=8 data=0)
01.565: |7f674000| Got ps2 nak (status=51)
01.565: |7f674000| ps2 command 2ff failed (aux=0)
01.566: |7f674000| Got ps2 nak (status=51)
01.567: |7f674000| ps2 command 2ff failed (aux=0)
01.569: |7f674000| Got ps2 nak (status=51)
01.569: |7f674000| ps2 command 2ff failed (aux=0)
01.572: |7f674000| Got ps2 nak (status=51)
01.572: |7f674000| ps2 command 2ff failed (aux=0)
01.574: |7f674000| Got ps2 nak (status=51)
01.574: |7f674000| ps2 command 2ff failed (aux=0)
01.576: |7f674000| Got ps2 nak (status=51)
01.576: |7f674000| ps2 command 2ff failed (aux=0)
01.577: |7f674000| Got ps2 nak (status=51)
01.578: |7f674000| ps2 command 2ff failed (aux=0)
01.580: |7f674000| Got ps2 nak (status=51)
01.580: |7f674000| ps2 command 2ff failed (aux=0)
01.582: |7f674000| Got ps2 nak (status=51)
01.583: |7f674000| ps2 command 2ff failed (aux=0)
01.583: |7f672000| ehci_control 0x7f675450 (dir=128 cmd=8 data=4)
01.584: |7f674000| Got ps2 nak (status=51)
01.585: |7f674000| ps2 command 2ff failed (aux=0)
01.585: |7f66f000| ehci_control 0x7f675450 (dir=128 cmd=8 data=4)
01.586: |7f670000| ehci_control 0x7f675450 (dir=128 cmd=8 data=4)
01.586: |7f672000| ehci_control 0x7f675450 (dir=128 cmd=8 data=4)
01.586: |7f674000| Got ps2 nak (status=51)
01.586: |7f674000| ps2 command 2ff failed (aux=0)
01.586: |7f66e000| ehci_control 0x7f675450 (dir=128 cmd=8 data=4)
01.587: |7f66f000| ehci_control 0x7f675450 (dir=128 cmd=8 data=4)
01.587: |7f674000| Got ps2 nak (status=51)
01.587: |7f674000| ps2 command 2ff failed (aux=0)
01.587: |7f670000| ehci_control 0x7f675450 (dir=128 cmd=8 data=4)
01.587: |7f672000| ehci_control 0x7f675450 (dir=128 cmd=8 data=4)
01.588: |7f66e000| ehci_control 0x7f675450 (dir=128 cmd=8 data=4)
01.588: |7f674000| Got ps2 nak (status=51)
01.588: |7f674000| ps2 command 2ff failed (aux=0)
01.588: |7f66f000| ehci_control 0x7f675450 (dir=128 cmd=8 data=4)
01.588: |7f670000| ehci_control 0x7f675450 (dir=128 cmd=8 data=4)
01.588: |7f672000| ehci_control 0x7f675450 (dir=128 cmd=8 data=4)
01.588: |7f674000| Got ps2 nak (status=51)
01.589: |7f674000| ps2 command 2ff failed (aux=0)
01.589: \7f672000/ End thread
01.589: |7f66e000| ehci_control 0x7f675450 (dir=128 cmd=8 data=4)
01.589: |7f66f000| ehci_control 0x7f675450 (dir=128 cmd=8 data=4)
01.589: |7f674000| Got ps2 nak (status=51)
01.589: |7f674000| ps2 command 2ff failed (aux=0)
01.589: \7f66f000/ End thread
01.589: |7f670000| ehci_control 0x7f675450 (dir=128 cmd=8 data=4)
01.589: \7f670000/ End thread
01.589: |7f66e000| ehci_control 0x7f675450 (dir=128 cmd=8 data=4)
01.590: |7f674000| Got ps2 nak (status=51)
01.590: |7f674000| ps2 command 2ff failed (aux=0)
01.590: \7f66e000/ End thread
01.590: |7f671000| Initialized USB HUB (0 ports used)
01.590: \7f671000/ End thread
01.590: |7f674000| Got ps2 nak (status=51)
01.591: |7f674000| ps2 command 2ff failed (aux=0)
01.591: \7f676000/ End thread
01.593: |7f674000| Got ps2 nak (status=51)
01.594: |7f674000| ps2 command 2ff failed (aux=0)
01.596: |7f674000| Got ps2 nak (status=51)
01.596: |7f674000| ps2 command 2ff failed (aux=0)
01.599: |7f674000| Got ps2 nak (status=51)
01.600: |7f674000| ps2 command 2ff failed (aux=0)
01.602: |7f674000| Got ps2 nak (status=51)
01.602: |7f674000| ps2 command 2ff failed (aux=0)
01.605: |7f674000| Got ps2 nak (status=51)
01.605: |7f674000| ps2 command 2ff failed (aux=0)
01.609: |7f674000| Got ps2 nak (status=51)
01.609: |7f674000| ps2 command 2ff failed (aux=0)
01.610: |7f674000| Got ps2 nak (status=51)
01.611: |7f674000| ps2 command 2ff failed (aux=0)
01.614: |7f674000| Got ps2 nak (status=51)
01.614: |7f674000| ps2 command 2ff failed (aux=0)
01.616: |7f674000| Got ps2 nak (status=51)
01.617: |7f674000| ps2 command 2ff failed (aux=0)
01.619: |7f674000| Got ps2 nak (status=51)
01.620: |7f674000| ps2 command 2ff failed (aux=0)
01.622: |7f674000| Got ps2 nak (status=51)
01.623: |7f674000| ps2 command 2ff failed (aux=0)
01.625: |7f674000| Got ps2 nak (status=51)
01.626: |7f674000| ps2 command 2ff failed (aux=0)
01.628: |7f674000| Got ps2 nak (status=51)
01.629: |7f674000| ps2 command 2ff failed (aux=0)
01.632: |7f674000| Got ps2 nak (status=51)
01.632: |7f674000| ps2 command 2ff failed (aux=0)
01.636: |7f674000| Got ps2 nak (status=51)
01.637: |7f674000| ps2 command 2ff failed (aux=0)
01.639: |7f674000| Got ps2 nak (status=51)
01.639: |7f674000| ps2 command 2ff failed (aux=0)
01.640: |7f674000| Got ps2 nak (status=51)
01.641: |7f674000| ps2 command 2ff failed (aux=0)
01.643: |7f674000| Got ps2 nak (status=51)
01.643: |7f674000| ps2 command 2ff failed (aux=0)
01.645: |7f674000| Got ps2 nak (status=51)
01.646: |7f674000| ps2 command 2ff failed (aux=0)
01.648: |7f674000| Got ps2 nak (status=51)
01.649: |7f674000| ps2 command 2ff failed (aux=0)
01.652: |7f674000| Got ps2 nak (status=51)
01.652: |7f674000| ps2 command 2ff failed (aux=0)
01.654: |7f674000| Got ps2 nak (status=51)
01.654: |7f674000| ps2 command 2ff failed (aux=0)
01.656: |7f674000| Got ps2 nak (status=51)
01.656: |7f674000| ps2 command 2ff failed (aux=0)
01.658: |7f674000| Got ps2 nak (status=51)
01.659: |7f674000| ps2 command 2ff failed (aux=0)
01.661: |7f674000| Got ps2 nak (status=51)
01.663: |7f674000| ps2 command 2ff failed (aux=0)
01.663: |7f674000| Got ps2 nak (status=51)
01.664: |7f674000| ps2 command 2ff failed (aux=0)
01.665: |7f674000| Got ps2 nak (status=51)
01.666: |7f674000| ps2 command 2ff failed (aux=0)
01.668: |7f674000| Got ps2 nak (status=51)
01.669: |7f674000| ps2 command 2ff failed (aux=0)
01.670: |7f674000| Got ps2 nak (status=51)
01.670: |7f674000| ps2 command 2ff failed (aux=0)
01.672: |7f674000| Got ps2 nak (status=51)
01.672: |7f674000| ps2 command 2ff failed (aux=0)
01.675: |7f674000| Got ps2 nak (status=51)
01.675: |7f674000| ps2 command 2ff failed (aux=0)
01.676: |7f674000| Got ps2 nak (status=51)
01.677: |7f674000| ps2 command 2ff failed (aux=0)
01.679: |7f674000| Got ps2 nak (status=51)
01.679: |7f674000| ps2 command 2ff failed (aux=0)
01.680: |7f674000| Got ps2 nak (status=51)
01.682: |7f674000| ps2 command 2ff failed (aux=0)
01.682: |7f674000| Got ps2 nak (status=51)
01.683: |7f674000| ps2 command 2ff failed (aux=0)
01.686: |7f674000| Got ps2 nak (status=51)
01.686: |7f674000| ps2 command 2ff failed (aux=0)
01.687: |7f674000| Got ps2 nak (status=51)
01.688: |7f674000| ps2 command 2ff failed (aux=0)
01.690: |7f674000| Got ps2 nak (status=51)
01.691: |7f674000| ps2 command 2ff failed (aux=0)
01.692: |7f674000| Got ps2 nak (status=51)
01.693: |7f674000| ps2 command 2ff failed (aux=0)
01.694: |7f674000| Got ps2 nak (status=51)
01.695: |7f674000| ps2 command 2ff failed (aux=0)
01.696: |7f674000| Got ps2 nak (status=51)
01.697: |7f674000| ps2 command 2ff failed (aux=0)
01.699: |7f674000| Got ps2 nak (status=51)
01.699: |7f674000| ps2 command 2ff failed (aux=0)
01.701: |7f674000| Got ps2 nak (status=51)
01.701: |7f674000| ps2 command 2ff failed (aux=0)
01.704: |7f674000| Got ps2 nak (status=51)
01.704: |7f674000| ps2 command 2ff failed (aux=0)
01.706: |7f674000| Got ps2 nak (status=51)
01.707: |7f674000| ps2 command 2ff failed (aux=0)
01.708: |7f674000| Got ps2 nak (status=51)
01.709: |7f674000| ps2 command 2ff failed (aux=0)
01.710: |7f674000| Got ps2 nak (status=51)
01.711: |7f674000| ps2 command 2ff failed (aux=0)
01.712: |7f674000| Got ps2 nak (status=51)
01.713: |7f674000| ps2 command 2ff failed (aux=0)
01.716: |7f674000| Got ps2 nak (status=51)
01.716: |7f674000| ps2 command 2ff failed (aux=0)
01.718: |7f674000| Got ps2 nak (status=51)
01.719: |7f674000| ps2 command 2ff failed (aux=0)
01.720: |7f674000| Got ps2 nak (status=51)
01.720: |7f674000| ps2 command 2ff failed (aux=0)
01.722: |7f674000| Discarding ps2 data aa (status=11)
02.335: |7f674000| PS2 keyboard initialized
02.335: \7f674000/ End thread
32.705: |7f673000| WARNING - Timeout at ahci_port_setup:466!
32.705: |7f673000| AHCI/0: device not ready (tf 0x80)
33.205: |7f673000| WARNING - Timeout at ahci_port_reset:336!
33.205: \7f673000/ End thread
33.206: All threads complete.
33.205: Scan for option roms
33.206: Attempting to init PCI bdf 00:00.0 (vd 8086:27a0)
33.206: Attempting to init PCI bdf 00:02.1 (vd 8086:27a6)
33.205: Attempting to init PCI bdf 00:1b.0 (vd 8086:27d8)
33.206: Attempting to init PCI bdf 00:1c.0 (vd 8086:27d0)
33.206: Attempting to init PCI bdf 00:1c.1 (vd 8086:27d2)
33.205: Attempting to init PCI bdf 00:1c.2 (vd 8086:27d4)
33.206: Attempting to init PCI bdf 00:1c.3 (vd 8086:27d6)
33.206: Attempting to init PCI bdf 00:1d.0 (vd 8086:27c8)
33.206: Attempting to init PCI bdf 00:1d.1 (vd 8086:27c9)
33.206: Attempting to init PCI bdf 00:1d.2 (vd 8086:27ca)
33.206: Attempting to init PCI bdf 00:1d.3 (vd 8086:27cb)
33.206: Attempting to init PCI bdf 00:1d.7 (vd 8086:27cc)
33.205: Attempting to init PCI bdf 00:1e.0 (vd 8086:2448)
33.205: Attempting to init PCI bdf 00:1f.0 (vd 8086:27b9)
33.206: Attempting to init PCI bdf 00:1f.2 (vd 8086:27c5)
33.206: Attempting to init PCI bdf 00:1f.3 (vd 8086:27da)
33.205: Attempting to init PCI bdf 01:00.0 (vd 8086:109a)
33.205: Attempting to init PCI bdf 02:00.0 (vd 8086:4227)
33.205: Attempting to init PCI bdf 05:00.0 (vd 1180:0476)
33.206: Attempting to init PCI bdf 05:00.1 (vd 1180:0552)
33.206: Attempting to init PCI bdf 05:00.2 (vd 1180:0822)
33.206: 
33.206: Press F12 for boot menu.
33.206: 
33.206: Checking for bootsplash
35.774: Searching bootorder for: HALT
35.774: Mapping cd drive 0x000f16b0
35.774: finalize PMM
35.774: malloc finalize
35.775: Space available for UMB: cf000-ee800, f0000-f1680
35.775: Returned 262144 bytes of ZoneHigh
35.775: e820 map has 6 items:
35.775:   0: 0000000000000000 - 000000000009fc00 = 1 RAM
35.774:   1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
35.774:   2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
35.775:   3: 0000000000100000 - 000000007f6c4000 = 1 RAM
35.774:   4: 000000007f6c4000 - 0000000080000000 = 2 RESERVED
35.774:   5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
35.775: Jump to int19
35.775: enter handle_19:
35.775:   NULL
35.776: Booting from DVD/CD...
35.777: Device reports MEDIUM NOT PRESENT
35.777: scsi_is_ready returned -1
35.777: Boot failed: Could not read from CDROM (code 0003)
35.777: enter handle_18:
35.777:   NULL
35.777: Booting from Floppy...
35.777: invalid handle_legacy_disk:696:
35.777:    a=00000201  b=00000000  c=00000001  d=00000000 ds=0000 es=07c0 ss=e000
35.777:   si=00000000 di=00000000 bp=00000000 sp=0000ffe8 cs=f000 ip=d066  f=0202
35.777: Boot failed: could not read the boot disk
35.777: 
35.777: enter handle_18:
35.777:   NULL
35.777: Booting from Hard Disk...
35.777: invalid handle_legacy_disk:696:
35.778:    a=00000201  b=00000000  c=00000001  d=00000080 ds=0000 es=07c0 ss=e000
35.777:   si=00000000 di=00000000 bp=00000000 sp=0000ffe8 cs=f000 ip=d066  f=0202
35.777: Boot failed: could not read the boot disk
35.777: 
35.777: enter handle_18:
35.777:   NULL
35.777: No bootable device.  Retrying in 60 seconds.
41.647: In resume (status=0)
41.647: In 32bit resume
41.647: Attempting a hard reboot
41.873: <00>
42.313: <00>
43.046: Changing serial settings was 0/0 now 3/0
43.046: SeaBIOS (version rel-1.7.5-40-g5109366-20140715_011246-my-lenovo-x60t)
43.046: Attempting to find coreboot table
43.046: Found coreboot table forwarder.
43.046: Now attempting to find coreboot memory map
43.047: SeaBIOS (version rel-1.7.5-40-g5109366-20140715_011246-my-lenovo-x60t)
43.046: Found coreboot cbmem console  <at>  7f7de000
43.046: Found mainboard Lenovo ThinkPad X60 / X60s
43.047: malloc preinit
43.047: Relocating init from 0x000e6c20 to 0x7f679220 (size 44320)
43.046: malloc init
43.047: Found CBFS header at 0xfffffa50
43.046: Add romfile: cmos_layout.bin (size=1828)
43.047: Add romfile: pci8086,27a2.rom (size=65536)
43.046: Add romfile: cmos.default (size=256)
43.046: Add romfile: cpu_microcode_blob.bin (size=94208)
43.047: Add romfile: etc/ps2-keyboard-spinup (size=8)
43.047: Add romfile: config (size=4221)
43.047: Add romfile:  (size=29976)
43.047: Add romfile: fallback/romstage (size=50939)
43.047: Add romfile: fallback/ramstage (size=68308)
43.047: Add romfile: fallback/payload (size=55644)
43.047: Add romfile:  (size=1723928)
43.048: init ivt
43.048: init bda
43.047: init bios32
43.047: init PMM
43.047: init PNPBIOS table
43.047: init keyboard
43.047: init mouse
43.047: init pic
43.047: math cp init
43.048: CPU Mhz=1664
43.049: init timer
43.049: PCI probe
43.049: PCI device 00:00.0 (vd=8086:27a0 c=0600)
43.049: PCI device 00:02.0 (vd=8086:27a2 c=0300)
43.049: PCI device 00:02.1 (vd=8086:27a6 c=0380)
43.049: PCI device 00:1b.0 (vd=8086:27d8 c=0403)
43.049: PCI device 00:1c.0 (vd=8086:27d0 c=0604)
43.049: PCI device 00:1c.1 (vd=8086:27d2 c=0604)
43.049: PCI device 00:1c.2 (vd=8086:27d4 c=0604)
43.049: PCI device 00:1c.3 (vd=8086:27d6 c=0604)
43.049: PCI device 00:1d.0 (vd=8086:27c8 c=0c03)
43.049: PCI device 00:1d.1 (vd=8086:27c9 c=0c03)
43.049: PCI device 00:1d.2 (vd=8086:27ca c=0c03)
43.049: PCI device 00:1d.3 (vd=8086:27cb c=0c03)
43.049: PCI device 00:1d.7 (vd=8086:27cc c=0c03)
43.049: PCI device 00:1e.0 (vd=8086:2448 c=0604)
43.049: PCI device 00:1f.0 (vd=8086:27b9 c=0601)
43.049: PCI device 00:1f.1 (vd=8086:27df c=0101)
43.049: PCI device 00:1f.2 (vd=8086:27c5 c=0106)
43.049: PCI device 00:1f.3 (vd=8086:27da c=0c05)
43.049: PCI device 01:00.0 (vd=8086:109a c=0200)
43.049: PCI device 02:00.0 (vd=8086:4227 c=0280)
43.049: PCI device 05:00.0 (vd=1180:0476 c=0607)
43.050: PCI device 05:00.1 (vd=1180:0552 c=0c00)
43.049: PCI device 05:00.2 (vd=1180:0822 c=0805)
43.050: Found 23 PCI devices (max PCI bus is 06)
43.050: Relocating coreboot bios tables
43.051: Copying SMBIOS entry point from 0x7f7cc000 to 0x000f1920
43.051: Copying ACPI RSDP from 0x7f7cd000 to 0x000f18f0
43.051: Copying MPTABLE from 0x7f7d9000/7f7d9010 to 0x000f1720
43.051: rsdp=0x000f18f0
43.051: rsdt=0x7f7cd030
43.051: fadt=0x7f7d0510
43.051: pm_tmr_blk=508
43.051: Using pmtimer, ioport 0x508
43.051: Scan for VGA option rom
43.052: Attempting to init PCI bdf 00:02.0 (vd 8086:27a2)
43.051: Copying data 65536 <at> 0xffe007b8 to 65536 <at> 0x000c0000
43.084: Running option rom at c000:0003
43.132: unimplemented handle_155fXX:26:
43.132:    a=80005f34  b=0000078f  c=00000002  d=00000002 ds=0000 es=c000 ss=e000
43.132:   si=00000994 di=00000080 bp=50a06e0c sp=0000ffe8 cs=c000 ip=4a6e  f=0046
43.178: Turning on vga text mode console
43.210: SeaBIOS (version rel-1.7.5-40-g5109366-20140715_011246-my-lenovo-x60t)
43.211: Machine UUID c09ecb7b-2a1f-dc11-b88a-942d40962902
43.211: /7f677000\ Start thread
43.210: |7f677000| init usb
43.211: |7f677000| EHCI init on dev 00:1d.7 (regs=0xe4444020)
43.210: /7f676000\ Start thread
43.211: init ps2port
43.210: /7f674000\ Start thread
43.212: |7f674000| Copying data 8 <at> 0xffe27978 to 8 <at> 0x7f674fc8
43.211: /7f673000\ Start thread
43.212: init lpt
43.212: Found 0 lpt ports
43.212: init serial
43.212: Found 1 serial ports
43.212: init hard drives
43.212: ATA controller 1 at 1f0/3f4/0 (irq 14 dev f9)
43.212: /7f672000\ Start thread
43.212: /7f671000\ Start thread
43.212: ATA controller 2 at 170/374/0 (irq 15 dev f9)
43.213: /7f670000\ Start thread
43.213: |7f670000| powerup IDE floating
43.212: |7f670000| powerup IDE floating
43.212: |7f670000| powerup IDE floating
43.212: |7f670000| powerup IDE floating
43.212: \7f670000/ End thread
43.212: /7f670000\ Start thread
43.212: \7f671000/ End thread
43.212: \7f673000/ End thread
43.212: init ahci
43.212: AHCI controller at 1f.2, iobase e4444400, irq 0
43.212: AHCI: cap 0xdf12ff03, ports_impl 0x1
43.212: /7f673000\ Start thread
43.212: |7f673000| AHCI/0: probing
43.212: /7f671000\ Start thread
43.213: \7f670000/ End thread
43.213: |7f673000| AHCI/0: link up
43.213: |7f672000| DVD/CD [ata0-0: DVD/CDRW UJDA775 ATAPI-5 DVD/CD]
43.213: |7f672000| Searching bootorder for: /pci <at> i0cf8/* <at> 1f,1/drive <at> 0/disk <at> 0
43.213: |7f672000| Registering bootable: DVD/CD [ata0-0: DVD/CDRW UJDA775 ATAPI-5 DVD/CD] (type:3
prio:102 data:f16b0)
43.213: \7f672000/ End thread
43.213: /7f672000\ Start thread
43.213: \7f671000/ End thread
43.213: |7f673000| AHCI/0: ... finished, status 0x51, ERROR 0x4
43.213: /7f671000\ Start thread
43.213: |7f673000| Searching bootorder for: /pci <at> i0cf8/* <at> 1f,2/drive <at> 0/disk <at> 0
43.213: /7f670000\ Start thread
43.213: |7f673000| AHCI/0: registering: "AHCI/0: M4-CT256M4SSD2 ATA-9 Hard-Disk (238 GiBytes)"
43.213: |7f673000| Registering bootable: AHCI/0: M4-CT256M4SSD2 ATA-9 Hard-Disk (238 GiBytes)
(type:2 prio:103 data:f1660)
43.213: \7f673000/ End thread
43.213: /7f673000\ Start thread
43.213: \7f670000/ End thread
43.213: \7f672000/ End thread
43.230: \7f673000/ End thread
43.261: |7f671000| set_address 0x7f678090
43.261: |7f677000| UHCI init on dev 00:1d.0 (io=5000)
43.261: /7f673000\ Start thread
43.261: /7f672000\ Start thread
43.262: \7f672000/ End thread
43.261: |7f671000| ehci_control 0x7f675bd0 (dir=0 cmd=8 data=0)
43.261: |7f677000| UHCI init on dev 00:1d.1 (io=5020)
43.262: /7f672000\ Start thread
43.261: /7f670000\ Start thread
43.261: \7f670000/ End thread
43.262: /7f670000\ Start thread
43.261: \7f670000/ End thread
43.261: |7f677000| UHCI init on dev 00:1d.2 (io=5040)
43.262: /7f670000\ Start thread
43.262: /7f66f000\ Start thread
43.262: \7f66f000/ End thread
43.262: /7f66f000\ Start thread
43.262: \7f66f000/ End thread
43.262: |7f671000| config_usb: 0x7f675bd0
43.262: |7f671000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=8)
43.262: |7f677000| UHCI init on dev 00:1d.3 (io=5060)
43.261: /7f66f000\ Start thread
43.262: /7f66e000\ Start thread
43.262: \7f66e000/ End thread
43.262: /7f66e000\ Start thread
43.262: \7f66e000/ End thread
43.262: \7f673000/ End thread
43.262: |7f671000| device rev=0200 cls=09 sub=00 proto=02 size=64
43.262: |7f671000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=9)
43.262: \7f677000/ End thread
43.262: /7f673000\ Start thread
43.262: \7f673000/ End thread
43.262: \7f672000/ End thread
43.262: |7f671000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=41)
43.262: \7f670000/ End thread
43.262: |7f671000| ehci_control 0x7f675bd0 (dir=0 cmd=8 data=0)
43.262: \7f66f000/ End thread
43.262: |7f671000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=7)
43.262: /7f673000\ Start thread
43.262: |7f673000| ehci_control 0x7f675bd0 (dir=0 cmd=8 data=0)
43.262: /7f672000\ Start thread
43.262: /7f670000\ Start thread
43.262: |7f670000| ehci_control 0x7f675bd0 (dir=0 cmd=8 data=0)
43.262: /7f66f000\ Start thread
43.262: |7f672000| ehci_control 0x7f675bd0 (dir=0 cmd=8 data=0)
43.262: |7f66f000| ehci_control 0x7f675bd0 (dir=0 cmd=8 data=0)
43.343: |7f673000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.347: |7f670000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.348: |7f672000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.347: |7f673000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.347: |7f66f000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.347: |7f670000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.347: |7f672000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.347: |7f673000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.348: |7f66f000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.348: |7f670000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.348: |7f672000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.348: |7f673000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.348: |7f66f000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.348: |7f670000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.348: |7f672000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.348: |7f673000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.348: |7f66f000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.348: |7f670000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.348: |7f672000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.348: |7f673000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.348: \7f673000/ End thread
43.348: |7f66f000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.348: |7f670000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.348: \7f670000/ End thread
43.348: |7f672000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.351: \7f672000/ End thread
43.349: |7f66f000| ehci_control 0x7f675bd0 (dir=128 cmd=8 data=4)
43.349: \7f66f000/ End thread
43.349: |7f671000| Initialized USB HUB (0 ports used)
43.348: \7f671000/ End thread
43.352: \7f676000/ End thread
43.501: |7f674000| PS2 keyboard initialized
43.501: \7f674000/ End thread
43.501: All threads complete.
43.501: Scan for option roms
43.501: Attempting to init PCI bdf 00:00.0 (vd 8086:27a0)
43.501: Attempting to init PCI bdf 00:02.1 (vd 8086:27a6)
43.501: Attempting to init PCI bdf 00:1b.0 (vd 8086:27d8)
43.501: Attempting to init PCI bdf 00:1c.0 (vd 8086:27d0)
43.501: Attempting to init PCI bdf 00:1c.1 (vd 8086:27d2)
43.501: Attempting to init PCI bdf 00:1c.2 (vd 8086:27d4)
43.502: Attempting to init PCI bdf 00:1c.3 (vd 8086:27d6)
43.501: Attempting to init PCI bdf 00:1d.0 (vd 8086:27c8)
43.501: Attempting to init PCI bdf 00:1d.1 (vd 8086:27c9)
43.501: Attempting to init PCI bdf 00:1d.2 (vd 8086:27ca)
43.501: Attempting to init PCI bdf 00:1d.3 (vd 8086:27cb)
43.501: Attempting to init PCI bdf 00:1d.7 (vd 8086:27cc)
43.501: Attempting to init PCI bdf 00:1e.0 (vd 8086:2448)
43.501: Attempting to init PCI bdf 00:1f.0 (vd 8086:27b9)
43.501: Attempting to init PCI bdf 00:1f.2 (vd 8086:27c5)
43.501: Attempting to init PCI bdf 00:1f.3 (vd 8086:27da)
43.501: Attempting to init PCI bdf 01:00.0 (vd 8086:109a)
43.501: Attempting to init PCI bdf 02:00.0 (vd 8086:4227)
43.501: Attempting to init PCI bdf 05:00.0 (vd 1180:0476)
43.501: Attempting to init PCI bdf 05:00.1 (vd 1180:0552)
43.502: Attempting to init PCI bdf 05:00.2 (vd 1180:0822)
43.501: 
43.501: Press F12 for boot menu.
43.502: 
43.502: Checking for bootsplash
46.035: Searching bootorder for: HALT
46.045: Mapping cd drive 0x000f16b0
46.045: Mapping hd drive 0x000f1660 to 0
46.045: drive 0x000f1660: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=500118192
46.045: finalize PMM
46.045: malloc finalize
46.045: Space available for UMB: cf000-ee800, f0000-f1630
46.045: Returned 253952 bytes of ZoneHigh
46.045: e820 map has 6 items:
46.045:   0: 0000000000000000 - 000000000009fc00 = 1 RAM
46.045:   1: 000000000009fc00 - 00000000000a0000 = 2 RESERVED
46.045:   2: 00000000000f0000 - 0000000000100000 = 2 RESERVED
46.045:   3: 0000000000100000 - 000000007f6c2000 = 1 RAM
46.045:   4: 000000007f6c2000 - 0000000080000000 = 2 RESERVED
46.045:   5: 00000000f0000000 - 00000000f4000000 = 2 RESERVED
46.045: Jump to int19
46.045: enter handle_19:
46.045:   NULL
46.045: Booting from DVD/CD...
46.045: Device reports MEDIUM NOT PRESENT
46.045: scsi_is_ready returned -1
46.045: Boot failed: Could not read from CDROM (code 0003)
46.045: enter handle_18:
46.045:   NULL
46.045: Booting from Hard Disk...
46.045: Booting from 0000:7c00
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Mohan | 11 Sep 09:34 2014
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MinnowMax: Tentative patch for S3 suspend/resume support

Hi,

This is a tentative patch for S3 suspend/resume support in MinnowMax Board.

It is based on the "src/soc/intel/baytrail/romstage/romstage.c" 
implementation.

Tested wakeup from Power Button and Magic packet using Debian Jessie RFS
and grub2.elf as coreboot payload.

S3 suspend/resume require Fast boot to be enabled.  (please correct me 
if i am mistaken)

Comments, suggestion, corrections are welcome.
I would like to get it added it, can anyone help me ?

Regards,
Mohan

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unb able | 10 Sep 19:27 2014
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Need help buying laptop with AMD CPU

Hi guys,
I am planning to buy a laptop and want to run coreboot on it.  I have basic information regarding the CPU and chipset in these laptops.  I will be greatful if someone can let me know which of these CPU+chipset combo has the potential to be best supported by coreboot:

(1) AMD A6 4400M Dual Core 2.7GHz + A70M chipset
(2) AMD A8 4500M Quad Core 2.1 GHz + A70M chipset
(3) AMD A8-5545M Quad Core 1.7 GHz + A76M FCH
(4) AMD A6-5200 Quad Core 2.0 GHz + A68M chipset

I believe (1) and (2) should be supported but am not 100% sure.

Is there any possibility of running coreboot on motherboards with newer 6000 series AMD CPUs?

Thanks in advance,
Vick
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Luigi Bai | 9 Sep 20:52 2014
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Picon

Unsupported hardware - information listed

Per the wiki, I am offering this information to try to determine the
status of coreboot support, especially for Intel/PM965 or Intel/82801H.
I didn't see either under the lists of supported hardware.

Dell Latitude D830
Apparently no Super I/O

DMI string system-manufacturer: "Dell Inc."
DMI string system-product-name: "Latitude D830                   "
DMI string system-version: "Not Specified"
DMI string baseboard-manufacturer: "Dell Inc."
DMI string baseboard-product-name: "0HN341"
DMI string baseboard-version: "   "
DMI string chassis-type: "Portable"
Laptop detected via DMI

processor	: 0
vendor_id	: GenuineIntel
cpu family	: 6
model		: 15
model name	: Intel(R) Core(TM)2 Duo CPU     T7250   <at>  2.00GHz
stepping	: 13
microcode	: 0xa1
cpu MHz		: 2001.000
cache size	: 2048 KB
physical id	: 0
siblings	: 2
core id		: 0
cpu cores	: 2
apicid		: 0
initial apicid	: 0
fpu		: yes
fpu_exception	: yes
cpuid level	: 10
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov
pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm
constant_tsc arch_perfmon pebs bts rep_good nopl aperfmperf pni dtes64
monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm lahf_lm ida dtherm
tpr_shadow vnmi flexpriority
bogomips	: 3990.08
clflush size	: 64
cache_alignment	: 64
address sizes	: 36 bits physical, 48 bits virtual
power management:

-[0000:00]-+-00.0  Intel Corporation Mobile PM965/GM965/GL960 Memory
Controller Hub [8086:2a00]
           +-02.0  Intel Corporation Mobile GM965/GL960 Integrated
Graphics Controller [8086:2a02]
           +-02.1  Intel Corporation Mobile GM965/GL960 Integrated
Graphics Controller [8086:2a03]
           +-1a.0  Intel Corporation 82801H (ICH8 Family) USB UHCI
Controller #4 [8086:2834]
           +-1a.1  Intel Corporation 82801H (ICH8 Family) USB UHCI
Controller #5 [8086:2835]
           +-1a.7  Intel Corporation 82801H (ICH8 Family) USB2 EHCI
Controller #2 [8086:283a]
           +-1b.0  Intel Corporation 82801H (ICH8 Family) HD Audio
Controller [8086:284b]
           +-1c.0-[0b]--
           +-1c.1-[0c]----00.0  Intel Corporation PRO/Wireless 3945ABG
[Golan] Network Connection [8086:4222]
           +-1c.3-[0d-0e]--
           +-1c.5-[09]----00.0  Broadcom Corporation NetXtreme BCM5755M
Gigabit Ethernet PCI Express [14e4:1673]
           +-1d.0  Intel Corporation 82801H (ICH8 Family) USB UHCI
Controller #1 [8086:2830]
           +-1d.1  Intel Corporation 82801H (ICH8 Family) USB UHCI
Controller #2 [8086:2831]
           +-1d.2  Intel Corporation 82801H (ICH8 Family) USB UHCI
Controller #3 [8086:2832]
           +-1d.7  Intel Corporation 82801H (ICH8 Family) USB2 EHCI
Controller #1 [8086:2836]
           +-1e.0-[03-07]--+-01.0  O2 Micro, Inc. Cardbus bridge [1217:7135]
           |               \-01.4  O2 Micro, Inc. Firewire (IEEE 1394)
[1217:00f7]
           +-1f.0  Intel Corporation 82801HEM (ICH8M) LPC Interface
Controller [8086:2815]
           +-1f.1  Intel Corporation 82801HBM/HEM (ICH8M/ICH8M-E) IDE
Controller [8086:2850]
           +-1f.2  Intel Corporation 82801HBM/HEM (ICH8M/ICH8M-E) SATA
IDE Controller [8086:2828]
           \-1f.3  Intel Corporation 82801H (ICH8 Family) SMBus
Controller [8086:283e]

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sanjeev chauhan | 8 Sep 18:49 2014
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AMD R-series APU based boards

Hi all,
I am wondering if there are any AMD R-series APU (not SoC) based
boards supported by coreboot.  I know some AMD G-series APU based
boards are supported but am specifically interested in R-series APUs
because of their higher processing power.

Thanks,

sanjeev

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Gmane