Share my code of running vgabios(in CBFS) in seabios when rusume from s3.

Hi Rudolf	,
I work out some code to make seabios run vgabios when resuming from S3
(follow your advice on IRC, again :) ). And it is unbelievable easy,
only 2 step:

Setp 1: In acpi.c

void acpi_jump_to_wakeup(void *vector)
{
	/* just restore the SMP trampoline and continue with wakeup on
assembly level */
	memcpy(lowmem_backup_ptr, lowmem_backup, lowmem_backup_size);
-//	acpi_jmp_to_realm_wakeup((u32) vector);

//	seabios at entry_post:(in romlayout.S) will check cmos[0x8f] it
as a S3 resuming flag.
+     outb(0x0f, RTC_BASE_PORT + 0); 
+     outb(0xfe, RTC_BASE_PORT + 1);  

+	//these two lines has same effect with the above two lines, and
I don know 8f or 0f which is better. cmos_read/write in coreboot do not
set bit 7.
+//	outb(0x8f, RTC_BASE_PORT + 0);  
+//	outb(0xfe, RTC_BASE_PORT + 1);  
+	acpi_jmp_to_realm_wakeup(0xffff0); 
}

Step 2: in seabios->resume.c->s3_resume()
    smm_init();
+   vga_setup();

Re: [v2] r4394 - in trunk/coreboot-v2/src: cpu/amd/sc520cpu/emulation/qemu-x86 cpu/ppc/ppc4xx devices include/devicenorthbridge/amd/amdfam10 northbridge/amd/amdk8northbridge/amd/gx1 northbridge/amd/gx2 northbridge/amd/lxnorthbridge/ibm/cpc710 n

This patch makes my AMD fam10 board not work (K8 works). The resource
can not be allocated correctly.


Zheng

-----Original Message-----
From: coreboot-bounces <at> coreboot.org
[mailto:coreboot-bounces <at> coreboot.org] On Behalf Of svn <at> coreboot.org
Sent: Friday, July 03, 2009 2:56 AM
To: coreboot <at> coreboot.org
Subject: [coreboot] [v2] r4394 - in trunk/coreboot-v2/src:
cpu/amd/sc520cpu/emulation/qemu-x86 cpu/ppc/ppc4xx devices
include/devicenorthbridge/amd/amdfam10
northbridge/amd/amdk8northbridge/amd/gx1 northbridge/amd/gx2
northbridge/amd/lxnorthbridge/ibm/cpc710 north

Author: myles
Date: 2009-07-02 20:56:24 +0200 (Thu, 02 Jul 2009)
New Revision: 4394

Modified:
   trunk/coreboot-v2/src/cpu/amd/sc520/sc520.c
   trunk/coreboot-v2/src/cpu/emulation/qemu-x86/northbridge.c
   trunk/coreboot-v2/src/cpu/ppc/ppc4xx/pci_domain.c
   trunk/coreboot-v2/src/devices/cardbus_device.c
   trunk/coreboot-v2/src/devices/device.c
   trunk/coreboot-v2/src/devices/device_util.c
   trunk/coreboot-v2/src/devices/pci_device.c
   trunk/coreboot-v2/src/devices/root_device.c

Support for Asus A8M2N-LA ?

I've got a HP Pavilion desktop that has an ASUS OEM motherboard model A8M2N-LA.
Manufacturer details are here (there is a nice schematic):
http://tr.im/qHw7

It appears to have an MCP51 southbridge, ASUS A8000 SuperIO, a "GeForce 6150 LE"
northbridge, Pm49FL004 flash, and also has a Nvidia C51PVG chip on it. I have no
idea what that last chip is, but I saw some references to it in an earlier
thread here http://tr.im/qHvZ .

I don't see the MCP51 listed in the supported southbridges, but then I saw some
reference to mcp51_early_setup_car.c in this thread http://tr.im/qHr8 so maybe
some headway has been made?

I'm really interested in getting the memory hole enabled so I can actually use
all my memory... Would that be possible with coreboot?

Here's outputs as requested in the faq:
 lspci -tvnn
-[0000:00]-+-00.0  nVidia Corporation C51 Host Bridge [10de:02f0]
           +-00.1  nVidia Corporation C51 Memory Controller 0 [10de:02fa]
           +-00.2  nVidia Corporation C51 Memory Controller 1 [10de:02fe]
           +-00.3  nVidia Corporation C51 Memory Controller 5 [10de:02f8]
           +-00.4  nVidia Corporation C51 Memory Controller 4 [10de:02f9]
           +-00.5  nVidia Corporation C51 Host Bridge [10de:02ff]
           +-00.6  nVidia Corporation C51 Memory Controller 3 [10de:027f]
           +-00.7  nVidia Corporation C51 Memory Controller 2 [10de:027e]
           +-02.0-[0000:01]--
           +-04.0-[0000:02]--
           +-05.0  nVidia Corporation C51 [GeForce 6150 LE] [10de:0241]
           +-09.0  nVidia Corporation MCP51 Host Bridge [10de:0270]

pci_rawops.h from vx800 tree

This file has been sanitized for your safety.

-Bari

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build service results for r4397

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "myles" checked in revision 4397 to
the coreboot repository. This caused the following 
changes:

Change Log:
Fix many things for via/epia-m700 to build.

Unfortunately it still doesn't.  I think it's close, though.

Signed-off-by: Myles Watson <mylesgw <at> gmail.com>
Acked-by: Myles Watson <mylesgw <at> gmail.com>

Build Log:
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4397&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4397&device=epia-m700&vendor=via&num=2

If something broke during this checkin please be a pain 
in myles's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system

[v2] r4397 - in trunk/coreboot-v2/src: include/device mainboard/via/epia-m700 northbridge/via/vx800 northbridge/via/vx800/examples

Author: myles
Date: 2009-07-02 23:19:33 +0200 (Thu, 02 Jul 2009)
New Revision: 4397

Modified:
   trunk/coreboot-v2/src/include/device/pci_ids.h
   trunk/coreboot-v2/src/mainboard/via/epia-m700/Config.lb
   trunk/coreboot-v2/src/mainboard/via/epia-m700/acpi_tables.c
   trunk/coreboot-v2/src/mainboard/via/epia-m700/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/via/epia-m700/driving_clk_phase_data.c
   trunk/coreboot-v2/src/mainboard/via/epia-m700/wakeup.c
   trunk/coreboot-v2/src/northbridge/via/vx800/dev_init.c
   trunk/coreboot-v2/src/northbridge/via/vx800/dram_util.c
   trunk/coreboot-v2/src/northbridge/via/vx800/examples/chipset_init.c
   trunk/coreboot-v2/src/northbridge/via/vx800/northbridge.c
   trunk/coreboot-v2/src/northbridge/via/vx800/raminit.c
   trunk/coreboot-v2/src/northbridge/via/vx800/uma_ram_setting.c
   trunk/coreboot-v2/src/northbridge/via/vx800/vga.c
   trunk/coreboot-v2/src/northbridge/via/vx800/vgabios.c
   trunk/coreboot-v2/src/northbridge/via/vx800/vx800.h
   trunk/coreboot-v2/src/northbridge/via/vx800/vx800_early_smbus.c
Log:
Fix many things for via/epia-m700 to build.

Unfortunately it still doesn't.  I think it's close, though.

Signed-off-by: Myles Watson <mylesgw <at> gmail.com>
Acked-by: Myles Watson <mylesgw <at> gmail.com>

Modified: trunk/coreboot-v2/src/include/device/pci_ids.h

build service results for r4396

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "hargut" checked in revision 4396 to
the coreboot repository. This caused the following 
changes:

Change Log:
ChangeLog:

Turn on Parallel Port and Floppy in Config.lb

Signed-off-by: Harald Gutmann <harald.gutmann <at> gmx.net>
Acked-by: Andreas B. Mundt <andi.mundt <at> web.de>

Build Log:
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4396&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4396&device=epia-m700&vendor=via&num=2

If something broke during this checkin please be a pain 
in hargut's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 
be backed out.

   Best regards,
     coreboot automatic build system

build service results for r4395

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "myles" checked in revision 4395 to
the coreboot repository. This caused the following 
changes:

Change Log:
Update the k8 code for the v3 resource allocator.
The major change is that the K8 registers don't get touched until the end of
resource allocation.

Fam10 code could be updated the same way.

Move VGA code before resource allocation but after device enumeration.

Signed-off-by: Myles Watson <mylesgw <at> gmail.com>
Acked-by: Ronald G. Minnich <rminnich <at> gmail.com>

Build Log:
Compilation of motorola:sandpointx3_altimus_mpc7410 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4395&device=sandpointx3_altimus_mpc7410&vendor=motorola&num=2
Compilation of via:epia-m700 is still broken
See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4395&device=epia-m700&vendor=via&num=2

If something broke during this checkin please be a pain 
in myles's neck until the issue is fixed.

If this issue is not fixed within 24h the revision should 

build service results for r4394

Dear coreboot readers!

This is the automatic build system of coreboot.

The developer "myles" checked in revision 4394 to
the coreboot repository. This caused the following 
changes:

Change Log:
Move the v3 resource allocator to v2.

Major changes:
1. Separate resource allocation into:
	A. Read Resources
	B. Avoid fixed resources (constrain limits)
	C. Allocate resources
	D. Set resources

Usage notes:
Resources which have IORESOURCE_FIXED set in the flags constrain the placement
of other resources.  All fixed resources will end up outside (above or below)
the allocated resources.

Domains usually start with base = 0 and limit = 2^address_bits - 1.

I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is
still there for resources.  Some platforms may want to change that, but I didn't
want to break anyone's board.

Resources are allocated in a single block for memory and another for I/O.

[v2] r4396 - trunk/coreboot-v2/src/mainboard/gigabyte/m57sli

Author: hargut
Date: 2009-07-02 21:06:01 +0200 (Thu, 02 Jul 2009)
New Revision: 4396

Modified:
   trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb
Log:
ChangeLog:

Turn on Parallel Port and Floppy in Config.lb

Signed-off-by: Harald Gutmann <harald.gutmann <at> gmx.net>
Acked-by: Andreas B. Mundt <andi.mundt <at> web.de>

Modified: trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb	2009-07-02 19:02:33 UTC (rev 4395)
+++ trunk/coreboot-v2/src/mainboard/gigabyte/m57sli/Config.lb	2009-07-02 19:06:01 UTC (rev 4396)
@@ -196,7 +196,7 @@
                 			device pci 1.0 on # LPC
 						chip superio/ite/it8716f
 							# Floppy and any LDN
-							device pnp 2e.0 off
+							device pnp 2e.0 on
                 	               			# Watchdog from CLKIN, CLKIN = 24 MHz
                 	                 			irq 0x23 = 0x11 
 							# Serial Flash (SPI only)
@@ -213,7 +213,7 @@
                 	                 			io 0x60 = 0x2f8
                 	                			irq 0x70 = 3

[v2] r4395 - in trunk/coreboot-v2/src: devices northbridge/amd/amdk8

Author: myles
Date: 2009-07-02 21:02:33 +0200 (Thu, 02 Jul 2009)
New Revision: 4395

Modified:
   trunk/coreboot-v2/src/devices/device.c
   trunk/coreboot-v2/src/northbridge/amd/amdk8/northbridge.c
Log:
Update the k8 code for the v3 resource allocator.
The major change is that the K8 registers don't get touched until the end of
resource allocation.

Fam10 code could be updated the same way.

Move VGA code before resource allocation but after device enumeration.

Signed-off-by: Myles Watson <mylesgw <at> gmail.com>
Acked-by: Ronald G. Minnich <rminnich <at> gmail.com>

Modified: trunk/coreboot-v2/src/devices/device.c
===================================================================
--- trunk/coreboot-v2/src/devices/device.c	2009-07-02 18:56:24 UTC (rev 4394)
+++ trunk/coreboot-v2/src/devices/device.c	2009-07-02 19:02:33 UTC (rev 4395)
@@ -663,9 +663,9 @@

 #if CONFIG_CONSOLE_VGA == 1
 device_t vga_pri = 0;
-static void allocate_vga_resource(void)
+static void set_vga_bridge_bits(void)
 {