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coreboot mailing list: coreboot <at>
Vladimir | 2 May 19:29 2015

Solving zilogpnz's backlight problem at Lenovo G505s

Try using vgabios of your Radeon HD 8650G ( " 1002,990b " graphic device of A10-5750M APU ) during coreboot compilation. According to G505s wiki page, currently AtomBIOS blob is needed for onboard VGA, but maybe its also needed for your working backlight?

I retrieved my vgabios via Linux kernel 3.19 using this method -  .Then I downloaded latest sources of SeaBIOS & Coreboot, and build Coreboot using compiled SeaBIOS payload as well as vgabios file. My configuration is a bit similar to this one - - although some options were added and some removed since a time of that build.

In my understanding, vgabios needs to be extracted from a running machine. So just in case if your G505s is in bricked state and you can't run it for extraction of vgabios, I am sending it to you in attachments of this letter!

However I need to mention one interesting thing: after my laptop started running coreboot, what I retrieve via Linux kernel is now slightly different -- if to compare with what I used to retrieve before , while my laptop was still running a proprietary BIOS. And I have flashed coreboot rom into BIOS chip with file verification , so that doesn't seem to be a  "bad flashing" case. Looks like Coreboot does not load a vgabios ROM inside it AS-IS, and instead modifies it slightly while loading...

So here are two bios files for you (could use any of them, maybe "before" one like I did)
vgabios_before.bin - SHA1 checksum: e4d320eb278b0118c46e2e470e7154b12c41966d
vgabios__after.bin - SHA1 checksum: a9e2ed569bbaaea283b5380a5f6c44fc4efc3da4

And here is a report about 3 bytes difference between them -

P.S. What if your backlight problem could be related to manufacturer/model of LCD panel? For the reference, my panel is Samsung LTN156AT30L01 ( SDC Model 4652 ) which is working perfectly

On 4 April 2015 at 13:08, Vladimir <quickcracktime <at>> wrote:
> Very sorry to hear that your LCD backlight problem is not resolved yet!
> Are you confident that LCD backlight is not faulty, and have you tried
> reinstalling coreboot?
> If answer for both questions is "yes", then you could try these two advices:
> 1) Redownload a source code of coreboot from github, compile it and flash
> again to your G505s.
> Since your last try - at the end of January - there were 5 commits to
> "coreboot/src/mainboard/lenovo/g505s" branch,
> and also some commits to the common branches, changes that affect all the
> mainboards supported by coreboot.
> Maybe your issue will be resolved if you would try coreboot again, with
> latest sources!
> 2) If 1st advice doesn't work, you could open
> "coreboot/src/mainboard/lenovo/g505s/buildOpts.c" file
> (which is the only file from G505s branch that has a reference to "LCD")
> Go to line 158, try to change the "#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL
> 200" parameter.
> Default value seems to be 200 for most platforms, but you could try setting
> it to 0. Then compile & flash again
> === Any advices from experienced coreboot members would be very welcome! ===
> On 3 April 2015 at 17:46, 1 1 <zilogpnz <at>> wrote:
>> No. I not solved this problem.
>> 2015-04-03 17:08 GMT+04:00 Vladimir <quickcracktime <at>>:
>>> > On Mon Jan 26 13:07:42 CET 2015 zilogpnz wrote:
>>> >> I'm trying to run Coreboot on Lenovo G505s and have a problem:
>>> >> - backlight of LCD is not turn on. But on the external LCD (by CRT
>>> >> connector) is all good.
>>> >>
>>> >> Could you help me with a solution to this problem?
>>> Sorry for such a long reply, but what is a current status of this
>>> problem?
>>> Have you resolved the LCD backlight problem with your G505s - and, if
>>> yes, how?
Attachment (vgabios_before.bin): application/octet-stream, 81 KiB
Attachment (vgabios_after.bin): application/octet-stream, 81 KiB

coreboot mailing list: coreboot <at>
Iru Cai | 2 May 13:43 2015

cmos.layout: power_on_after_fail


After I set CONFIG_USE_OPTION_TABLE, my laptop will power on when I plug in the AC adapter. Then I find disabling `power_on_after_fail' will prevent my laptop from booting when AC is plugged in. So I wonder why this setting is called `power_on_after_fail' instead of `power on AC attach' as with the vendor BIOS?


coreboot mailing list: coreboot <at>
Peter Stuge | 1 May 20:30 2015

Re: Kconfig: Move `CBFS_SIZE` out of main section

Julius Werner wrote:
> > What section should
> >
> >         (0x400000) Size of CBFS filesystem in ROM
> >
> > be moved to?
> The option is closely related to ROM_SIZE, so maybe put it under
> 'Mainboard -->' with that?

Sounds good.

> > Furthermore, should it even be visible or be hidden as an expert option?
> Hiding it as an expert option probably makes sense. It is used to
> restrict the amount of space coreboot (CBFS) takes up on the ROM in
> case you want to put other stuff on there as well, which is probably a
> pretty limited use case.

I think making it depend on EXPERT is a great idea.

I'd also like the interface to be friendlier. What granularity is
actually supported for the option? I doubt that it's single bytes?

Maybe make it decimal kb? The default value depends on ROM_SIZE, right?



coreboot mailing list: coreboot <at>

Paul Menzel | 1 May 13:55 2015

[RFC] Putting HDA verbs in CBFS

Dear coreboot folks,

currently there are three change sets up for review adding new Lenovo
laptops based on the Intel GM45 chipset [1][2][3]. Most of them are very
similar to the Lenovo X200, which is already in our tree.

One of the major differences between the Lenovo T* models is the HDA
verb table. As these are currently included during compile time, all
board files have to be copied [3] as Peter noted:

        Patch Set 2: Code-Review-2

        vendor BIOS provides different HDA verbs: coreboot of course
        needs to do that too. This should still be replaced with a
        separate port: yes exactly. please resubmit when that is done.

It’d be great to have one image to support all these different models.

Is it feasible to put the HDA verb tables for the different models into
CBFS and load the right one during run time? If such a model run time
detection is not possible, then the corresponding HDA verb file could be
added during the build process and the devices Lenovo R400 and T500
would just be clones of the Lenovo T400 for example with different HDA



New mainboard: Lenovo T500
mainboards/lenovo: Copy X200 board to T400 for future expansion
lenovo/r400: Add clone of Lenovo T400

coreboot mailing list: coreboot <at>
Paul Menzel | 1 May 11:21 2015

Kconfig: Move `CBFS_SIZE` out of main section

Dear coreboot folks,

commit f780c40f (CBFS: Correct ROM_SIZE for ARM boards, use CBFS_SIZE
for cbfstool) [1] adds a description to the Kconfig variable
`CBFS_SIZE`, which makes it, I think, visible in the Kconfig menu (`make

┌─────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────────┐ │
  │ │                                 General setup  --->                                                                             │ │
  │ │                                 Mainboard  --->                                                                                 │ │
  │ │                                 Chipset  --->                                                                                   │ │
  │ │                                 Devices  --->                                                                                   │ │
  │ │                                 Display  --->                                                                                   │ │
  │ │                                 Generic Drivers  --->                                                                           │ │
  │ │                                 Console  --->                                                                                   │ │
  │ │                             (0x400000) Size of CBFS filesystem in ROM                                                           │ │
  │ │                                 System tables  --->                                                                             │ │
  │ │                                 Payload  --->                                                                                   │ │
  │ │                                 Debugging  --->

What section should

        (0x400000) Size of CBFS filesystem in ROM

be moved to?

Furthermore, should it even be visible or be hidden as an expert option?




coreboot mailing list: coreboot <at>
Timothy Pearson | 29 Apr 23:30 2015

coreboot ported to the ASUS KGPE-D16 (Libreboot: blobless, fully functional!)


I have successfully ported coreboot to the relatively modern ASUS 
KGPE-D16 server board (dual AMD socket G34, 16 DDR3 DIMMs,!  This 
port uses native Family 10h initialization (_not_ AGESA or CIMX).

The Libreboot folks will be interested to know that this board can run 
blob-free and still retain full functionality!

Port specifications:
CPU: Dual AMD G34 Magny-Cours (Family 10h)
RAM: 16 DDR3 DIMM slots with ECC support (tested with x4 4G DDR3-1333 
unbuffered DIMMs)

PCIe slots: all functional
PCI slot: functional
RS-232: functional
PS/2: expected to function, not tested (on SuperIO)
ASpeed VGA device: functional (text mode, see below)
IEEE1394: functional
On-board USB: functional
On-board NICs: functional
ASUS PIKE SAS controller: functional
PCIe ROMs: functional

Power management:
DDR3 voltage set: functional
ACPI/APIC: functional
Suspend/resume: broken

cbmem console: partial support (log truncated)
cbmem timestamps: functional
nvram: functional
BIOS recovery jumper: functional

ASpeed VGA:
The ASpeed VGA device initialises in text mode via its (new) coreboot 
driver, however this initialisation is incomplete, leading to distorted 
but quite usable VGA output.  When Linux boots and engages the graphical 
framebuffer all distortion disappears.

This port was not trivial.  Almost every device used was broken and 
required debugging/repair, with the notable exception of the SuperIO 
chip.  The AMD DDR3 controller was severely broken to the point where 
large rewrites were needed in order to bring it in line with the BKDG. 
Even after the various component drivers were repaired

Due to the labor-intensive nature of the port and the extensive changes 
throughout the entire source tree, it is not economically feasible to 
merge this port upstream at this time (I estimate upward of 30 
independent patches would be required just to get the board booting!). 
Raptor Engineering will, however, be continuing to maintain this port 
internally, and I am currently looking into adding native Family 15h 
support on top of this internal tree.  Additionally, while it was not a 
priority for the initial port, I will be attempting to enable 
suspend/resume functionality as I have time.

If there is sufficient interest from the community in adding this board 
to coreboot I would consider merging the changes in exchange for a 
one-time contract payment in the vicinity of $35,000 USD.  When 
considering this offer please bear in mind that this is a fully 
functional blobless board with a wide range of peripherals and expansion 
options available, and that once these large changes are merged I will 
continue to enhance coreboot functionality as before (e.g. with the 
KFSN4-DRE and the T400).  I would also be willing to add this board to 
the test stand as the only fully supported 4-way Opteron board (socket 
G34 Magny-Cours CPUs contain two separate CPUs in one package, making 
this 2-socket board a 4-way system from a HyperTransport perspective).

Please let me know if you have any questions!

Timothy Pearson
Raptor Engineering
+1 (415) 727-8645


coreboot mailing list: coreboot <at>

sibu | 27 Apr 21:25 2015

build failure on amd64 host:- help


I am new to this list.

I am trying to learn how to compile coreboot.  My host has these:

---cpu:  AMD64 3 cores
---OS:  linux (BLFS) linux-3.10.32, ( pure 64-bit ), gcc-4.8.1. IASL ( 
downloaded as tbb41_201305160ss )

A ) I fetched coreboot  fron the git repository
B ) I unpacked the downloaded in /usr/src 
C ) I ran 'make menuconfig' and  selected  'build with any toolchain'
D ) I then ran 'make'  which ended as follows:-

mv build/coreboot.pre1.tmp build/coreboot.pre1
    LINK       cbfs/fallback/romstage_null.debug
ld.bfd -b elf32-i386 -melf_i386 --gc-sections -nostdlib -nostartfiles -static 
-o build/cbfs/fallback/romstage_null.debug -Lbuild --wrap __divdi3 --wrap 
__udivdi3 --wrap __moddi3 --wrap __umoddi3 --start-group 
build/generated/crt0.romstage.o build/mainboard/emulation/qemu-
i440fx/static.romstage.o build/arch/x86/boot/boot.romstage.o 
build/arch/x86/lib/memcpy.romstage.o build/arch/x86/lib/memmove.romstage.o 
build/arch/x86/lib/memset.romstage.o build/arch/x86/lib/rom_media.romstage.o 
build/console/console.romstage.o build/console/die.romstage.o 
build/console/init.romstage.o build/console/post.romstage.o 
build/console/printk.romstage.o build/console/vtxprintf.romstage.o 
build/cpu/x86/car.romstage.o build/cpu/x86/lapic/boot_cpu.romstage.o 
build/device/device_romstage.romstage.o build/device/pci_early.romstage.o 
build/drivers/uart/uart8250io.romstage.o build/drivers/uart/util.romstage.o 
build/lib/bootmode.romstage.o build/lib/cbfs.romstage.o 
build/lib/cbfs_core.romstage.o build/lib/cbmem_common.romstage.o 
build/lib/cbmem_console.romstage.o build/lib/clog2.romstage.o 
build/lib/compute_ip_checksum.romstage.o build/lib/dynamic_cbmem.romstage.o 
build/lib/gcc.romstage.o build/lib/halt.romstage.o 
build/lib/hexdump.romstage.o build/lib/loaders/cbfs_ramstage_loader.romstage.o 
build/lib/loaders/load_and_run_ramstage.romstage.o build/lib/lzma.romstage.o 
build/lib/lzmadecode.romstage.o build/lib/memchr.romstage.o 
build/lib/memcmp.romstage.o build/lib/prog_ops.romstage.o 
build/lib/ramtest.romstage.o build/lib/version.romstage.o 
build/southbridge/intel/i82371eb/early_smbus.romstage.o  /usr/lib/gcc/x86_64-
unknown-linux-gnu/4.8.1/libgcc.a --end-group -T 
build/lib/gcc.romstage.o: In function `__wrap___udivdi3':
/usr/src/coreboot_GIT170415/src/lib/gcc.c:37: undefined reference to 
build/lib/gcc.romstage.o: In function `__wrap___umoddi3':
/usr/src/coreboot_GIT170415/src/lib/gcc.c:39: undefined reference to 
make: *** [build/cbfs/fallback/romstage_null.debug] Error 1
rm build/cbfs/fallback/bootblock.elf


I am running on a pure 64-bit host   but it seems coreboot is attempting to  
link 32-bit binaries.     Help  to successfuly build coreboot  will be 

Yours sincerely



coreboot mailing list: coreboot <at>

ASUS KFSN4-DRE Automated Test Failure

The ASUS KFSN4-DRE fails verification as of commit 595e7777e7282249b13c3d7f8a45178e76798690

The following tests failed:

Commits since last successful test:
595e777 Kconfig whitespace fixes

See attached boot log for details

This message was automatically generated from Raptor Engineering's ASUS KFSN4-DRE test stand
Raptor Engineering offers coreboot consulting services!  Please visit for more information

Please contact Timothy Pearson at Raptor Engineering <tpearson <at>> regarding
any issues stemming from this notification
Attachment (1430252793-0-automaster.log.bz2): application/octet-stream, 30 KiB

coreboot mailing list: coreboot <at>
chp | 28 Apr 08:42 2015

error building coreboot

i am trying to build coreboot according to

make crossgcc worked fine.

after running "make" im getting the following error and the building 
process is stopped:
/coreboot/util/cbfstool/cbfs_image.c:451:59: error: comparison between 
signed and unsigned integer expressions [-Werror=sign-compare]
   assert((char*)CBFS_SUBHEADER(entry) - image-> ==
cc1: all warnings being treated as errors
make: *** [build/util/cbfstool/cbfs_image.o] Fehler 1

any ideas what is causing this error and how to fix it?

thanks in advance



coreboot mailing list: coreboot <at>

L.R. D.S. | 25 Apr 18:54 2015

Supported VIA notebook?

There any coreboot VIA notebook? On [1] is cited the One A110, but in supported motherboards
page have nothing about it. The VIA website [3] list some models, many with supported specs 
(CPU C7-M ULV and Chipset VIA VX800).


Please, CC me, I'm not in this mailing list.



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