thejapanscout . | 28 May 06:13 2016
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Fujitsu Lifebook P1610 - morely possible candidate

I think I may have found a likely coreboot candidate-- with hardware far more supported than the hardware on the laptop from 2005 that I posted earlier.

Currently, Coreboot has no Fujitsu mobos. But the specs of this Lifebook P1610 are close to a Thinkpad X60, except for the NIC, CPU, and astonishingly the mPCIe cards. Most models of the P1610 shipped with an Ath5k Wi-Fi mPCIe card, which has free software drivers, along with the rest of the non-ME hardware, including the fingerprint reader, making it essentially free-software compatible on the software side.

It also has a touch-screen, making it nifty for artists and workers that want a tablet.

Before you ask, GOOD NEWS! Most of the hardware, as seen in my lspci -tvnn output, has completely added support in coreboot. It also runs off a GM45-based chipset, which can have it's ME deblobbed, making it viable for GNU libreboot.

-[0000:00]-+-00.0  Intel Corporation Mobile 945GM/PM/GMS, 943/940GML and 945GT Express Memory Controller Hub [8086:27a0]
           +-02.0  Intel Corporation Mobile 945GM/GMS, 943/940GML Express Integrated Graphics Controller [8086:27a2]
           +-02.1  Intel Corporation Mobile 945GM/GMS/GME, 943/940GML Express Integrated Graphics Controller [8086:27a6]
           +-1b.0  Intel Corporation NM10/ICH7 Family High Definition Audio Controller [8086:27d8]
           +-1c.0-[02]----00.0  Marvell Technology Group Ltd. 88E8055 PCI-E Gigabit Ethernet Controller [11ab:4363]
           +-1c.2-[05]----00.0  Qualcomm Atheros AR242x / AR542x Wireless Network Adapter (PCI-Express) [168c:001c]
           +-1d.0  Intel Corporation NM10/ICH7 Family USB UHCI Controller #1 [8086:27c8]
           +-1d.1  Intel Corporation NM10/ICH7 Family USB UHCI Controller #2 [8086:27c9]
           +-1d.2  Intel Corporation NM10/ICH7 Family USB UHCI Controller #3 [8086:27ca]
           +-1d.3  Intel Corporation NM10/ICH7 Family USB UHCI Controller #4 [8086:27cb]
           +-1d.7  Intel Corporation NM10/ICH7 Family USB2 EHCI Controller [8086:27cc]
           +-1e.0-[08-0c]--+-03.0  Ricoh Co Ltd RL5c476 II [1180:0476]
           |               \-03.1  Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter [1180:0822]
           +-1f.0  Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge [8086:27b9]
           +-1f.1  Intel Corporation 82801G (ICH7 Family) IDE Controller [8086:27df]
           \-1f.3  Intel Corporation NM10/ICH7 Family SMBus Controller [8086:27da]

SN and UUID:
R7108162
13F0737D-AD13-11DB-8B14-001742268EEB

Baseboard SN:
FJNB1C5

superiotool -dV log:
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
Found SMSC LPC47N217 (id=0x7a, rev=0x00) at 0x2e
No dump available for this Super I/O
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
Found SMSC FDC37N972 (id=0x0b, rev=0x00) at 0x4e
Register dump:
idx 02 20 21 22 23 24 25 26  27 28 29 2a 2b 2c 2d 2e  2f
val 00 0b 00 00 00 00 00 4e  00 00 00 00 00 00 00 00  00
def 00 0b 00 00 00 04 04 NA  NA 00 00 00 00 00 00 00  00
LDN 0x00 (Floppy)
idx 30 60 61 70 74 f0 f1 f2  f3 f4 f5
val 01 fd 00 00 00 00 d1 15  0b 00 10
def 00 03 f0 06 02 0e 00 ff  RR 00 00
LDN 0x01 (Power management (PM1))
idx 30 60 61
val 01 fd 00
def 00 00 00
LDN 0x03 (Parallel port)
idx 30 60 61 70 74 f0 f1
val 01 fd 00 00 00 00 d1
def 00 00 00 00 04 3c 00
LDN 0x04 (COM1)
idx 30 60 61 70 f0
val 01 fd 00 00 00
def 00 00 00 00 00
LDN 0x05 (COM2)
idx 30 60 61 62 63 70 74 f0  f1 f2 f7 f8
val 01 fd 00 00 00 00 00 00  d1 15 00 00
def 00 00 00 00 00 00 04 00  02 03 00 00
LDN 0x06 (Real-time clock (RTC))
idx 30 60 61 62 63 70 f0 f1
val 01 fd 00 00 00 00 00 d1
def 00 00 70 00 74 00 00 NA
LDN 0x07 (Keyboard)
idx 30 60 61 70 72 f0
val 01 fd 00 00 00 00
def 00 00 00 00 00 00
LDN 0x08 (Embedded controller (EC))
idx 30 60 61
val 01 fd 00
def 00 00 62
LDN 0x09 (Mailbox)
idx 30 60 61
val 01 fd 00
def 00 00 00

flashrom is once again, detecting an unsupported laptop though. Is there an option to bypass detection in flashrom?
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Antonello Dettori | 28 May 00:32 2016

Re: Building tint


If you are still interested try this commit:

https://review.coreboot.org/#/c/14989/

It should work. The instructions on the wiki are not needed now, just 
make the payload.

On 27/05/16 08:48, David Griffith wrote:
>
> Has anyone here been able to produce a Coreboot image that contains 
> tint? It won't compile without a lot of tinkering and uses a really 
> old version.
>

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김유석 책임연구원 | 23 May 02:47 2016

Re: SeaBios serial(RX) is not running.

Dear Sir.

Thank's your work.


Enable the bi-direction serial console is done.


2016-05-20 오후 8:36에 Kyösti Mälkki 이(가) 쓴 글:


On Tue, May 17, 2016 at 10:46 PM, Martin Roth <gaumless <at> gmail.com> wrote:
Hi,
  If you want bi-directional serial port in SeaBIOS, I think you need
to stick with the version from Sage. As far as I know, it's never been
supported in the upstream SeaBIOS version.


I have pulled this serial to keyboard mapping change from SageBIOS and posted on the seabios list today. Hitting ESC and changing boot media seemed to work.

BR,
Kyösti
 

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김유석 책임연구원 | 26 May 08:17 2016

How to control the GPIO on x86 rangely?

Dear Sir.


My platform is intel rangely.


I'm must contol the GPIO pins, But i'm can't found the example code on coreboot source tree.


Could you show me the example code to control GPIO?


Thank you.


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김유석 책임연구원 | 25 May 07:56 2016

How to change the Core input voltage setting?

Dear Sir.


My HW enginner required to me. that Change the setting of "Core input voltage".


But, I don't know everything this one. Because x86 platform is first time of my develop life.

Anyway, I'm try to find the something on coreboot source code.

But, still unknow.


So, I need a start point or key point that Initial code for "Core input voltage".


Please advise to me.

Thank you.

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David Griffith | 27 May 08:48 2016
Gravatar

Building tint


Has anyone here been able to produce a Coreboot image that contains tint? 
It won't compile without a lot of tinkering and uses a really old version.

-- 
David Griffith
dave <at> 661.org

A: Because it fouls the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing in e-mail?

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Andrew Barnes | 26 May 13:21 2016

Guidance for adding SuperIO support


Hi,

I'm new to coreboot. I would like to have it working on the following
hardware:

* Fujitsu D3231  (Q87)
* Intel   DQ87PG (Q87)
* Intel   DQ67OW (Q67)
* Intel   DQ45CB (Q45)

Focusing on the first 3, which are all core-i systems, sandybridge and
haswell. I *believe* that coreboot would already support the CPU and
Chipsets.

(If that is correct?)

However, the SuperIO I know is not supported. They are respectively:

* SMSC SCH5636, devid '0xc7', kdriver 'sch5636'
* NCT6683D-T, devid '0xc730', kdriver 'nct6683'
* W83677HG-I, devid '0xb470', kdriver 'w83627ehf'
* WPCD377I, devid '0xf1', kdriver 'not-a-sensor'?

I know that these chips are supported in the kernel/lm_sensors. So
perhaps all the info I need to add the support into coreboot is already
available?

However, I'm not entirely sure how best to go about this. I don't
really understand what needs to be achieved or how.

I need some guidance to figure this out, is there an good example I
could follow where by a driver from kernel/lm_sensors has been ported
into coreboot?

If I port the superIO chip successfully, is the next stage to simply
create a board which combines the 3 components CPU,Chipset and SIO? or
am I underestimating this?

Could anyone possibly comment on how much work this will be? The
SuperIO support files don't look that indepth, however if that were
true, and if all the info required is already in the kernel - I wonder
why coreboot doesn't already implement the same list in the kernel.

Thanks,

Andy
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Mayuri Tendulkar | 26 May 06:33 2016

Re: Query regarding coreboot for new intel customized board

Thanks Vim.

 

Currently I am not able to get any serial prints out on my reference board.

 

My board is based on Intel ISX board based on Baytrail-I soc E3825 given below.

 

https://www-ssl.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e3800-dev-kit-isx-ref-design-product-brief.html

 

I have built coreboot for this, but unable to get serial prints.

 

How I should debug this further.

 

Regards

Mayuri

 

From: Wim Vervoorn [mailto:wvervoorn <at> eltan.com]
Sent: 24 May 2016 13:26
To: Mayuri Tendulkar <mayuri.tendulkar <at> aricent.com>
Subject: Re: Query regarding coreboot for new intel customized board

 

Hello Mayuri,

 

If your rom image is the same it could be due to the lack of support for the flash device you are using. The MRC cache is preserved in flash so you need to be able to write it.

 

For the others the numbers etc you mention are informational for the OS. They are not strictly required but the OS builds a registry of the items it retrieves from the SMBIOS. If you don’t require this you could also disable the functionality.

 

 

Best Regards,

Wim Vervoorn

 

Eltan B.V.

Ambachtstraat 23

5481 SM Schijndel

The Netherlands

 

T : +31-(0)73-594 46 64

E : wvervoorn <at> eltan.com

W : http://www.eltan.com

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From: coreboot [mailto:coreboot-bounces <at> coreboot.org] On Behalf Of Mayuri Tendulkar
Sent: Tuesday, May 24, 2016 7:26 AM
To: coreboot <coreboot <at> coreboot.org>
Subject: [coreboot] Query regarding coreboot for new intel customized board

 

Hi team

 

I am working on building coreboot for one of our customized board. This is based on Intel ISX board reference design, reference can be taken as Minnowboard or BayleyBay CRB.

 

As per documentation given under coreboot, I created folder with my board name under src/intel/mainboard/xxx and did changes required.

 

If I tried the coreboot with these changes on minnowboard, it got stuck at FSP MRC Cache not found.

 

But if the same code changes I copied under  src/intel/mainboard/minnowmax and built, it booted fine.

 

I would like to know what is the importance of these board names, SMBIOS table name, serial no which are defined for Minnowmax.

 

Is there some master registry where all these are stored, and if any new entry comes, how we should add it.

 

Regards

Mayuri

 

 

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Daniel Kulesz via coreboot | 24 May 20:20 2016

Target Evaluation: Gigabyte GA-EG45M-DS2H

Hi,

since I switched to an F2A-85M I have a spare gigabyte desktop board with the Intel X4500 onboard graphics
(quite rare) which has afaik no coreboot so far. In general, it seems like only one other socket 775 board is
supported. I was wondering if this could be an interesting target or if any major showstoppers are to be
expected. Here's are the specs:

http://www.gigabyte.com/products/product-page.aspx?pid=2877#sp

Although the board just supports DDR2 memory (4 slots), with the Socket 771 pinmod it should be able to run
quite decent and cheap Xeon quadcores.

Cheers, Daniel

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cheng yichen | 24 May 13:42 2016
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Re: Microcode problem with Braswell CPU

Hi all

I find the same problem in my mainboard.The cpu type is N3150. 
but I can't find why the microcode is not loaded to SOC. 
Could you please share your exprience to me? Thank you
 
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David Griffith | 24 May 10:27 2016
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T60: running nvramcui and coreinfo secondary payloads


I'm at the boot menu.  When I select "nvramcui", I get this:

IO space mapped serial not present. Could not find coreboot options table.

Then the firmware locks up.  If I try coreinfo, I get the first sentence, 
then the screen blanks and the firmware locks up.  Ctrl-Alt-Del does 
nothing.  Taking the exact same .config and setting it for QEMU, coreinfo 
works, but selecting nvramcui causes "Could not find coreboot option 
table" to be printed.

-- 
David Griffith
dave <at> 661.org

A: Because it fouls the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing in e-mail?

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Gmane