Daniel Kulesz via coreboot | 28 Jun 10:24 2016

F2A-85M: Different VGA BIOS needed after CPU Upgrade?

Hi folks,

I upgraded the CPU in my F2A-85M from a A4-5300 (Trinity) to a A10-6700 (Richland). The board had Coreboot
installed before with the VGA BIOS extracted from the A4-5300. However, I did not get any video output when
trying to boot after the upgrade, so I replaced the flash chip with a backup with the vendor BIOS that works.

Is it likely that the A10-6700 needs a different VGA BIOS or does this this rather look like a different
issue? I don't want to experiment too much because the BIOS chips are hardware-wise pretty fragile (even
when using the extractor tool).

Cheers, Daniel

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Sergio Valverde | 28 Jun 06:28 2016
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Project for thesis

Hello:

My name is Sergio Valverde and I'm a student at Universidad de Costa Rica. I came across Google Summer of Code and I'm very interested in collaborating with you if any project of those is still available. I'm eager to participate in an open source project, especially one that involves Linux device drivers and Kernel hacking. 

I'm currently finishing my licentiate ("licenciatura") degree, which would be a degree between bachelor and master here in Costa Rica. For graduation, it requires a bachelor-level thesis, so I wanted to know if you have a project that has that kind of scope (or if I can propose one) and if it would be available for a student like me to collaborate. 

My background is in electronic engineering and I'm currently working as an embedded software developer in Hewlett Packard Enterprise in Costa Rica. I'm working in a SDK team for a networking ASIC and my main duties have involved building firmware images with Yocto, writing Linux device drivers for PCIe and coding software to interface high-level functions with hardware registers.

I'm really looking forward for whatever information you can give me in this matter. I attached my resume to this mail and my Linkedin profile URL is https://cr.linkedin.com/in/sergio-valverde-9058b971.

Hopefully we can work together.
Sergio Valverde
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WordPress | 27 Jun 22:49 2016

New on blogs.coreboot.org: [GSoC] Better RISC-V support, week #4/5

A new post titled "[GSoC] Better RISC-V support, week #4/5" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2016/06/27/gsoc-better-risc-v-support-week-45/

Week 4

In week 4, I tracking down why coreboot halted after about one line of output. It turned out to be a spike bug, that I wrote up in this bug report, and affect any program that doesn’t have a tohost symbol. As a workaround, I extended my script that turns coreboot.rom into a ELF to also include this symbol.

After some more patches I could run coreboot in spike and get the familiar “Payload not loaded” line.

Week 5

I was now clearly moving towards being able to run linux on spike/coreboot. But there was a problem: The RISC-V linux port requires a working implementation of the Supervisor Binary Interface (SBI), which is a collection of functions that the supervisor (i.e. the linux kernel) can call in the system firmware.

Coreboot has an implementation of the SBI, but it’s probably outdated by now. To get an up-to-date SBI implementation, I decided to use bbl as a payload. When I built bbl with coreboot’s RISC-V toolchain, I noticed that it depends on a libc being installed in two ways:

  • The autoconf-generated configure script checks that the C compiler can compile and link a program, which only succeeds if it finds a linker script (riscv.ld) and a crt0.o in the right place.
  • bbl relies on the libc headers to declare some common functions and types (it doesn’t use any of the implementations in the libc, though).

The coreboot toolchain script doesn’t, however, install a libc, because coreboot doesn’t need one.

I tweaked the bbl source code until it didn’t need the libc headers, changed the implementation of mcall_console_putchar to use my 8250 UART, got the payload section of bbl (where linux is stored before it’s loaded) out of the way of the CBFS by moving it to 0x81000000 (bbl/bbl.lds is the relevant file for this change), and could finally observe Linux booting in spike, on top of coreboot and bbl. It stops with a kernel panic, though, because it doesn’t have a root filesystem.

Plans for this week

This week I will document my work on the Spike wiki page in the coreboot wiki, so others can run coreboot on spike, too.

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Patrick Rudolph | 27 Jun 16:17 2016

Re: T420 Optimus/NVIDIA GPU support

On 2016-06-26 07:25 AM, Intel Miner wrote:
> Hi everyone,
> 
> Apologies if this is the wrong place to ask about this, but
> 
> I'm eyeing off buying a Lenovo T420 ThinkPad, specifically one with the
> NVIDIA GPU, with "Optimus" support
> 
> The information I can dig up on the initial support says that the NVIDIA
> GPU models are NOT supported by Coreboot
> 
> However I see in the hybrid_graphics.c file that there's a listing for the
> "T420/T520" (the T520 seemingly /does/ support the NVIDIA GPU?)
> 
> I can't seem to find any up-to-date information either way regarding the
> GPU status in the T420 however. Any information regarding this would be
> appreciated :)
> 
> (Alternatively I could just purchase one, build Coreboot and try, of
> course!)

Hi !
Latest coreboot does support Nvidia GPUs on all Txx models, but it
doesn't support Optimus.
The hybrid_graphics is for switching display panel to the selected GPU
on Optimus muxed laptops.
At the moment you can choose to use one of the GPUs at boot time! The
other one will be disabled.
In theory you could use both GPU at the same time using DRI_PRIME (with
latest HEAD),
but it will use much more power, as Optimus isn't supported, and the
Nvidia GPU is always active.

What's missing to implement Nvidia Optimus:
* ACPI for panel switching on "muxed" devices
* ACPI for power switching on all devices

Regards,
Patrick

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Intel Miner | 26 Jun 07:25 2016
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T420 Optimus/NVIDIA GPU support

Hi everyone,

Apologies if this is the wrong place to ask about this, but

I'm eyeing off buying a Lenovo T420 ThinkPad, specifically one with the NVIDIA GPU, with "Optimus" support

The information I can dig up on the initial support says that the NVIDIA GPU models are NOT supported by Coreboot

However I see in the hybrid_graphics.c file that there's a listing for the "T420/T520" (the T520 seemingly /does/ support the NVIDIA GPU?)

I can't seem to find any up-to-date information either way regarding the GPU status in the T420 however. Any information regarding this would be appreciated :)

(Alternatively I could just purchase one, build Coreboot and try, of course!)
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How to get support for amd southbridge rs780l

Hi, I porting Coreboot on the motherboard Asus m5a78l-m lx3 (AMD Fam10h + 760G (RS780L).
I cant set the correct memory map and launch the internal graphics core. I think the problem is an incorrect initialization Southbridge RS780L and gfx. The lack of documentation on the chipset RS780L and the source code to initialize it makes it impossible to complete the porting.
How can I get support from AMD, get documentation or source code for initialize Southbridge RS780L and gfx?
All thanks!
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WordPress | 21 Jun 17:08 2016

New on blogs.coreboot.org: [GSOC] Panic Room, week #3

A new post titled "[GSOC] Panic Room, week #3" has been published on the coreboot blog. Find the full post at http://blogs.coreboot.org/blog/2016/06/21/gsoc-panic-room-week-3/

What happened during the past week ?

After many iteration of patches and bug hunting I finished writing and testing the code that added to cbfstool allows to convert between SELF and ELF.
The code has been now merged.

One of the most problematic things has been to get GRUB to work after the conversion to ELF whereas all of the other payloads were working wonderfully.
It turned out it is the only payload (that I tested) that used more than two segments to describe the memory image of  the program.
This also uncovered a bug contained inside the elf_writer code that was probably never triggered given that the majority of payloads only contain one segment (commit).

I also received the replacement mobo for my Lenovo X60 target, so I can get back on track with the SerialICE part of the project.

What are your plans for next week?

I am currently investigating a bug in the serial communication between QEMU and the target while using the most recent version of the patch that integrates SerialICE into coreboot.
I am also looking into some work related to selfboot.c and the region api; the objective is to avoid loading the payload all at once while it is being executed and allow for the various parts of the payload to be loaded when needed.
Hopefully I’ll manage to finish all of this before next week. (Sometimes I definitely feel too optimistic)

What?! Didn’t you have any mishaps© this week?

It’s indeed quite fascinating how my equipment keeps breaking… this week was my Raspberry Pi’s turn. It won’t boot anymore.
Fortunately I have a Bus Pirate and a BeagleBone Black to use for SPI flashing, so it’s all good.

See you next week!

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Alexander Couzens | 23 Jun 03:02 2016
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some noise on gerrit by lava

hi,

I'll do some testing with gerrit + jenkins integration related to
the lava test framework.
I'm using the user *lava* to do those tests.
If you get an unrelated `Verified -1` by the user *lava* on your
commit, please ping me on irc or by mail so I can fix that.

Best,
lynxis
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Alexander Couzens

mail: lynxis <at> fe80.eu
jabber: lynxis <at> fe80.eu
mobile: +4915123277221
gpg: 390D CF78 8BF9 AA50 4F8F  F1E2 C29E 9DA6 A0DF 8604
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Arthur Heymans | 22 Jun 23:34 2016

RFC: implementing a way to force external EDID use.

Hi

In Linux it is possible to load an EDID externally. Coreboot can
currently not do this. Do you think it is worth implementing this
feature?

An EDID file is a bit to big (128 bytes) to fit in nvram so it would have to go in cbfs.
Where in the code do you think this setting should be implemented:
NB code, read_edid in drivers, decode_edid in lib, somewhere else?
How do you think this feature should be turned on: nvram option or build
option?

Thank you for your comments
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ron minnich | 20 Jun 20:19 2016
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kgpe-d16

I have a kgpe-d16 with coreboot and it *was* working with linux. I now have a linux kernel that won't boot on fuctory bios or coreboot. I can't recall changing anything ...

If somebody's got a known good .config for linux I could sure use it. I'm booting stock tinycore and it seems to hang a lot.

thanks

ron
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Rolf Evers-Fischer | 21 Jun 15:25 2016
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How to obtain FSP v2.0 for ApolloLake?

Coreboot for Intel ApolloLake needs FSP v2.0 blobs. Unfortunately FSP v2.0 is
not offered at www.intel.com/fsp.
Do you know, how or where I could get it?

Kind regards,
 Rolf

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Gmane