Recording the LinuxTag talks

Hi,

would someone please be so kind and record the coreboot talks at
LinuxTag? A few of my colleagues can't be at LinuxTag, but they have
expressed interest in watching the talks if any recording is made available.

Thanks in advance!

Regards,
Carl-Daniel

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S3 fails to suspend after wake up from USB keyboard

Hi,
I am trying to debug an issue on Parmer.
1) use "pm-suspend" to suspend.
2) use USB keyboard to wake up.
3) use "pm-suspend" to suspend. FAIL To SUSPEND.

After wake up by USB keyboard, I got some errors in dmesg:
[   55.585935] Disabling IRQ #9

I don't know why this is happened. It seems that ACPI method (_PTS,
_WAK) have nothing to do with suspend and wake up.

Does anybody can help me?
1) What is the workflow of USB keyboard wake up from S3?
2) What are differences between power button wake up and USB keyboard wake up?

dmesg:
[   55.585874] irq 9: nobody cared (try booting with the "irqpoll" option)
[   55.585880] Pid: 691, comm: X Tainted: P           O 3.6.11-1-ARCH #1
[   55.585882] Call Trace:
[   55.585884]  <IRQ>  [<ffffffff810daffd>] __report_bad_irq+0x3d/0xe0
[   55.585895]  [<ffffffff810db2f3>] note_interrupt+0x1a3/0x1f0
[   55.585899]  [<ffffffff810e1bdf>] ? rcu_process_callbacks+0xaf/0x5b0
[   55.585903]  [<ffffffff810d8bcf>] handle_irq_event_percpu+0xbf/0x260
[   55.585907]  [<ffffffff8105e952>] ? __do_softirq+0x122/0x240
[   55.585910]  [<ffffffff810d8db8>] handle_irq_event+0x48/0x70
[   55.585913]  [<ffffffff810dbe0a>] handle_fasteoi_irq+0x5a/0x100
[   55.585917]  [<ffffffff81017502>] handle_irq+0x22/0x40
[   55.585921]  [<ffffffff8149c04a>] do_IRQ+0x5a/0xe0
[   55.585925]  [<ffffffff8149356a>] common_interrupt+0x6a/0x6a

Trying to get coreboot running on VIA EPIA-M (lzma: Decoding error = 1)

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Exposing performance data to user space/systemd

Dear coreboot folks,

as LinuxTag approaches and some of the systemd developers are going to
be there, I remembered the discussion how systemd only supports exposing
performance data on EFI systems [1].

Christian already brought up coreboot/SeaBIOS in that discussion. H.
Peter Anvin (Syslinux) also voiced a need for a having that for non-EFI
systems.

Christin, are there any news?

Thanks to the CBMEM console, the cbmem utility can read, and the timer
work, we have performance data available now. If I am not mistaken,
Chrome OS also supports reading these values. So maybe such an interface
could be designed during LinuxTag and implemented afterward.

If I am right about Chrome OS, do the developers have any suggestions?
Are you content with your interface and can it be generalized for
different boot loaders?

Thanks,

Paul

[1] https://plus.google.com/115547683951727699051/posts/dXs8rrFQkLd
[2] http://www.freedesktop.org/wiki/Software/systemd/BootLoaderInterface/

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Coreboot hackathon hardware

Hello, all. I'll be at LinuxTAG and hackathon. This mail is to ask if
someone needs some of hw I can take with me (list at the end), I won't
take it unless I have requests.
Does anybody want to share rooms to save on hotel costs?

HW List:
PL2303 USB-RS232 converter
bus pirate
2 SOIC 8-pin clips
Raspberry Pie
Thinkpad X201 (coreboot)
USB rollable keyboard
cables of all kind
NET20DC USBdebug
gear for network
USB wireless
USB 3G modems
Thinkpad X230 (my next port)
Asus A8N-E (corebootable)
PLCC32 parallel flash chips
PLCC32 FWH/LPC chips
PLCC extractor
Lemote Yeeloong 2F
Lemote Fuloong 2F
Lemote Yeeloong 3A
Apple Powerbook G4

Too big for transport but I can setup SSH in advance if needed: ia64,
alpha, sparc64, SGI Indy, hppa

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Where to put configuration of USB debug port (was: [PATCH] intel/bd82x6x: Add Kconfig options for USB debug port)

Dear coreboot folks,

today several devices have more than just one USB debug port, so it
makes sense to be able to configure it. Patch »intel/bd82x6x: Add
Kconfig options for USB debug port« [1] implements that for Intel
BD82x6x. I guess this could be made available to all boards right away.
So suggestions where to put these Kconfig variables are very much
appreciated.

Thanks,

Paul

[1] http://review.coreboot.org/3240

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coreboot on a Toshiba A100-151 laptop?

Dear coreboot folks,
 
I admire the coreboot project because it's a fast and up-to-date open source alternative to the
proprietary bios crap provided by many vendors. For this reason I am thinking about using coreboot on my
Toshiba A100-151 laptop system since it is not supported anymore by Toshiba and even they discontinued to
provide all the old drivers for this model in the support section on their homepage (Thank you, you
customer-unfriendly profiteers!). How ridiculous that this company has received the German  
 environmental label "Blue Angel" for some of their products in the past (just a little side note). And
even with their locked and constricted Firmware updates I feel somehow as if I should be artificially
hindered to use the full potentials of hardware features of my laptop. Just to mention some examples:
 
- I cannot use the AHCI mode of the SATA controller although the mainboard should be able to switch to this
mode. There is no option in the bios and it's always locked to IDE mode. Therefore, the performance of my new
SSD is artificially limited to a low level.
- Even Toshiba showes on their homepage that 4GB RAM memory are supported by the mainboard, I could only use
3GB at maximum, even after installing diverse 64bit OS such as Ubuntu Linux 12.04 and Windows 7. I guess
that some of the missing 1GB RAM will be addressed to the OS and to my ATI video graphic card in particular,
although it was shipped with 128MB of dedicated RAM. But again there is no option in the bios settings to
manage the VGA Shared Memory.
- Few time ago, I couldn't enable the Intel VT feature of my CPU. However, I found a workaround by flashing a
modded custom bios from another forum which enabled some great features. But unfortunately, there is
still no ahci support 
 
In short, after reading a lot of tutorials in the internet and trying different solutions in Linux and
Windows OS (e.g. using registry modifications, pre-boot parameters in grub2 mainly with the command
"setpci" as well as trying a MBR mod at the end), I wasn't successful to enable ahci mode and I recognized in
general that the bios restrictions by Toshiba obviously represent the biggest problem.
 
But now to coreboot: So far, I made some first experimental steps by testing coreboot in a qemu environment.
At least, in qemu I succeeded! The documentation on the coreboot homepage was of great help.
 
However, I am still unsure if coreboot could work on my machine under real conditions after flashing. And
because of my very limmited technical knowledge, I would appreciate some help and advices very much in
order to avoid making mistakes or to brick my laptop at the end. Therefore, I hope to meet here some friendly
persons who are willing to help.
 
In view of the fact, that my model hasn't been supported yet by coreboot I would like to provide all needed
information I could get in the following part (with my personal comments marked by "###“):
 
 
------ A very brief description of my system: 
 
board vendor:    Toshiba
 
board name:    Satellite A100-151
### please, don't get confused because later you will also see the product name "Satellite M110". This is
due to the modded bios with advanced features which I have flashed. The right name is "Satellite A100-151".
 
CPU:        Intel Core2Duo T7200
### I have upgraded the CPU. Maybe following output from "dmidecode" could be usefull as well:
 
Handle 0x0004, DMI type 4, 35 bytes
Processor Information
    Socket Designation: U2E1
    Type: Central Processor
    Family: Other
    Manufacturer: Intel
    ID: F6 06 00 00 FF FB EB BF
    Signature: Type 0, Family 6, Model 15, Stepping 6
    Flags:
        FPU (Floating-point unit on-chip)
        VME (Virtual mode extension)
        DE (Debugging extension)
        PSE (Page size extension)
        TSC (Time stamp counter)
        MSR (Model specific registers)
        PAE (Physical address extension)
        MCE (Machine check exception)
        CX8 (CMPXCHG8 instruction supported)
        APIC (On-chip APIC hardware supported)
        SEP (Fast system call)
        MTRR (Memory type range registers)
        PGE (Page global enable)
        MCA (Machine check architecture)
        CMOV (Conditional move instruction supported)
        PAT (Page attribute table)
        PSE-36 (36-bit page size extension)
        CLFSH (CLFLUSH instruction supported)
        DS (Debug store)
        ACPI (ACPI supported)
        MMX (MMX technology supported)
        FXSR (FXSAVE and FXSTOR instructions supported)
        SSE (Streaming SIMD extensions)
        SSE2 (Streaming SIMD extensions 2)
        SS (Self-snoop)
        HTT (Multi-threading)
        TM (Thermal monitor supported)
        PBE (Pending break enabled)
    Version: Intel(R) Core(TM)2 CPU         T7200
    Voltage: 3.3 V
    External Clock: Unknown
    Max Speed: 2048 MHz
    Current Speed: 2000 MHz
    Status: Populated, Enabled
    Upgrade: ZIF Socket
    L1 Cache Handle: 0x0005
    L2 Cache Handle: 0x0006
    L3 Cache Handle: Not Provided
    Serial Number: Not Specified
    Asset Tag: Not Specified
    Part Number: Not Specified
 
 
northbridge:    8086:27a0 (i945GM)
 
### Here is some further information extraced by using the program "PC Wizard 2012" in Windows. However, I
am not sure if this will be usefull. Furthermore, this application reports "Intel i945PM" as northbridge
in contrast to the Linux output.
 
Codename :    Calistoga  Revision :     Stepping :    A3  
Bus Speed :    .24 M
FSB Frequenz :    MHz (QDR)
FSB max. Support :    MHz  RAM max. Support :    DDR2 (667)
 
 
southbridge:    SouthBridge :    8086:27b9 (ICH7-M)
 
### Here is what the Windows program "PC Wizard 2012" reports:
GBM (ICH7-M/U) LPC Interface Controller
Revision :    
 
 
 
------ output of "lspci -tvnn" 
 
-[0000:00]-+-00.0  Intel Corporation Mobile 945GM/PM/GMS, 943/940GML and 945GT Express Memory
Controller Hub [8086:27a0]
+-01.0-[01]----00.0  Advanced Micro Devices [AMD] nee ATI M56P [Radeon Mobility X1600] [1002:71c5]
+-1b.0  Intel Corporation N10/ICH 7 Family High Definition Audio Controller [8086:27d8]
+-1c.0-[02]--
+-1c.1-[03-04]--
+-1c.2-[05-06]----00.0  Intel Corporation PRO/Wireless 3945ABG [Golan] Network Connection [8086:4222]
+-1d.0  Intel Corporation N10/ICH 7 Family USB UHCI Controller #1 [8086:27c8]
+-1d.1  Intel Corporation N10/ICH 7 Family USB UHCI Controller #2 [8086:27c9]
+-1d.2  Intel Corporation N10/ICH 7 Family USB UHCI Controller #3 [8086:27ca]
+-1d.3  Intel Corporation N10/ICH 7 Family USB UHCI Controller #4 [8086:27cb]
+-1d.7  Intel Corporation N10/ICH 7 Family USB2 EHCI Controller [8086:27cc]
+-1e.0-[07-0b]--+-06.0  Texas Instruments PCIxx12 Cardbus Controller [104c:8039]
|               +-06.1  Texas Instruments PCIxx12 OHCI Compliant IEEE 1394 Host Controller [104c:803a]
|               +-06.2  Texas Instruments 5-in-1 Multimedia Card Reader (SD/MMC/MS/MS PRO/xD) [104c:803b]
|               +-06.3  Texas Instruments PCIxx12 SDA Standard Compliant SD Host Controller [104c:803c]
|               \-08.0  Intel Corporation PRO/100 VE Network Connection [8086:1092]
+-1f.0  Intel Corporation 82801GBM (ICH7-M) LPC Interface Bridge [8086:27b9]
+-1f.2  Intel Corporation 82801GBM/GHM (ICH7-M Family) SATA Controller [IDE mode] [8086:27c4]
\-1f.3  Intel Corporation N10/ICH 7 Family SMBus Controller [8086:27da]
 
 
------ output of "superiotool -dV"
 
superiotool r6637
Probing for ALi Super I/O at 0x3f0...
Failed. Returned data: id=0xffff, rev=0xff
Probing for ALi Super I/O at 0x370...
Failed. Returned data: id=0xffff, rev=0xff
Probing for Fintek Super I/O at 0x2e...
Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x2e...
Failed. Returned data: vid=0xffff, id=0xffff
Probing for Fintek Super I/O at 0x4e...
Failed. Returned data: vid=0xffff, id=0xffff
Probing for ITE Super I/O (init=standard) at 0x25e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x25e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x25e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x25e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x25e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=standard) at 0x2e...
Failed. Returned data: id=0x3503, rev=0x0
Probing for ITE Super I/O (init=it8502e) at 0x2e...
Failed. Returned data: id=0x3503, rev=0x0
Probing for ITE Super I/O (init=it8761e) at 0x2e...
Failed. Returned data: id=0x3503, rev=0x0
Probing for ITE Super I/O (init=it8228e) at 0x2e...
Failed. Returned data: id=0x3503, rev=0x0
Probing for ITE Super I/O (init=0x87,0x87) at 0x2e...
Failed. Returned data: id=0x3503, rev=0x0
Probing for ITE Super I/O (init=standard) at 0x4e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8502e) at 0x4e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8761e) at 0x4e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=it8228e) at 0x4e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=0x87,0x87) at 0x4e...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8661f) at 0x370...
Failed. Returned data: id=0xffff, rev=0xf
Probing for ITE Super I/O (init=legacy/it8671f) at 0x370...
Failed. Returned data: id=0xffff, rev=0xf
Probing for NSC Super I/O at 0x2e...
Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x4e...
Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x15c...
Failed. Returned data: port=0xff, port+1=0xff
Probing for NSC Super I/O at 0x164e...
Failed. Returned data: port=0xff, port+1=0xff
Probing for Nuvoton Super I/O at 0x164e...
Failed. Returned data: chip_id=0xffff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e...
Failed. Returned data: sid=0xff, id=0xffff, rev=0x00
Probing for Nuvoton Super I/O at 0x2e...
Failed. Returned data: chip_id=0xffff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e...
Failed. Returned data: sid=0xff, id=0xffff, rev=0x00
Probing for Nuvoton Super I/O at 0x4e...
Failed. Returned data: chip_id=0xffff
Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e...
Failed. Returned data: sid=0xff, id=0xffff, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e...
Failed. Returned data: id=0x35, rev=0x03
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e...
Failed. Returned data: id=0x00, rev=0x00
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370...
Failed. Returned data: id=0xff, rev=0xff
Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370...
Failed. Returned data: id=0xff, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x2e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x2e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x4e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x4e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x3f0...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x3f0...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x370...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x370...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x370...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x370...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x88) at 0x250...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x89) at 0x250...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x86,0x86) at 0x250...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for Winbond Super I/O (init=0x87,0x87) at 0x250...
Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff
Probing for VIA Super I/O at 0x3f0...
PCI device 1106:0686 not found.
Probing for Server Engines Super I/O at 0x2e...
Failed. Returned data: id=0xffff, rev=0xff
No Super I/O found
 
### The Windows program "HWiNFO64" also showes that the Super-IO/LPC Chip is unknown.
 
 
------ output of "ectool"
 
EC RAM:
 
: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
: 10 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
: 00 00 08 1b 00 00 00 00 00 0a 02 00 23 00 7f 68 
a0: 00 00 01 07 00 00 03 00 00 00 00 00 00 00 00 00 
b0: 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 
c0: 00 62 67 2d 41 00 00 00 ff 03 00 41 01 00 00 36 
d0: 00 00 00 00 00 00 00 00 01 06 00 00 31 00 00 00 
e0: 7e 00 00 00 00 00 1e 00 00 00 00 00 00 00 00 00 
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
 
Not dumping EC IDX RAM.
 
### Concerning the Embedded Controller (EC) I could get some little information by the Windows tool "Rw
version 1.6" which might be usefull for an advanced technician. According to the information it's an EC6662.
 
 
------ output of "flashrom -V"
 
flashrom v0.9.5.2-r1517 on Linux 3.7.0-7-generic (x86_64), built with libpci 3.1.8, GCC 4.6.3, little endian
flashrom is free software, get the source code at http://www.flashrom.org
 
Calibrating delay loop... OS timer resolution is 1 usecs, 1989M loops per second, 10 myus = 10 us, 100 myus =
101 us, 1000 myus = 998 us, 10000 myus = 10162 us, 4 myus = 6 us, OK.
Initializing internal programmer
No coreboot table found.
DMI string system-manufacturer: "TOSHIBA"
DMI string system-product-name: "Satellite M110"
DMI string system-version: "PSMB0U-1234567"
DMI string baseboard-manufacturer: "Intel Corporation"
DMI string baseboard-product-name: "CAPELL VALLEY(NAPA) CRB"
DMI string baseboard-version: "Not Applicable"
DMI string chassis-type: "Other"
DMI chassis-type is not specific enough.
 
### I add here some part of the output from "dmidecode" as well with extracted information only about
relevant bios parameters. By "dmidecode" I could figure out that ROM Size is only 1024 kB:
 
Handle 0x0000, DMI type 0, 24 bytes
BIOS Information
    Vendor: Phoenix Technologies LTD
    Version: 6.00   
    Release Date: 07/12/2007
    Address: 0xE4480
    Runtime Size: 113536 bytes
    ROM Size: 1024 kB
    Characteristics:
        ISA is supported
        PCI is supported
        PC Card (PCMCIA) is supported
        PNP is supported
        APM is supported
        BIOS is upgradeable
        BIOS shadowing is allowed
        ESCD support is available
        Boot from CD is supported
        ACPI is supported
        USB legacy is supported
        AGP is supported
        BIOS boot specification is supported
        Targeted content distribution is supported
 
 
------ URL to the mainboard specifications page:
http://www.toshiba.de/discontinued-products/satellite-a100-151/?PRODUCT_ID=114071
 
### Unfortunately, I could only find this German website. But I have access to the manual. However, it does
not provide much additional information which would be usefull here.
 
 
 
------ Any other relevant information:
 
As I have mentioned before, I have upgraded my system including a new CPU (Intel Core2Duo T7200), more RAM (2
x 2GB, identical and  from the same vendor) and a SSD. Furthermore I have flashed a modded custom bios
which has enabled some more features and seems to work perfectly untill now. However, after the bios mod
the model name has been changed. 
 
 
To end with, I would like to say thank you for your commitment concerning this great open source projet and
especially for reading my long message! As I explained I am still a beginner, comming from a completely
different working field, but having some ambition to use open source software. I would appreciate your
support so that coreboot might natively run on my system.
 
--
With best regards,
Daniel
 
 

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AMD AGESA: How to access an indexed register?

Dear coreboot folks,

to read the value of the BIOS Timer (section 2.11.4 of the BIOS and
Kernel Developer’s Guide (BKDG) for the AMD Family 14 processors [1]), I
am stuck at how to do that.

Below is the register description from the BKDG.

        D0F0xE4_x0130_80F0 BIOS Timer
        -----------------------------
        Reset: 0000_0000h.
        -----------------------------
        Bits
                31:0
        Description
                MicroSeconds. Read-write; updated-by hardware. This
                field increments once every microsecond when the timer
                is enabled. The counter rolls over and continues
                counting when it reaches FFFF_FFFFh. A write to this
                register causes the counter to reset and begin counting
                from the value written.

I could not find any wrapper(?) function in the non-vendor code for
that. In the vendor code directory `src/vendorcode/amd/agesa/f14/`, I
found only `PcieRegisterRead`, which looks “hard” to access from
outside.

        $ git grep -i iocf8
        $ git grep -i d0f0xe4 src/vendorcode/amd/agesa/f14

Any pointers to code already dealing with such indexed registers or
instructions how to do that would help me very much.

Thanks,

Paul

[1] http://www.coreboot.org/Datasheets#AMD_Fam14
    BKDG 43170 Rev 3.13 – February 17, 2012

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Use the constant TSC for AMD Family 10h–15h processors?

Dear coreboot folks,

do you know if the timer mentioned in the BIOS and Kernel Developer’s
Guide (BKGD) for the AMD Family 14h processors [1]

        2.11.4 BIOS Timer

        The root complex implements a 32-bit microsecond timer (see
        D0F0xE4_x0130_80F0 and D0F0xE4_x0130_80F1) that the BIOS can use
        to accurately time wait operations between initialization steps.
        To ensure that BIOS waits a minimum number of microseconds
        between steps BIOS should always wait for one microsecond more
        than the required minimum wait time.

could be used for implementing `tsc_freq_mhz()` as done for Intel
Haswell processors?

The Wikipedia article for Time Stamp Counter (TSC) claims that since AMD
family 10h processors a constant TSC is integrated [2]. Indeed, checking
the processor flags under GNU/Linux, the flag `tsc_constant` is present.

        $ grep -i tsc /proc/cpuinfo 
        flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht
syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc nonstop_tsc extd_apicid aperfmperf pni
monitor ssse3 cx16 popcnt lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse
3dnowprefetch ibs skinit wdt arat hw_pstate npt lbrv svm_lock nrip_save pausefilter
        flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht
syscall nx mmxext fxsr_opt pdpe1gb rdtscp lm constant_tsc nonstop_tsc extd_apicid aperfmperf pni
monitor ssse3 cx16 popcnt lahf_lm cmp_legacy svm extapic cr8_legacy abm sse4a misalignsse
3dnowprefetch ibs skinit wdt arat hw_pstate npt lbrv svm_lock nrip_save pausefilter

Suggestions, if this should be shared and how the files should be named
are appreciated.

Thanks,

Paul

[1] http://review.coreboot.org/3169
[2] http://www.coreboot.org/Datasheets#AMD_Fam14
[3] http://en.wikipedia.org/wiki/Time_Stamp_Counter#Implementation_in_various_processors

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Tree broken: ASUS M4A785T-M and PC Engines ALIX.1C fail to build

Dear coreboot folks,

since yesterday the tree is broken [1] due to merging the following
commits [2][3] without their dependencies as they were not pushed as a
branch [4].

        commit b8b3e8bff32ee7dddcacec11e015f6683783eb2f
        Author: Denis 'GNUtoo' Carikli <GNUtoo <at> no-log.org>
        Date:   Thu May 9 16:14:59 2013 +0200

            Asus M4A785T-M: Add CMOS defaults.

        commit f90071faeee3358748d0c8d31e46721b53241e28
        Author: Denis 'GNUtoo' Carikli <GNUtoo <at> no-log.org>
        Date:   Thu May 9 23:35:18 2013 +0200

            PC Engines ALIX.1C: Add CMOS defaults.

The following two boards fail to build [1].

    board.i386/asus/m4a785t-m
    board.i386/pcengines/alix1c

Could the two commits be reverted as it does not look like that [4] is
going to be approved soon.

Thanks,

Paul

[1] http://qa.coreboot.org/job/coreboot-gerrit/6251/
[2] http://review.coreboot.org/#/c/3224/
[3] http://review.coreboot.org/#/c/3229/
[4] http://review.coreboot.org/#/c/3223/

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How to set different defaults for Kconfig values like `CONFIG_USBDEBUG_DEFAULT_PORT`

Dear coreboot folks,

looking at how to split up the patch for the Lenovo X201 southbridge
support [1],

        commit 92ba16cf9fabcf478c225dff687ae717666b502d
        Author: Vladimir Serbinenko <phcoder <at> gmail.com>
        Date:   Sun Mar 31 22:22:10 2013 +0200

            intel/bd82x6x: Support mobile 5 southbridge

I stumbled over `CONFIG_USBDEBUG_DEFAULT_PORT`.

        $ git describe
        4.0-3936-g92ba16c
        $ git grep -A3 USBDEBUG_DEFAULT_PORT
        src/console/Kconfig:config USBDEBUG_DEFAULT_PORT
        src/console/Kconfig-    int "Default USB port to use as Debug Port"
        src/console/Kconfig-    default 1
        src/console/Kconfig-    depends on USBDEBUG && !SOUTHBRIDGE_INTEL_I82801GX && !SOUTHBRIDGE_AMD_SB600
        --
        src/console/console.c:  enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
        src/console/console.c-  early_usbdebug_init();
        src/console/console.c-#endif
        src/console/console.c-#if CONFIG_CONSOLE_SERIAL
        --
        src/southbridge/amd/sb600/Kconfig:config USBDEBUG_DEFAULT_PORT
        src/southbridge/amd/sb600/Kconfig-      int
        src/southbridge/amd/sb600/Kconfig-      default 0
        src/southbridge/amd/sb600/Kconfig-
        --
        src/southbridge/intel/bd82x6x/Kconfig:config USBDEBUG_DEFAULT_PORT
        src/southbridge/intel/bd82x6x/Kconfig-  int
        src/southbridge/intel/bd82x6x/Kconfig-  default 2
        src/southbridge/intel/bd82x6x/Kconfig-
        --
        src/southbridge/intel/i82801gx/Kconfig:config USBDEBUG_DEFAULT_PORT
        src/southbridge/intel/i82801gx/Kconfig- int
        src/southbridge/intel/i82801gx/Kconfig- default 1
        src/southbridge/intel/i82801gx/Kconfig-
        --
        src/southbridge/intel/i82801ix/Kconfig:config USBDEBUG_DEFAULT_PORT
        src/southbridge/intel/i82801ix/Kconfig- int
        src/southbridge/intel/i82801ix/Kconfig- default 1
        src/southbridge/intel/i82801ix/Kconfig-

1. Is there an easier way to handle this? I assume the complexity is due
to the fact, that boards have different defaults?

Is default

        default 1
        default 0 if SOUTHBRIDGE_AMD_SB600

a shorter alternative?

2. The other thing is probably under what menu item this option is
displayed at. If under Console or Chipset.

Do you have other suggestions? Shall I prepare a commit to change the
code as suggested above?

Thanks,

Paul

[1] http://review.coreboot.org/#/c/2995/

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