scan-admin | 24 Nov 19:58 2014

New Defects reported by Coverity Scan for coreboot


Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan.

5 new defect(s) introduced to coreboot found with Coverity Scan.
9 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan.

New defect(s) Reported-by: Coverity Scan
Showing 5 of 5 defect(s)

** CID 1255946:  Out-of-bounds access  (ARRAY_VS_SINGLETON)
/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c: 155 in ConfigureDefaultUpdData()

** CID 1255945:  Dereference null return value  (NULL_RETURNS)
/coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 98 in LocateModule()

** CID 1255944:  Dereference null return value  (NULL_RETURNS)
/src/northbridge/amd/pi/00730F01/dimmSpd.c: 37 in AmdMemoryReadSPD()

** CID 1255943:  Dereference null return value  (NULL_RETURNS)
/src/cpu/amd/pi/s3_resume.c: 164 in move_stack_high_mem()

** CID 1255942:  Unused value  (UNUSED_VALUE)
/src/drivers/usb/ehci_debug.c: 573 in usbdebug_init_()

*** CID 1255946:  Out-of-bounds access  (ARRAY_VS_SINGLETON)
/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c: 155 in ConfigureDefaultUpdData()
149     			case MIPI_DEV_FUNC:	/* Camera / Image Signal Processing */
(Continue reading)

Gailu Singh | 24 Nov 13:59 2014

How to get coreboot debug prints during suspend resume

Hi Experts,

Is it possible to get coreboot debug prints during suspend/resume?

Best Regards


coreboot mailing list: coreboot <at>
Gailu Singh | 24 Nov 12:34 2014

WOL/PCI PME wakeup from S3 Baytrail SoC (Bayleybay CRB)

Hi Experts,

I have PCIe card that supports wake on lan and it works fine with BIOS. On sending magic packet System wakes up from S3.

However If I use same Linux image with coreboot wake from PCI device does not wake the system. System wakes up from S3 using power button only.

I suspected the problem with dsdt and took dsdt binary from bios setup, disassembled it and replaced dsdt.asl in coreboot with the one from bios to match dsdt configuration. Now my dsdt and linux image are same but still system does not wake from PCI PME (WOL) in coreboot but works fine with bios.

In both cases wakeup is enabled in /sys/bus/pci/devices/0000\:01\:00.0/power/wakeup

Can you please advise what else could be the problem?

PME signal is connected to GPIOS5 on the SoC.

Best Regards


coreboot mailing list: coreboot <at>
Antoine PLANTY | 22 Nov 18:15 2014

Coreboot on a thinkpad x300


Since I saw on the product list that the thinkpad x300 wasn't  supported and you advised to send an e-mail here it :

-Thinkpad X300 :
CPU : Intel C2D SL7100 (merom)
North Bridge: Crestline_SFF
South Bridge: ICH8M SFF

I've included the output of lscpi, flashrom, superiotool aswell as the X300 schematics in the archive.

Best regards,
Attachment (x300.tar.gz): application/gzip, 1196 KiB

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Vincent Pelletier | 23 Nov 17:35 2014

Donating hardware


(please keep me CC'ed, I'm not subscribed)

I am getting rid of two old motherboards and would like to donate them
to coreboot.

Both cards are ASUS:
- M2N32-SLI deluxe
- M5A88-V EVO

Any dev interested ?
Questions welcome.

Vincent Pelletier


coreboot mailing list: coreboot <at>


Infrastructure work

Hello, all. I know I've signed up to fix board-status and cmos but I
don't want to go through painful reviews, so I'm not going to do this,
even though maintaining current CMOS stuff is a pain in itself.


coreboot mailing list: coreboot <at>
The Gluglug | 21 Nov 06:03 2014

cbfstool build issue in gcc 4.6.3


cbfs-mkstage.c: In function ‘is_phdr_ignored’:
cbfs-mkstage.c:45:84: error: cast to pointer from integer of different
size [-Werror=int-to-pointer-cast]

The fix was made in but some
people were unhappy about the use of extra type casting.

One possible solution is to simply upgrade GCC, which I will, but I
would also like to get cbfstool to build again for this version of
GCC. The patch in the gerrit link works, but is not accepted for

Does anyone know a better way of doing it?

Francis Rowe.
Gailu Singh | 19 Nov 20:36 2014

Memory corruption on Resume from S3 Baytrail

Hi Experts,

I am using Baytrail SoC board (Bayleybay CRB) and testing suspend/resume from Linux (kernel 3.10). I can suspend with pm-suspend and resume with power button; however after resuming I get following logs in Linux
Corrupted low memory at c0001004 (1004 phys) = 0008eaea
Corrupted low memory at c0001008 (1008 phys) = b0606600
Corrupted low memory at c00018fc (18fc phys) = 000008ea

This seems to be caused by coreboot as I do not see these logs if I use BIOS instead of coreboot.
Is it true that during resume coreboot uses RAM portion already mapped by Linux and thus corrupting it. How to I avoid the RAM conflict?


coreboot mailing list: coreboot <at>
The Gluglug | 19 Nov 10:42 2014


What systems in coreboot use intel ME 4 and which ones use ME 5?
(I know X200 uses ME4 already.)

ROSA MARIA LOPEZ ROBLES | 17 Nov 12:08 2014

Re: coreboot Digest, Vol 117, Issue 28

De: coreboot [coreboot-bounces <at>] en nom de coreboot-request <at> [coreboot-request <at>]
Enviat el: dilluns, 17 / novembre / 2014 12:00
Per a: coreboot <at>
Tema: coreboot Digest, Vol 117, Issue 28

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Today's Topics:

   1. vortex86ex (The Gluglug)


Message: 1
Date: Sun, 16 Nov 2014 23:38:41 +0000
From: The Gluglug <info <at>>
To: coreboot <at>
Subject: [coreboot] vortex86ex
Message-ID: <54693581.4060205 <at>>
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Does anyone have a vortex86ex board with coreboot?
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End of coreboot Digest, Vol 117, Issue 28

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The Gluglug | 17 Nov 00:38 2014


Does anyone have a vortex86ex board with coreboot?