Vitor Augusto | 12 Apr 03:04 2014
Picon

Fans and BIOS

Hello.

I'm searching for any information about where (memory, IO port, etc.)
the status (on or off) of the fans of a laptop are stored. Anything is
very welcome! This is to improve the compatibility of i8kutils package
at Linux. The site of the development is
"https://launchpad.net/i8kutils".

Thanks in advance.

Vitor Augusto

--

-- 
coreboot mailing list: coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

HacKurx | 14 Apr 15:44 2014
Picon

ASRock E350M1 start automatically after a electric cut

Hi,

My E350M1 start automatically after a electric cut. I tested this in
the hope but I get the same result:
http://review.coreboot.org/#/c/5397/

I do not have this problem with the manufacturer bios. Does watchdog
is used by default? Do you have an idea or solution?

Thanks, best regards

--

-- 
coreboot mailing list: coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

mad | 12 Apr 21:49 2014
Picon

Thinkpad X61

Hi!

Does some have the X61 running with coreboot and can provide help to a
beginner (config, images, ...)?

I read the X60 wiki articles and there is a X61 mentioned as a
reference. But the actual chips seem to differ very much.

TIA
mad

--

-- 
coreboot mailing list: coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

mrnuke | 12 Apr 21:14 2014
Picon

So, you want to try coreboot? Here are a few hints

Installing coreboot can be an either enthralling or appalling experience. If 
you're new to coreboot and want to give it a try, following a few simple steps 
can save you a ton of time and frustration.

Ask around first
================

Let the "coreboot people" know you want to try coreboot on board 'xyz'. You 
may find someone with the same board, who may be able to give you hints on 
flashing. This is especially useful on laptops, where a brick will most likely 
result in the need for disassembly to access the flash chip, and external 
flashing.

Prebuilt images
===============

If you're lucky enough to find someone with the same board as you, they may be 
able to provide a pre-built coreboot image. This eliminates issues where 
flashing is done correctly, but a mysterious bug prevents the system for 
booting.

Binary coreboot distributions
=============================

Sometimes people get together and create tested binaries binaries for a subset 
of boards. They can give you help on flashing, and making sure your board 
works as expected. This is by far the best way to try coreboot.

If you have a Lenovo X60, give the libreboot[1] guys a holler. That's libre-
boot, not lib-reboot.
(Continue reading)

Paul Menzel | 10 Apr 09:45 2014
Picon
Picon

Re: Questions about EC and keyboard layout in Google Parrot

Dear David,

thank you for your reply.

Am Mittwoch, den 09.04.2014, 21:07 -0700 schrieb David Hendricks:
> On Wed, Apr 9, 2014 at 1:52 PM, Paul Menzel wrote:

> > Google Parrot (Acer C7 Chromebook) has the following in
> > `src/mainboard/google/parrot/ec.c` [1].
> >
> >     52          /* US Keyboard */
> >     53          ec_kbc_write_cmd(0x59);
> >     54          ec_kbc_write_ib(0xE5);
> >
> > If the comment is correct, this is surprising to me in two ways:
> >
> > 1. Normally such things are the payload’s or operating system’s job.
> 
> In this case, it's telling the EC how to interpret keystrokes it sees on
> the physical key matrix. For example, pressing a key which asserts a
> particular column and shorts a particular row will generate a particular
> keycode, which the EC translates into a byte that is sent to the host as a
> raw scancode.
> 
> From there, the payload or OS can define what the scancode actually means
> (e.g. which language encoding to use).
> 
> This depends on the particular keyboard matrix which is used with the
> system. We assume that the keyboard is non-replaceable on a laptop, so it
> makes sense to set this in firmware.
(Continue reading)

Paul Menzel | 9 Apr 22:52 2014
Picon
Picon

Questions about EC and keyboard layout in Google Parrot

Dear coreboot folks,

Google Parrot (Acer C7 Chromebook) has the following in
`src/mainboard/google/parrot/ec.c` [1].

    52		/* US Keyboard */
    53		ec_kbc_write_cmd(0x59);
    54		ec_kbc_write_ib(0xE5);

If the comment is correct, this is surprising to me in two ways:

1. Normally such things are the payload’s or operating system’s job.

2. The code is also used for Google Parrots with German keyboards.
Wouldn’t that cause conflicts?

Could somebody please enlighten me? I did not work with embedded
controllers yet and I am very interested how that all fits together.

Thanks,

Paul

[1] http://review.coreboot.org/2026
--

-- 
coreboot mailing list: coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Paul Menzel | 9 Apr 00:07 2014
Picon
Picon

[RFH] Reviewers wanted for HP Pavillion patch sets in Gerrit

Dear coreboot folks,

Alexandru is almost done with the HP Pavillion port and he submitted a
lot of patch sets waiting for review [1]. It would be great if you could
review them, so they can be submitted soon.

Thanks,

Paul

[1] http://review.coreboot.org/#/q/status:open+project:coreboot+branch:master+topic:pavilion/new_features,n,z
--

-- 
coreboot mailing list: coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
mrnuke | 8 Apr 04:05 2014
Picon

[proposal] EC-mainboard interaction at ASL level

This is an ugly one, and we keep having to find different workarounds to make 
this happen. We have the preprocessor, so why not use it?

Define a set of common ACPI method names which the mainboard code should 
define, and the EC code can always use.

* MB_TOGGLE_WLAN() or MB_TOGGLE_WIRELESS()
  Toggle wireless LAN on and off, or wireless LAN and bluetooth
  (respectively). EC calls this on hotkey events.

* MB_INCREASE_BRIGHTNESS() and MB_DECREASE_BRIGHTNESS()
  Increase or decrease screen brightness. EC calls this on hotkey events.

* MB_SWITCH_DISPLAY()
  Switch the active display. EC calls this on hotkey events.

* MB_NOTIFY_POWER_EVENT()
  Handle power state notifications and notify CPU device objects to re-
  evaluate their _PPC and _CST tables.

Of course, we would have the mainboard #define these to an existing method, we 
wouldn't really use these long method names in ASL. Another idea would be to 
standardize on four letter names, but those are not as clear, and hide the 
"MB_" which is there to indicate that the mainboard should provide those.

Notice that these methods are only called on hotkey events. As such, unless 
the user has really fast fingers, there isn't a huge ACPI overhead as opposed 
to setting/clearing the needed bits directly in the caller.

We then extend this to also include ACPI objects for different purposes.
(Continue reading)

mrnuke | 6 Apr 21:30 2014
Picon

AGESA (f15tn) AmdInitReset doing nasty things

It's changing the ROM base (devfn 14.3, register 0x6c) from 0xffc0 to 0xff00. 
The bootblock sets it up correctly, but AmdInitReset messes it up.

Any ideas? AGESA is particularly annoying to grep.

Alex

--

-- 
coreboot mailing list: coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

mrnuke | 5 Apr 19:03 2014
Picon

[HELP!!!] Pavilion EC (similar to compal/ene932) and its woes

So, in messing with this Pavilion m6_1935dx, I was able to get most of the EC 
running as expected. It seems that, at least the (ACPI) register layout is the 
same. We can get good battery _and_ AC indicators from it.

When we query the EC (say, doing a cat /sys/class/power/AC/online), it 
responds properly with an SCI whenever the status register changes, and the 
query goes well. And that's about it.

When an event happens, on the other hand, like a hotkey, or AC is removed, it 
does not generate an SCI that would lead to a query call (_Qxx). Instead it 
spits out an SMI. I know for a fact that the SCI and SMI GPEs are where we 
expect them to be.

I see google/parrot uses the same physical EC silicon, though the EC firmware 
may be a different beast. However, I'd like to ask of you gurus who have 
worked on parrot... what's your take on this?

Alex

More technical details:
I've made ACPI print a debug message whenever GPE23 is triggered (_L17). This 
is the EC SMI event.

I'm also using linux supermagic to get an idea of what is going on:
 # echo 0x88000502 > /sys/module/acpi/parameters/debug_level 
 # echo 0x00060006 > /sys/module/acpi/parameters/debug_layer 
 # echo -n 'file ec.c +p' | tee /sys/kernel/debug/dynamic_debug/control

That's how I know the GPE for SCI is correct (also same GPE in the vendor's 
ACPI).
(Continue reading)

mrnuke | 5 Apr 19:02 2014
Picon

[HELP!!!] Pavilion EC (similar to compal/ene932) and its woes

So, in messing with this Pavilion m6_1935dx, I was able to get most of the EC 
running as expected. It seems that, at least the (ACPI) register layout is the 
same. We can get good battery _and_ AC indicators from it.

When we query the EC (say, doing a cat /sys/class/power/AC/online), it 
responds properly with an SCI whenever the status register changes, and the 
query goes well. And that's about it.

When an event happens, on the other hand, like a hotkey, or AC is removed, it 
does not generate an SCI that would lead to a query call (_Qxx). Instead it 
spits out an SMI. I know for a fact that the SCI and SMI GPEs are where we 
expect them to be.

I see google/parrot uses the same physical EC silicon, though the EC firmware 
may be a different beast. However, I'd like to ask of you gurus who have 
worked on parrot... what's your take on this?

Alex

More technical details:
I've made ACPI print a debug message whenever GPE23 is triggered (_L17). This 
is the EC SMI event.

I'm also using linux supermagic to get an idea of what is going on:

--

-- 
coreboot mailing list: coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

(Continue reading)


Gmane