Picon

Infrastructure work

Hello, all. I know I've signed up to fix board-status and cmos but I
don't want to go through painful reviews, so I'm not going to do this,
even though maintaining current CMOS stuff is a pain in itself.

--

-- 
coreboot mailing list: coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
The Gluglug | 21 Nov 06:03 2014
Picon

cbfstool build issue in gcc 4.6.3


Hi,

cbfs-mkstage.c: In function ‘is_phdr_ignored’:
cbfs-mkstage.c:45:84: error: cast to pointer from integer of different
size [-Werror=int-to-pointer-cast]

The fix was made in http://review.coreboot.org/#/c/7545/ but some
people were unhappy about the use of extra type casting.

One possible solution is to simply upgrade GCC, which I will, but I
would also like to get cbfstool to build again for this version of
GCC. The patch in the gerrit link works, but is not accepted for
upstream.

Does anyone know a better way of doing it?

Regards,
Francis Rowe.
Gailu Singh | 19 Nov 20:36 2014
Picon

Memory corruption on Resume from S3 Baytrail

Hi Experts,

I am using Baytrail SoC board (Bayleybay CRB) and testing suspend/resume from Linux (kernel 3.10). I can suspend with pm-suspend and resume with power button; however after resuming I get following logs in Linux
Corrupted low memory at c0001004 (1004 phys) = 0008eaea
Corrupted low memory at c0001008 (1008 phys) = b0606600
...
Corrupted low memory at c00018fc (18fc phys) = 000008ea

This seems to be caused by coreboot as I do not see these logs if I use BIOS instead of coreboot.
Is it true that during resume coreboot uses RAM portion already mapped by Linux and thus corrupting it. How to I avoid the RAM conflict?


--

-- 
coreboot mailing list: coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
The Gluglug | 19 Nov 10:42 2014
Picon

ME4/5


What systems in coreboot use intel ME 4 and which ones use ME 5?
(I know X200 uses ME4 already.)

ROSA MARIA LOPEZ ROBLES | 17 Nov 12:08 2014

Re: coreboot Digest, Vol 117, Issue 28


________________________________________
De: coreboot [coreboot-bounces <at> coreboot.org] en nom de coreboot-request <at> coreboot.org [coreboot-request <at> coreboot.org]
Enviat el: dilluns, 17 / novembre / 2014 12:00
Per a: coreboot <at> coreboot.org
Tema: coreboot Digest, Vol 117, Issue 28

Send coreboot mailing list submissions to
        coreboot <at> coreboot.org

To subscribe or unsubscribe via the World Wide Web, visit
        http://www.coreboot.org/mailman/listinfo/coreboot

or, via email, send a message with subject or body 'help' to
        coreboot-request <at> coreboot.org

You can reach the person managing the list at
        coreboot-owner <at> coreboot.org

When replying, please edit your Subject line so it is more specific
than "Re: Contents of coreboot digest..."


Today's Topics:

   1. vortex86ex (The Gluglug)


----------------------------------------------------------------------

Message: 1
Date: Sun, 16 Nov 2014 23:38:41 +0000
From: The Gluglug <info <at> gluglug.org.uk>
To: coreboot <at> coreboot.org
Subject: [coreboot] vortex86ex
Message-ID: <54693581.4060205 <at> gluglug.org.uk>
Content-Type: text/plain; charset=utf-8

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1

Does anyone have a vortex86ex board with coreboot?
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)

iQEcBAEBAgAGBQJUaTV4AAoJEP9Ft0z50c+UgzwH/3/Jx914Y6e0pFTaSE256oxs
eKHigGpiMVpjseYCtMTK8ZulAIydvumY+jclwAzydY0P8IlcTW9teKF5JNxvnf0D
EyaOel/pbxhIexOzs/ei8ALSil3+fPIhC2rqVs00l0MrO5DvBwa/fxF4qjWbnuuW
KS+k68z2sLbD7UI+LDlJaj/ecZ1lzS/YaN1a7r2Wem1ZPda3ATjV0xMjFChvBkbo
kFauxuLeVlBxqJfhkRZijpFrD0cpljCL6LWn/738HZbzXGVlqqKsCQcMBtcUsiEq
o8yEI97BesJfXvFGXPsw05swoWxrVF/yJDR8ALM9Dy7Uabqumg/vhRK95EHbtF0=
=g3MX
-----END PGP SIGNATURE-----



------------------------------

Subject: Digest Footer

_______________________________________________
coreboot mailing list
coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot


------------------------------

End of coreboot Digest, Vol 117, Issue 28
*****************************************


Aquest correu electrònic i els annexos poden contenir informació confidencial o protegida legalment i
està adreçat exclusivament a la persona o entitat destinatària. Si no sou el destinatari final o la
persona encarregada de rebre’l, no esteu autoritzat a llegir-lo, retenir-lo, modificar-lo,
distribuir-lo, copiar-lo ni a revelar-ne el contingut. Si heu rebut aquest correu electrònic per
error, us preguem que n’informeu al remitent i que elimineu del sistema el missatge i el material annex
que pugui contenir. Gràcies per la vostra col·laboració.

Este correo electrónico y sus anexos pueden contener información confidencial o legalmente protegida
y está exclusivamente dirigido a la persona o entidad destinataria. Si usted no es el destinatario final
o la persona encargada de recibirlo, no está autorizado a leerlo, retenerlo, modificarlo,
distribuirlo, copiarlo ni a revelar su contenido. Si ha recibido este mensaje electrónico por error, le
rogamos que informe al remitente y elimine del sistema el mensaje y el material anexo que pueda contener.
Gracias por su colaboración.

This email message and any documents attached to it may contain confidential or legally protected
material and are intended solely for the use of the individual or organization to whom they are addressed.
We remind you that if you are not the intended recipient of this email message or the person responsible for
processing it, then you are not authorized to read, save, modify, send, copy or disclose any of its
contents. If you have received this email message by mistake, we kindly ask you to inform the sender of this
and to eliminate both the message and any attachments it carries from your account. Thank you for your collaboration.
--

-- 
coreboot mailing list: coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
The Gluglug | 17 Nov 00:38 2014
Picon

vortex86ex


Does anyone have a vortex86ex board with coreboot?
Gailu Singh | 16 Nov 19:03 2014
Picon

USB keyboard wakeup from S3 Baytrail: Bayley Bay CRB

Hi Experts,

I am trying to use ACPI_RESUME functionality of coreboot on Bayley Bay CRB and unable to wakeup board with USB Keyboard. Board resumes with power button only. Below is the detailed description.

1. I am using EHCI instead of XHCI as I need to support boot from USB in grub.
2. Enabled S3 support in coreboot File: src/soc/intel/fsp_baytrail/acpi/usb.asl, Chnage: Name (_PRW, Package(){ 13, 3 })
3. Linux Kernel Version: 3.10

In Linux I see following in /proc/acpi/wakeup
root <at> localhost:~# cat /proc/acpi/wakeup
Device  S-state   Status   Sysfs node
EHC1      S3    *enabled   pci:0000:00:1d.0
XHCI      S3    *disabled

When I plugin USB keyboard following are logs
root <at> localhost:~# usb 1-1.2: new low-speed USB device number 3 using ehci-pci
input: SIGMACHIP USB Keyboard as /devices/pci0000:00/0000:00:1d.0/usb1/1-1/1-1.2/1-1.2:1.0/input/input3
hid-generic 0003:1C4F:0016.0001: input: USB HID v1.10 Keyboard [SIGMACHIP USB Keyboard] on usb-0000:00:1d.0-1.2/input0
input: SIGMACHIP USB Keyboard as /devices/pci0000:00/0000:00:1d.0/usb1/1-1/1-1.2/1-1.2:1.1/input/input4
hid-generic 0003:1C4F:0016.0002: input: USB HID v1.10 Device [SIGMACHIP USB Keyboard] on usb-0000:00:1d.0-1.2/input1

Based on above information I tried to enable wakeup from USB keyboard as follows
echo enabled > /sys/devices/pci0000\:00/0000\:00\:1d.0/usb1/power/wakeup
echo enabled > /sys/bus/usb/devices/1-1/power/wakeup

Still see the same entried in /proc/acpi/wakeup
root <at> localhost:~# cat /proc/acpi/wakeup
Device  S-state   Status   Sysfs node
EHC1      S3    *enabled   pci:0000:00:1d.0
XHCI      S3    *disabled

Did pm-suspend. Following are the logs
root <at> localhost:~# pm-suspend
ata2.00: configured for UDMA/100
ata2: EH complete
PM: Syncing filesystems ... done.
Freezing user space processes ... (elapsed 0.01 seconds) done.
Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done.
Suspending console(s) (use no_console_suspend to debug)

At this stage power to USB keyboard is off. No LED for Capslock. Nothing happens when I press any key on the keyboard.

System resumes with power button with the following logs.
POST: 0x76
Finalize devices...
DOMAIN: 0000 final
FspNotify(EnumInitPhaseAfterPciEnumeration)
Devices finalized
BS: BS_POST_DEVICE times (us): entry 0 run 12389 exit 0
POST: 0x77
Trying to find the wakeup vector...
Looking on 000f0000 for valid checksum
Checksum 1 passed
Checksum 2 passed all OK
RSDP found at 000f0000
RSDT found at 7add7030 ends at 7add7068
FADT found at 7add9cf0
FACS found at 7add7210
OS waking vector is 0009c090
BS: BS_OS_RESUME_CHECK times (us): entry 0 run 26951 exit 0
POST: 0x78
Restore GNVS pointer to 0x7adfb000
POST: 0xfd

sd 1:0:0:0: [sda] Synchronizing SCSI cache
sd 1:0:0:0: [sda] Stopping disk
PM: suspend of devices complete after 601.507 msecs
------------[ cut here ]------------
WARNING: at /home/linux/3.10-r0/linux/drivers/clk/clk.c:842 __clk_disable+0x50/0x70()
Modules linked in:
CPU: 1 PID: 453 Comm: pm-suspend Not tainted 3.10.38 #1
Hardware name: Intel Bayley Bay CRB/Bayley Bay CRB, BIOS 4.0-7016-g0a66991-dirty 11/15/2014
 00000000 00000000 f407de08 c181ea2c f407de30 c1036c7e c1a1541d c1a80588
 0000034a c16ca130 c16ca130 f4d89420 f4d89420 c13d8bf0 f407de40 c1036d42
 00000009 00000000 f407de4c c16ca130 00000246 f407de5c c16ca22a f4d89420
Call Trace:
 [<c181ea2c>] dump_stack+0x16/0x18
 [<c1036c7e>] warn_slowpath_common+0x5e/0x80
 [<c16ca130>] ? __clk_disable+0x50/0x70
 [<c16ca130>] ? __clk_disable+0x50/0x70
 [<c13d8bf0>] ? dw_pci_resume_early+0x20/0x20
 [<c1036d42>] warn_slowpath_null+0x22/0x30
 [<c16ca130>] __clk_disable+0x50/0x70
 [<c16ca22a>] clk_disable+0x1a/0x30
 [<c13d7ca0>] dw_dma_suspend+0x20/0x30
 [<c13d8c02>] dw_pci_suspend_late+0x12/0x20
 [<c149f1bb>] dpm_run_callback.isra.3+0x2b/0x70
 [<c1823d37>] ? _raw_spin_unlock_irq+0x17/0x40
 [<c149f79d>] dpm_suspend_end+0x4d/0x490
 [<c1079598>] suspend_devices_and_enter+0xf8/0x440
 [<c181a528>] ? printk+0x50/0x52
 [<c1079a90>] pm_suspend+0x1b0/0x220
 [<c1078aab>] state_store+0x5b/0xb0
 [<c1078a50>] ? wakeup_count_show+0x50/0x50
 [<c1355997>] kobj_attr_store+0x17/0x30
 [<c11905bb>] sysfs_write_file+0x9b/0x110
 [<c1190520>] ? sysfs_open_file+0x1f0/0x1f0
 [<c113aea9>] vfs_write+0x99/0x190
 [<c113b481>] SyS_write+0x51/0x90
 [<c182a5be>] sysenter_do_call+0x12/0x12
---[ end trace d63a3167b6ae1b8f ]---
------------[ cut here ]------------
WARNING: at /home/linux/3.10-r0/linux/drivers/clk/clk.c:751 __clk_unprepare+0x50/0x70()
Modules linked in:
CPU: 1 PID: 453 Comm: pm-suspend Tainted: G        W    3.10.38 #1
Hardware name: Intel Bayley Bay CRB/Bayley Bay CRB, BIOS 4.0-7016-g0a66991-dirty 11/15/2014
 00000000 00000000 f407de0c c181ea2c f407de34 c1036c7e c1a1541d c1a80588
 000002ef c16cab60 c16cab60 f4d89420 f4c4c064 c13d8bf0 f407de44 c1036d42
 00000009 00000000 f407de50 c16cab60 f4d89420 f407de5c c16cab97 f4d89420
Call Trace:
 [<c181ea2c>] dump_stack+0x16/0x18
 [<c1036c7e>] warn_slowpath_common+0x5e/0x80
 [<c16cab60>] ? __clk_unprepare+0x50/0x70
 [<c16cab60>] ? __clk_unprepare+0x50/0x70
 [<c13d8bf0>] ? dw_pci_resume_early+0x20/0x20
 [<c1036d42>] warn_slowpath_null+0x22/0x30
 [<c16cab60>] __clk_unprepare+0x50/0x70
 [<c16cab97>] clk_unprepare+0x17/0x20
 [<c13d7ca7>] dw_dma_suspend+0x27/0x30
 [<c13d8c02>] dw_pci_suspend_late+0x12/0x20
 [<c149f1bb>] dpm_run_callback.isra.3+0x2b/0x70
 [<c1823d37>] ? _raw_spin_unlock_irq+0x17/0x40
 [<c149f79d>] dpm_suspend_end+0x4d/0x490
 [<c1079598>] suspend_devices_and_enter+0xf8/0x440
 [<c181a528>] ? printk+0x50/0x52
 [<c1079a90>] pm_suspend+0x1b0/0x220
 [<c1078aab>] state_store+0x5b/0xb0
 [<c1078a50>] ? wakeup_count_show+0x50/0x50
 [<c1355997>] kobj_attr_store+0x17/0x30
 [<c11905bb>] sysfs_write_file+0x9b/0x110
 [<c1190520>] ? sysfs_open_file+0x1f0/0x1f0
 [<c113aea9>] vfs_write+0x99/0x190
 [<c113b481>] SyS_write+0x51/0x90
 [<c182a5be>] sysenter_do_call+0x12/0x12
---[ end trace d63a3167b6ae1b90 ]---
PM: late suspend of devices complete after 0.999 msecs
ehci-pci 0000:00:1d.0: System wakeup enabled by ACPI
PM: noirq suspend of devices complete after 33.501 msecs
ACPI: Preparing to enter system sleep state S3
PM: Saving platform NVS memory
Disabling non-boot CPUs ...
Broke affinity for irq 104
smpboot: CPU 1 is now offline
ACPI: Low-level resume complete
PM: Restoring platform NVS memory
Enabling non-boot CPUs ...
smpboot: Booting Node 0 Processor 1 APIC 0x4
Initializing CPU#1
Intel pstate controlling: cpu 1
CPU1 is up
ACPI: Waking up from system sleep state S3
ehci-pci 0000:00:1d.0: System wakeup disabled by ACPI
PM: noirq resume of devices complete after 187.013 msecs
PM: early resume of devices complete after 0.315 msecs
ata1: SATA link down (SStatus 0 SControl 300)
ata2: SATA link up 3.0 Gbps (SStatus 123 SControl 300)
ata2.00: configured for UDMA/100
sd 1:0:0:0: [sda] Starting disk
PM: resume of devices complete after 2046.412 msecs
Restarting tasks ... done.
ata2.00: configured for UDMA/100
ata2: EH complete
root <at> localhost:~#

Any idea what do I need to enable USB keyboard wakeup





--

-- 
coreboot mailing list: coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
scan-admin | 16 Nov 00:18 2014

New Defects reported by Coverity Scan for coreboot


Hi,

Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan.

17 new defect(s) introduced to coreboot found with Coverity Scan.
5 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by Coverity Scan.

New defect(s) Reported-by: Coverity Scan
Showing 17 of 17 defect(s)

** CID 1254658:  Out-of-bounds access  (ARRAY_VS_SINGLETON)
/coreboot-builds/amd_olivehillplus/agesa/amdlib.c: 1407 in IdsErrorStop()

** CID 1254657:  Unchecked return value  (CHECKED_RETURN)
/src/cpu/amd/car/post_cache_as_ram.c: 107 in post_cache_as_ram()

** CID 1254659:  Operands don't affect result  (CONSTANT_EXPRESSION_RESULT)
/src/soc/nvidia/tegra124/sor.c: 555 in tegra_dc_sor_config_panel()

** CID 1254652:  Logically dead code  (DEADCODE)
/src/northbridge/amd/agesa/00730F01/northbridge.c: 1067 in cpu_bus_scan()

** CID 1254650:  Division or modulo by zero  (DIVIDE_BY_ZERO)
/src/northbridge/amd/agesa/00730F01/northbridge.c: 1067 in cpu_bus_scan()
/src/northbridge/amd/agesa/00730F01/northbridge.c: 1067 in cpu_bus_scan()

** CID 1254656:  Missing break in switch  (MISSING_BREAK)
/src/soc/nvidia/tegra124/sor.c: 768 in tegra_dc_sor_power_down_unused_lanes()

** CID 1254653:  Out-of-bounds read  (OVERRUN)
/coreboot-builds/amd_olivehillplus/agesa/amdlib.c: 1407 in IdsErrorStop()

** CID 1254646:  Uninitialized pointer read  (UNINIT)
/src/ec/google/chromeec/ec.c: 104 in google_chromeec_check_ec_image()

** CID 1254655:  Uninitialized pointer read  (UNINIT)
/src/ec/google/chromeec/ec.c: 143 in google_chromeec_get_board_version()

** CID 1254654:  Structurally dead code  (UNREACHABLE)
/coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 554 in ImcDisableSurebootTimer()

** CID 1254649:  Structurally dead code  (UNREACHABLE)
/coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 491 in ImcSleep()

** CID 1254645:  Structurally dead code  (UNREACHABLE)
/coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 575 in ImcWakeup()

** CID 1254648:  Structurally dead code  (UNREACHABLE)
/coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 470 in WaitForEcLDN9MailboxCmdAck()

** CID 1254651:  Structurally dead code  (UNREACHABLE)
/coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 400 in AmdIdsRunApTaskLate()

** CID 1254644:  Structurally dead code  (UNREACHABLE)
/coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 533 in ImcEnableSurebootTimer()

** CID 1254643:  Structurally dead code  (UNREACHABLE)
/coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 512 in SoftwareDisableImc()

** CID 1254647:  Structurally dead code  (UNREACHABLE)
/coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 596 in ImcIdle()

________________________________________________________________________________________________________
*** CID 1254658:  Out-of-bounds access  (ARRAY_VS_SINGLETON)
/coreboot-builds/amd_olivehillplus/agesa/amdlib.c: 1407 in IdsErrorStop()
1401     	} post = {0xDEAD, FileCode, 0xDEAD, FileCode};
1402     	UINT16 offset = 0;
1403     	UINT16 j;
1404     
1405     	while(1) {
1406     		offset %= sizeof(struct POST) / 2;
>>>     CID 1254658:  Out-of-bounds access  (ARRAY_VS_SINGLETON)
>>>     Using "&post" as an array.  This might corrupt or misinterpret adjacent memory locations.
1407     		WriteIo32(80, *((UINT32*)(&post+offset)));
1408     		++offset;
1409     		for (j=0; j<250; ++j) {
1410     			ReadIo8(80);
1411     		}
1412     	}

________________________________________________________________________________________________________
*** CID 1254657:  Unchecked return value  (CHECKED_RETURN)
/src/cpu/amd/car/post_cache_as_ram.c: 107 in post_cache_as_ram()
101     {
102     	void *resume_backup_memory = NULL;
103     
104     	int s3resume = acpi_s3_resume_allowed() && acpi_is_wakeup_early();
105     	if (s3resume) {
106     #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
>>>     CID 1254657:  Unchecked return value  (CHECKED_RETURN)
>>>     Calling "cbmem_recovery" without checking return value (as is done elsewhere 18 out of 20 times).
107     		cbmem_recovery(s3resume);
108     		resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
109     #endif
110     	}
111     	prepare_romstage_ramstack(resume_backup_memory);
112     

________________________________________________________________________________________________________
*** CID 1254659:  Operands don't affect result  (CONSTANT_EXPRESSION_RESULT)
/src/soc/nvidia/tegra124/sor.c: 555 in tegra_dc_sor_config_panel()
549     		vblank_start << NV_HEAD_STATE4_VBLANK_START_SHIFT |
550     		hblank_start << NV_HEAD_STATE4_HBLANK_START_SHIFT);
551     
552     	/* TODO: adding interlace mode support */
553     	tegra_sor_writel(sor, NV_HEAD_STATE5(head_num), 0x1);
554     
>>>     CID 1254659:  Operands don't affect result  (CONSTANT_EXPRESSION_RESULT)
>>>     "(33554432 /* 2 << 24 */) | is_lvds" is always true regardless of the values of its operands. This occurs
as the logical first operand of '?:'.
555     	tegra_sor_write_field(sor, NV_SOR_CSTM,
556     		NV_SOR_CSTM_ROTCLK_DEFAULT_MASK |
557     		NV_SOR_CSTM_LVDS_EN_ENABLE,
558     		2 << NV_SOR_CSTM_ROTCLK_SHIFT |
559     		is_lvds ? NV_SOR_CSTM_LVDS_EN_ENABLE :
560     		NV_SOR_CSTM_LVDS_EN_DISABLE);

________________________________________________________________________________________________________
*** CID 1254652:  Logically dead code  (DEADCODE)
/src/northbridge/amd/agesa/00730F01/northbridge.c: 1067 in cpu_bus_scan()
1061                              */
1062     			if ((node_nums * core_max) + ioapic_count >= 0x10) {
1063     				lapicid_start = (ioapic_count - 1) / core_max;
1064     				lapicid_start = (lapicid_start + 1) * core_max;
1065     				printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
1066     			}
>>>     CID 1254652:  Logically dead code  (DEADCODE)
>>>     Execution cannot reach the expression "j + (siblings + 1)" inside this statement: "apic_id =
lapicid_start * (...".
1067     			u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
1068     			printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
1069     					i, j, apic_id);
1070     
1071     			device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
1072     			if (cpu)

________________________________________________________________________________________________________
*** CID 1254650:  Division or modulo by zero  (DIVIDE_BY_ZERO)
/src/northbridge/amd/agesa/00730F01/northbridge.c: 1067 in cpu_bus_scan()
1061                              */
1062     			if ((node_nums * core_max) + ioapic_count >= 0x10) {
1063     				lapicid_start = (ioapic_count - 1) / core_max;
1064     				lapicid_start = (lapicid_start + 1) * core_max;
1065     				printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
1066     			}
>>>     CID 1254650:  Division or modulo by zero  (DIVIDE_BY_ZERO)
>>>     In expression "i / modules", division by expression "modules" which may be zero has undefined behavior.
1067     			u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
1068     			printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
1069     					i, j, apic_id);
1070     
1071     			device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
1072     			if (cpu)
/src/northbridge/amd/agesa/00730F01/northbridge.c: 1067 in cpu_bus_scan()
1061                              */
1062     			if ((node_nums * core_max) + ioapic_count >= 0x10) {
1063     				lapicid_start = (ioapic_count - 1) / core_max;
1064     				lapicid_start = (lapicid_start + 1) * core_max;
1065     				printk(BIOS_SPEW, "lpaicid_start=0x%x ", lapicid_start);
1066     			}
>>>     CID 1254650:  Division or modulo by zero  (DIVIDE_BY_ZERO)
>>>     In expression "i % modules", modulo by expression "modules" which may be zero has undefined behavior.
1067     			u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j);
1068     			printk(BIOS_SPEW, "node 0x%x core 0x%x apicid=0x%x\n",
1069     					i, j, apic_id);
1070     
1071     			device_t cpu = add_cpu_device(cpu_bus, apic_id, enable_node);
1072     			if (cpu)

________________________________________________________________________________________________________
*** CID 1254656:  Missing break in switch  (MISSING_BREAK)
/src/soc/nvidia/tegra124/sor.c: 768 in tegra_dc_sor_power_down_unused_lanes()
762     		drive_current = 0x13131313;
763     		pre_emphasis = 0;
764     		break;
765     	case SOR_LINK_SPEED_G5_4:
766     		drive_current = 0x19191919;
767     		pre_emphasis = 0x09090909;
>>>     CID 1254656:  Missing break in switch  (MISSING_BREAK)
>>>     The above case falls through to this one.
768     	default:
769     		printk(BIOS_ERR, "Invalid sor link bandwidth: %d\n",
770     			sor->link_cfg->link_bw);
771     		return;
772     	}
773     
774     	tegra_sor_writel(sor, NV_SOR_LANE_DRIVE_CURRENT(sor->portnum),
775     				drive_current);
776     	tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), pre_emphasis);

________________________________________________________________________________________________________
*** CID 1254653:  Out-of-bounds read  (OVERRUN)
/coreboot-builds/amd_olivehillplus/agesa/amdlib.c: 1407 in IdsErrorStop()
1401     	} post = {0xDEAD, FileCode, 0xDEAD, FileCode};
1402     	UINT16 offset = 0;
1403     	UINT16 j;
1404     
1405     	while(1) {
1406     		offset %= sizeof(struct POST) / 2;
>>>     CID 1254653:  Out-of-bounds read  (OVERRUN)
>>>     Overrunning array of 3 4-byte elements at element index 15 (byte offset 60) by dereferencing pointer
"(UINT32 *)(&post + offset)".
1407     		WriteIo32(80, *((UINT32*)(&post+offset)));
1408     		++offset;
1409     		for (j=0; j<250; ++j) {
1410     			ReadIo8(80);
1411     		}
1412     	}

________________________________________________________________________________________________________
*** CID 1254646:  Uninitialized pointer read  (UNINIT)
/src/ec/google/chromeec/ec.c: 104 in google_chromeec_check_ec_image()
98     	return google_chromeec_get_mask(EC_CMD_HOST_EVENT_GET_B);
99     }
100     
101     #ifndef __SMM__
102     void google_chromeec_check_ec_image(int expected_type)
103     {
>>>     CID 1254646:  Uninitialized pointer read  (UNINIT)
>>>     Declaring variable "cec_cmd" without initializer.
104     	struct chromeec_command cec_cmd;
105     	struct ec_response_get_version cec_resp = {{0}};
106     
107     	cec_cmd.cmd_code = EC_CMD_GET_VERSION;
108     	cec_cmd.cmd_version = 0;
109     	cec_cmd.cmd_data_out = &cec_resp;

________________________________________________________________________________________________________
*** CID 1254655:  Uninitialized pointer read  (UNINIT)
/src/ec/google/chromeec/ec.c: 143 in google_chromeec_get_board_version()
137     		google_chromeec_check_ec_image(EC_IMAGE_RO);
138     	}
139     }
140     
141     u16 google_chromeec_get_board_version(void)
142     {
>>>     CID 1254655:  Uninitialized pointer read  (UNINIT)
>>>     Declaring variable "cmd" without initializer.
143     	struct chromeec_command cmd;
144     	struct ec_response_board_version board_v;
145     
146     	cmd.cmd_code = EC_CMD_GET_BOARD_VERSION;
147     	cmd.cmd_version = 0;
148     	cmd.cmd_size_in = 0;

________________________________________________________________________________________________________
*** CID 1254654:  Structurally dead code  (UNREACHABLE)
/coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 554 in ImcDisableSurebootTimer()
548       )
549     {
550     	MODULE_ENTRY Dispatcher = NULL;
551     	const AMD_MODULE_HEADER* module = LocateModule(ModuleIdentifier);
552     	((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0;
553     	return;
>>>     CID 1254654:  Structurally dead code  (UNREACHABLE)
>>>     This code cannot be reached: "if (!module)
  return;".
554     	if (!module) return;
555     	Dispatcher = module->ModuleDispatcher;
556     	Dispatcher(FchDataPtr);
557     }
558     
559     /**

________________________________________________________________________________________________________
*** CID 1254649:  Structurally dead code  (UNREACHABLE)
/coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 491 in ImcSleep()
485       )
486     {
487     	MODULE_ENTRY Dispatcher = NULL;
488     	const AMD_MODULE_HEADER* module = LocateModule(ModuleIdentifier);
489     	((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0;
490     	return;
>>>     CID 1254649:  Structurally dead code  (UNREACHABLE)
>>>     This code cannot be reached: "if (!module)
  return;".
491     	if (!module) return;
492     	Dispatcher = module->ModuleDispatcher;
493     	Dispatcher(FchDataPtr);
494     }
495     
496     /**

________________________________________________________________________________________________________
*** CID 1254645:  Structurally dead code  (UNREACHABLE)
/coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 575 in ImcWakeup()
569       )
570     {
571     	MODULE_ENTRY Dispatcher = NULL;
572     	const AMD_MODULE_HEADER* module = LocateModule(ModuleIdentifier);
573     	((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0;
574     	return;
>>>     CID 1254645:  Structurally dead code  (UNREACHABLE)
>>>     This code cannot be reached: "if (!module)
  return;".
575     	if (!module) return;
576     	Dispatcher = module->ModuleDispatcher;
577     	Dispatcher(FchDataPtr);
578     }
579     
580     /**

________________________________________________________________________________________________________
*** CID 1254648:  Structurally dead code  (UNREACHABLE)
/coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 470 in WaitForEcLDN9MailboxCmdAck()
464       )
465     {
466     	MODULE_ENTRY Dispatcher = NULL;
467     	const AMD_MODULE_HEADER* module = LocateModule(ModuleIdentifier);
468     	StdHeader->Func = 0;
469     	return;
>>>     CID 1254648:  Structurally dead code  (UNREACHABLE)
>>>     This code cannot be reached: "if (!module)
  return;".
470     	if (!module) return;
471     	Dispatcher = module->ModuleDispatcher;
472     	Dispatcher(StdHeader);
473     }
474     
475     /**

________________________________________________________________________________________________________
*** CID 1254651:  Structurally dead code  (UNREACHABLE)
/coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 400 in AmdIdsRunApTaskLate()
394       )
395     {
396     	MODULE_ENTRY Dispatcher = NULL;
397     	const AMD_MODULE_HEADER* module = LocateModule(ModuleIdentifier);
398     	AmdApExeParams->StdHeader.Func = -1;
399     	return AGESA_UNSUPPORTED;
>>>     CID 1254651:  Structurally dead code  (UNREACHABLE)
>>>     This code cannot be reached: "if (!module)
  return AGESA...".
400     	if (!module) return AGESA_UNSUPPORTED;
401     	Dispatcher = module->ModuleDispatcher;
402     	return Dispatcher(AmdApExeParams);
403     }
404     
405     /**********************************************************************

________________________________________________________________________________________________________
*** CID 1254644:  Structurally dead code  (UNREACHABLE)
/coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 533 in ImcEnableSurebootTimer()
527       )
528     {
529     	MODULE_ENTRY Dispatcher = NULL;
530     	const AMD_MODULE_HEADER* module = LocateModule(ModuleIdentifier);
531     	((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0;
532     	return;
>>>     CID 1254644:  Structurally dead code  (UNREACHABLE)
>>>     This code cannot be reached: "if (!module)
  return;".
533     	if (!module) return;
534     	Dispatcher = module->ModuleDispatcher;
535     	Dispatcher(FchDataPtr);
536     }
537     
538     /**

________________________________________________________________________________________________________
*** CID 1254643:  Structurally dead code  (UNREACHABLE)
/coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 512 in SoftwareDisableImc()
506       )
507     {
508     	MODULE_ENTRY Dispatcher = NULL;
509     	const AMD_MODULE_HEADER* module = LocateModule(ModuleIdentifier);
510     	((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0;
511     	return;
>>>     CID 1254643:  Structurally dead code  (UNREACHABLE)
>>>     This code cannot be reached: "if (!module)
  return;".
512     	if (!module) return;
513     	Dispatcher = module->ModuleDispatcher;
514     	Dispatcher(FchDataPtr);
515     }
516     
517     /**

________________________________________________________________________________________________________
*** CID 1254647:  Structurally dead code  (UNREACHABLE)
/coreboot-builds/amd_olivehillplus/agesa/AGESA.c: 596 in ImcIdle()
590       )
591     {
592     	MODULE_ENTRY Dispatcher = NULL;
593     	const AMD_MODULE_HEADER* module = LocateModule(ModuleIdentifier);
594     	((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0;
595     	return;
>>>     CID 1254647:  Structurally dead code  (UNREACHABLE)
>>>     This code cannot be reached: "if (!module)
  return;".
596     	if (!module) return;
597     	Dispatcher = module->ModuleDispatcher;
598     	Dispatcher(FchDataPtr);
599     }
600     
601     // TODO This has to be removed

________________________________________________________________________________________________________
To view the defects in Coverity Scan visit, http://scan.coverity.com/projects/1016?tab=overview

To unsubscribe from the email notification for new defects, http://scan5.coverity.com/cgi-bin/unsubscribe.py

--

-- 
coreboot mailing list: coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

John Lewis | 14 Nov 12:44 2014
Picon

board-status "binary"

Hey y'all,

I've modified the board-status script to have as few external 
dependencies as possible, be a self-extracting, self-running "binary". 
and removed the time-stamp to keep the number initial commits down. Feel 
free to tell me how bad it is and how it murdered your children. :P

John.
Attachment (board-status.run): application/octet-stream, 1494 KiB
--

-- 
coreboot mailing list: coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
ron minnich | 11 Nov 23:23 2014
Picon

programming a 2764

I have a friend who has a parallel port programmer for a 2764. He needs to program it.


Options? 
1. Get a pin-compatible replacement for a 2764
2.get a USB to parallel port adapter
3. get something more modern that will program a 2764
4. build a 2764 programmer from scratch

Any ideas?

ron
--

-- 
coreboot mailing list: coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Gailu Singh | 8 Nov 10:18 2014
Picon

SuperIO support on Bayley Bay CRB (Baytrail SoC)

Hi Experts,

May I know if the support for SuperIO on Bayley Bay CRB is available in coreboot? and can I access UART available on SuperIO?

This board seems to be using Nuvoton SuperIO chip (NPCE985EA0DX). I checked src/superio directory and do not see this chip listed there. Data sheet is also not  available on Nuvoton web site. Can anyone please help?


--

-- 
coreboot mailing list: coreboot <at> coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

Gmane