Timothy Pearson | 24 Jan 23:51 2015

CK804 PCIe PME#

Hi all,

Does anyone have experience with using the CK804 PCIe PME# signal?  I 
have a board here that is receiving PME from the power button but I 
cannot seem to get it to receive PME from the PCIe PME# signal.

Dumping the CK804 configuration space and the SYS/ANACTL LPC 
configuration spaces with the "Wake on PCIe" option enabled then 
disabled in the proprietary BIOS didn't reveal anything interesting.

Thanks!
-- 
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Raptor Engineering
+1 (415) 727-8645
http://www.raptorengineeringinc.com

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The Gluglug | 23 Jan 21:14 2015
Picon

T410S support


Hi,

I found this patch on http://review.coreboot.org/#/c/7975/ but I was
surprised to see a lack of testers. Is there someone out there with
this machine that would still be willing to test it?

Regards,
Francis Rowe.
Wen Wang | 23 Jan 05:34 2015

grub2 as SeaBIOS payload

Hello,

Has anybody tried to launch GRUB2 by SeaBIOS as a payload (not grub2 on
MBR)?  I am hoping to see grub2 on SeaBIOS boot menu.

I followed the coreboot wiki page to compile grub2:
git clone git://git.savannah.gnu.org/grub.git grub
cd grub
./autogen.sh
./configure --with-platform=coreboot
make

At this point it is not clear to me how to create grub2.elf and what the
role of memdisk is. I would appreciate it if somebody could clarify the
steps.

Thanks!

Wen

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Timothy Pearson | 20 Jan 20:55 2015

Quick CK804 PCI device numbering question

All,

I have been working on porting Coreboot to a new CK804-based K10 
mainboard; it warm boots but will not cold boot due to IRQ/MSI 
configuration issues.

While tracing the IRQ problem I noticed that the CK804 PCI function 
numbers change from the proprietary BIOS to Coreboot:

Proprietary:
-[0000:00]-+-00.0  NVIDIA Corporation CK804 Memory Controller [10de:005e]
            +-01.0  NVIDIA Corporation CK804 ISA Bridge [10de:0051]
            +-01.1  NVIDIA Corporation CK804 SMBus [10de:0052]
            ...etc...

Coreboot:
-[0000:00]-+-01.0  NVIDIA Corporation CK804 Memory Controller [10de:005e]
            +-02.0  NVIDIA Corporation CK804 ISA Bridge [10de:0051]
            +-02.1  NVIDIA Corporation CK804 SMBus [10de:0052]

This, in turn, causes Linux to not detect the CK804 root bridge.

Has anyone else seen this with the CK804 chipset?  Is there a magic 
register somewhere that configures the CK804 to use the "correct" PCI 
function numbers?

The only pertinent quirk of this mainboard is that Asus put the CK804 on 
HT link 1, not 0 or 2 as is more common.

Thanks!
(Continue reading)

Kuzmichev Viktor | 20 Jan 14:31 2015
Picon

Mohon Peak, Memtest86+ does not start

Hello,

I'm trying to load Memtest86+ on the Mohon Peak reference board from 
CBFS and it fails.
My primary payload is SeaBIOS. Memtest is added using cbfstool, so the 
layout of my ROM file is as follows:

$ ./build/cbfstool build/coreboot.rom print
coreboot.rom: 8192 kB, bootblocksize 1024, romsize 8388608, offset 0x600000
alignment: 64 bytes, architecture: x86

Name                           Offset     Type         Size
cmos_layout.bin                0x600000   cmos_layout  1352
fallback/romstage              0x600580   stage        26616
fallback/ramstage              0x606dc0   stage        60446
fallback/payload               0x615a40   payload      55799
config                         0x623480   raw          4323
revision                       0x6245c0   raw          714
img/Memtest86+                 0x6248c0   payload      225028
(empty)                        0x65b800   null         1001368
mrc.cache                      0x74ffc0   (unknown)    65536
cpu_microcode_blob.bin         0x760000   microcode    83968
(empty)                        0x774840   null         46936
fsp.bin                        0x77ffc0   (unknown)    372736
(empty)                        0x7db000   null         150424

I've tried versions 4.20 and 5.01. Memtest86+ v4.20 just hangs, here is 
output of SeaBIOS trying to load it:
Trying CBFS
Booting from CBFS...
(Continue reading)

waltermusic | 17 Jan 22:08 2015

Help With An R50e!

Good Day,

I have an IBM ThinkPad R50e (and thinking about getting an X220). Would 
anybody be able to help me liberate my laptop, and install coreboot, and 
get rid of the proprietary BIOS that is present on it (and possibly do 
the same for the X220)?

Thank You.
Dennis

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Marc Jones | 16 Jan 19:15 2015
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coreboot code of conduct

A coreboot code of conduct has been posted on the wiki. 


I have written a blog post about why we have a code of conduct.

Feel free to give feedback on the policy and how else we can contribute to a welcoming and collaborative environment. 

Marc
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Paul Menzel | 14 Jan 23:11 2015
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Picon

Access to bug reports in Chromium bug tracker

Dear coreboot folks,

looking at change set #8214 [1], it adds a comment with a reference to
the Chromium bug tracker at <code.google.com>.

    http://crosbug.com/p/29117

Unfortunately access to view that is denied to me.

Looking at some of the items already in the upstream tree, most of them
seem to be accessible though.

        $ git grep crosbug
        payloads/libpayload/drivers/serial/ipq806x.c:    * See
        http://crosbug.com/p/29313
        payloads/libpayload/drivers/timer/ipq806x.c: *
        http://crosbug.com/p/28880 for details.
        src/ec/google/chromeec/acpi/battery.asl:        // a bug in the
        Linux kernel: http://crosbug.com/28747
        src/ec/google/chromeec/ec_commands.h: *
        TODO(crosbug.com/p/11223): This is effectively useless; protocol
        is
        src/ec/google/chromeec/ec_commands.h: *
        TODO(crosbug.com/p/23570): These commands are deprecated, and
        will be
        src/ec/google/chromeec/ec_commands.h: *
        TODO(crosbug.com/p/23747): This is a confusing name, since it
        doesn't
        src/mainboard/samsung/lumpy/acpi_tables.c:       * Provide
        option to enable for http://crosbug.com/p/7925
        src/soc/intel/broadwell/acpi/gpio.asl:          // Disabled due
        to IRQ storm: http://crosbug.com/p/29548
        src/vendorcode/google/chromeos/vboot.c: * crosbug.com/17017 */

So my question is, is access granted to all these bugs eventually?

Thanks,

Paul

[1] http://review.coreboot.org/#/c/8214/1/src/mainboard/google/samus/romstage.c
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Paul Menzel | 14 Jan 22:53 2015
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Picon

Lenovo X60: GRUB_GFXMODE=1024x768 only works with docking station connected

Dear coreboot folks,

on the Lenovo X60s, running coreboot with SeaBIOS as payload, adding the
two lines below to GRUB’s configuration in `/etc/default/grub`

        GRUB_GFXMODE=1024x768
        GRUB_GFXPAYLOAD_LINUX=keep

and running `update-grub`, which updates GRUB 2.02~beta2-20 (Debian
Jessie/testing) in the MBR, it does only work, when the laptop is
attached to the docking station (nothing attached to the docking
station).

Those of you with a Lenovo system, could you please try to reproduce
this? Also if you still have the vendor firmware, it’d be great to get
some data points. Any hints, how to debug this issue are also
appreciated.

Thanks,

Paul
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Rudolf Marek | 13 Jan 15:55 2015
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AMD technical contact?

Hi all,

Who is the current AMD technical contact? I would like to know whom to ask for
the help with the S3 CAR issue of fam15h.

The CAR teardown routine has wbinvd instead of invd and memory is currupted with
CAR contents during resume from suspend. Replacing WBINVD with INVD does not
work, coreboot will crash during cold boot (perhaps due to unconsistent L2 state).

Thanks
Rudolf

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scan-admin | 10 Jan 16:18 2015

New Defects reported by Coverity Scan for coreboot


Hi,

Please find the latest report on new defect(s) introduced to coreboot found with Coverity Scan.

12 new defect(s) introduced to coreboot found with Coverity Scan.
12 defect(s), reported by Coverity Scan earlier, were marked fixed in the recent build analyzed by
Coverity Scan.

New defect(s) Reported-by: Coverity Scan
Showing 12 of 12 defect(s)

** CID 1255943:  Dereference null return value  (NULL_RETURNS)
/src/cpu/amd/agesa/s3_resume.c: 164 in move_stack_high_mem()
/src/cpu/amd/pi/s3_resume.c: 164 in move_stack_high_mem()

** CID 1262213:  Out-of-bounds access  (ARRAY_VS_SINGLETON)
/src/cpu/x86/car.c: 102 in do_car_migrate_variables()

** CID 1262212:  Unchecked return value  (CHECKED_RETURN)
/src/cpu/intel/hyperthreading/intel_sibling.c: 49 in intel_sibling_init()

** CID 1262211:  Unchecked return value  (CHECKED_RETURN)
/src/southbridge/intel/i82801gx/lpc.c: 220 in i82801gx_power_options()

** CID 1262210:  Unchecked return value  (CHECKED_RETURN)
/src/southbridge/intel/i82801gx/smihandler.c: 286 in southbridge_smi_sleep()

** CID 1262209:  Logically dead code  (DEADCODE)
/src/soc/intel/broadwell/igd.c: 429 in igd_cdclk_init_broadwell()

** CID 1262208:  Division or modulo by zero  (DIVIDE_BY_ZERO)
/payloads/libpayload/arch/arm64/main.c: 46 in test_exception()

** CID 1262207:  Self assignment  (NO_EFFECT)
/src/soc/intel/broadwell/finalize.c: 107 in broadwell_finalize()

** CID 1262206:  Unsigned compared against 0  (NO_EFFECT)
/payloads/libpayload/libc/memory.c: 91 in default_memmove()

** CID 1262205:  Dereference null return value  (NULL_RETURNS)
/src/drivers/intel/fsp/fsp_util.c: 192 in print_fsp_info()

** CID 1262204:  Dereference null return value  (NULL_RETURNS)
/src/drivers/intel/fsp/fsp_util.c: 265 in find_fsp_hob_update_mrc()

** CID 1262203:  Out-of-bounds read  (OVERRUN)
/coreboot-builds/amd_olivehillplus/agesa/amdlib.c: 1411 in IdsErrorStop()

________________________________________________________________________________________________________
*** CID 1255943:  Dereference null return value  (NULL_RETURNS)
/src/cpu/amd/agesa/s3_resume.c: 164 in move_stack_high_mem()
158     
159     static void move_stack_high_mem(void)
160     {
161     	void *high_stack;
162     
163     	high_stack = cbmem_find(CBMEM_ID_RESUME_SCRATCH);
>>>     CID 1255943:  Dereference null return value  (NULL_RETURNS)
>>>     Dereferencing a pointer that might be null "high_stack" when calling "memcpy". [Note: The source code
implementation of the function has been overridden by a builtin model.]
164     	memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR,
165     		(CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE));
166     
167     	__asm__
168     	    volatile ("add	%0, %%esp; add %0, %%ebp; invd"::"g"
169     		      (high_stack - BSP_STACK_BASE_ADDR)
/src/cpu/amd/pi/s3_resume.c: 164 in move_stack_high_mem()
158     
159     static void move_stack_high_mem(void)
160     {
161     	void *high_stack;
162     
163     	high_stack = cbmem_find(CBMEM_ID_RESUME_SCRATCH);
>>>     CID 1255943:  Dereference null return value  (NULL_RETURNS)
>>>     Dereferencing a pointer that might be null "high_stack" when calling "memcpy". [Note: The source code
implementation of the function has been overridden by a builtin model.]
164     	memcpy(high_stack, (void *)BSP_STACK_BASE_ADDR,
165     		(CONFIG_HIGH_SCRATCH_MEMORY_SIZE - BIOS_HEAP_SIZE));
166     
167     	__asm__
168     	    volatile ("add	%0, %%esp; add %0, %%ebp; invd"::"g"
169     		      (high_stack - BSP_STACK_BASE_ADDR)

________________________________________________________________________________________________________
*** CID 1262213:  Out-of-bounds access  (ARRAY_VS_SINGLETON)
/src/cpu/x86/car.c: 102 in do_car_migrate_variables()
96     	car_migrated = ~0;
97     
98     	/* Call all the migration functions. */
99     	migrate_func = &_car_migrate_start;
100     	while (*migrate_func != NULL) {
101     		(*migrate_func)();
>>>     CID 1262213:  Out-of-bounds access  (ARRAY_VS_SINGLETON)
>>>     Using "migrate_func" as an array.  This might corrupt or misinterpret adjacent memory locations.
102     		migrate_func++;
103     	}
104     }
105     
106     void car_migrate_variables(void)
107     {
108     	if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE))
109     		do_car_migrate_variables();

________________________________________________________________________________________________________
*** CID 1262212:  Unchecked return value  (CHECKED_RETURN)
/src/cpu/intel/hyperthreading/intel_sibling.c: 49 in intel_sibling_init()
43     	unsigned i, siblings;
44     	struct cpuid_result result;
45     
46     	/* On the bootstrap processor see if I want sibling cpus enabled */
47     	if (first_time) {
48     		first_time = 0;
>>>     CID 1262212:  Unchecked return value  (CHECKED_RETURN)
>>>     Calling "get_option" without checking return value (as is done elsewhere 15 out of 18 times).
49     		get_option(&disable_siblings, "hyper_threading");
50     	}
51     	result = cpuid(1);
52     	/* Is hyperthreading supported */
53     	if (!(result.edx & (1 << 28))) {
54     		return;

________________________________________________________________________________________________________
*** CID 1262211:  Unchecked return value  (CHECKED_RETURN)
/src/southbridge/intel/i82801gx/lpc.c: 220 in i82801gx_power_options()
214     	// reg8 &= ~(1 << 2);	/* PCI SERR# Enable */
215     	reg8 |= (1 << 2); /* PCI SERR# Disable for now */
216     	outb(reg8, 0x61);
217     
218     	reg8 = inb(0x70);
219     	nmi_option = NMI_OFF;
>>>     CID 1262211:  Unchecked return value  (CHECKED_RETURN)
>>>     Calling "get_option" without checking return value (as is done elsewhere 15 out of 18 times).
220     	get_option(&nmi_option, "nmi");
221     	if (nmi_option) {
222     		printk(BIOS_INFO, "NMI sources enabled.\n");
223     		reg8 &= ~(1 << 7);	/* Set NMI. */
224     	} else {
225     		printk(BIOS_INFO, "NMI sources disabled.\n");

________________________________________________________________________________________________________
*** CID 1262210:  Unchecked return value  (CHECKED_RETURN)
/src/southbridge/intel/i82801gx/smihandler.c: 286 in southbridge_smi_sleep()
280     	u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
281     
282     	// save and recover RTC port values
283     	u8 tmp70, tmp72;
284     	tmp70 = inb(0x70);
285     	tmp72 = inb(0x72);
>>>     CID 1262210:  Unchecked return value  (CHECKED_RETURN)
>>>     Calling "get_option" without checking return value (as is done elsewhere 15 out of 18 times).
286     	get_option(&s5pwr, "power_on_after_fail");
287     	outb(tmp70, 0x70);
288     	outb(tmp72, 0x72);
289     
290     	/* First, disable further SMIs */
291     	reg8 = inb(pmbase + SMI_EN);

________________________________________________________________________________________________________
*** CID 1262209:  Logically dead code  (DEADCODE)
/src/soc/intel/broadwell/igd.c: 429 in igd_cdclk_init_broadwell()
423     	/* CD clock frequency 675MHz not supported on ULT */
424     	if (cpu_is_ult() && cdclk == GT_CDCLK_675)
425     		cdclk = GT_CDCLK_540;
426     
427     	/* Set variables based on CD Clock setting */
428     	switch (cdclk) {
>>>     CID 1262209:  Logically dead code  (DEADCODE)
>>>     Execution cannot reach this statement: "case 0:".
429     	case GT_CDCLK_337:
430     		cdset = 337;
431     		lpcll = (1 << 27);
432     		pwctl = 2;
433     		dpdiv = 169;
434     		break;

________________________________________________________________________________________________________
*** CID 1262208:  Division or modulo by zero  (DIVIDE_BY_ZERO)
/payloads/libpayload/arch/arm64/main.c: 46 in test_exception()
40     int test_exception(void);
41     int test_exception(void)
42     {
43     	int a = 1;
44     	int b = 0;
45     	test_exc = 1;
>>>     CID 1262208:  Division or modulo by zero  (DIVIDE_BY_ZERO)
>>>     In expression "a / b", division by expression "b" which may be zero has undefined behavior.
46     	return a/b;
47     }
48     
49     /**
50      * This is our C entry function - set up the system
51      * and jump into the payload entry point.

________________________________________________________________________________________________________
*** CID 1262207:  Self assignment  (NO_EFFECT)
/src/soc/intel/broadwell/finalize.c: 107 in broadwell_finalize()
101     	reg_script_run_on_dev(PCH_DEV_LPC, pch_finalize_script);
102     
103     	/* Read+Write the following registers */
104     	MCHBAR32(0x6030) = MCHBAR32(0x6030);
105     	MCHBAR32(0x6034) = MCHBAR32(0x6034);
106     	MCHBAR32(0x6008) = MCHBAR32(0x6008);
>>>     CID 1262207:  Self assignment  (NO_EFFECT)
>>>     Assignment operation "*(u32 volatile *)0xfed1e1a4 = *(u32 volatile *)0xfed1e1a4" has no effect.
107     	RCBA32(0x21a4) = RCBA32(0x21a4);
108     
109     	/* Re-init SPI after lockdown */
110     	spi_init();
111     
112     	/* Lock down management engine */

________________________________________________________________________________________________________
*** CID 1262206:  Unsigned compared against 0  (NO_EFFECT)
/payloads/libpayload/libc/memory.c: 91 in default_memmove()
85     
86     	offs = n - (n % sizeof(unsigned long));
87     
88     	for (i = (n % sizeof(unsigned long)) - 1; i >= 0; i--)
89     		((u8 *)dst)[i + offs] = ((u8 *)src)[i + offs];
90     
>>>     CID 1262206:  Unsigned compared against 0  (NO_EFFECT)
>>>     This greater-than-or-equal-to-zero comparison of an unsigned value is always true. "i >= 0UL".
91     	for (i = n / sizeof(unsigned long) - 1; i >= 0; i--)
92     		((unsigned long *)dst)[i] = ((unsigned long *)src)[i];
93     
94     	return dst;
95     }
96     

________________________________________________________________________________________________________
*** CID 1262205:  Dereference null return value  (NULL_RETURNS)
/src/drivers/intel/fsp/fsp_util.c: 192 in print_fsp_info()
186     		if ((u32)fsp_header_ptr < 0xff) {
187     			post_code(0x4F); /* output something in case there is no serial */
188     			die("Can't find the FSP!\n");
189     		}
190     
191     	if (FspHobListPtr == NULL) {
>>>     CID 1262205:  Dereference null return value  (NULL_RETURNS)
>>>     Dereferencing a null pointer "cbmem_find(1213153825U)".
192     		FspHobListPtr = (void*)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER));
193     	}
194     
195     	printk(BIOS_SPEW,"fsp_header_ptr: %p\n", fsp_header_ptr);
196     	printk(BIOS_INFO,"FSP Header Version: %d\n", fsp_header_ptr->HeaderRevision);
197     	printk(BIOS_INFO,"FSP Revision: %d.%d\n",

________________________________________________________________________________________________________
*** CID 1262204:  Dereference null return value  (NULL_RETURNS)
/src/drivers/intel/fsp/fsp_util.c: 265 in find_fsp_hob_update_mrc()
259     }
260     #endif /* CONFIG_ENABLE_MRC_CACHE */
261     
262     static void find_fsp_hob_update_mrc(void *unused)
263     {
264     	/* Set the global HOB list pointer */
>>>     CID 1262204:  Dereference null return value  (NULL_RETURNS)
>>>     Dereferencing a null pointer "cbmem_find(1213153825U)".
265     	FspHobListPtr = (void*)*((u32*) cbmem_find(CBMEM_ID_HOB_POINTER));
266     
267     	if (!FspHobListPtr){
268     		printk(BIOS_ERR, "ERROR: Could not find FSP HOB pointer in CBFS!\n");
269     	} else {
270     		/* 0x0000: Print all types */

________________________________________________________________________________________________________
*** CID 1262203:  Out-of-bounds read  (OVERRUN)
/coreboot-builds/amd_olivehillplus/agesa/amdlib.c: 1411 in IdsErrorStop()
1405     	} post = {0xDEAD, FileCode, 0xDEAD, FileCode};
1406     	UINT16 offset = 0;
1407     	UINT16 j;
1408     
1409     	while(1) {
1410     		offset %= sizeof(struct POST) / 2;
>>>     CID 1262203:  Out-of-bounds read  (OVERRUN)
>>>     Overrunning array of 3 4-byte elements at element index 15 (byte offset 60) by dereferencing pointer
"(UINT32 *)(&post + offset)".
1411     		WriteIo32(80, *((UINT32*)(&post+offset)));
1412     		++offset;
1413     		for (j=0; j<250; ++j) {
1414     			ReadIo8(80);
1415     		}
1416     	}

________________________________________________________________________________________________________
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