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fche | 1 Jan 2012 15:13
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new cgen snapshot available

A new automated cgen source snapshot is available
ftp://sourceware.org/pub/cgen/snapshots/cgen-20120101.tar.bz2
1614480 bytes, cgen-snapshot-20120101 tag
See also ftp://sourceware.org/pub/cgen/snapshots/
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Julius Baxter | 2 Jan 2012 10:44
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Encoding of immediates different to label addresses

Hi,

I'm working on fixing up the OpenRISC 1000 CGEN port and have come
across something I find I can't quite do with CGEN.

For the jump and branch instructions, if we use immediate value number
specified in the assembly, we need that encoded into the instruction
without any shifting occurring to it.

Eg. "l.bf 1" should become 0x10000001, "l.bf 4" should become 0x10000004 etc.

These target addresses are shifted-left by two during decoding, and so
"l.bf 1" is actually a branch of 4 bytes.

If we use a label for an address, though, I'm seeing that we're
getting the offset in bytes during encoding, which then needs to be
shifted right by two before being put in the instruction.

But it seems we can have the shifting on both numerical immediates and
labels, or neither. (Pardon my incorrect use of terminology, I have a
feeling I'm not quite calling everything its right name!)

Upon inspecttion, it looks like the binutils port we have been using
for the past few years (not CGEN-based) has a right-shift of 2 in the
md_apply_fix() function in binutils/gas/config/tc-or32.c (
http://sourceware.org/git/?p=binutils.git;a=blob;f=gas/config/tc-or32.c;h=7234fb837e006f979c255f62206e39a9822046d2;hb=HEAD#l603
) when the instruction had the actual value of the label inserted into
it.

Is there any way to handle this using the CGEN description?
(Continue reading)

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Andrew Burgess | 3 Jan 2012 11:57
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Re: Encoding of immediates different to label addresses

On 02/01/2012 09:44, Julius Baxter wrote:
> I'm working on fixing up the OpenRISC 1000 CGEN port and have come
> across something I find I can't quite do with CGEN.
>
> For the jump and branch instructions, if we use immediate value number
> specified in the assembly, we need that encoded into the instruction
> without any shifting occurring to it.
>
> Eg. "l.bf 1" should become 0x10000001, "l.bf 4" should become 0x10000004 etc.
>
> These target addresses are shifted-left by two during decoding, and so
> "l.bf 1" is actually a branch of 4 bytes.
>
> If we use a label for an address, though, I'm seeing that we're
> getting the offset in bytes during encoding, which then needs to be
> shifted right by two before being put in the instruction.
>
> But it seems we can have the shifting on both numerical immediates and
> labels, or neither. (Pardon my incorrect use of terminology, I have a
> feeling I'm not quite calling everything its right name!)
>
> Upon inspecttion, it looks like the binutils port we have been using
> for the past few years (not CGEN-based) has a right-shift of 2 in the
> md_apply_fix() function in binutils/gas/config/tc-or32.c (
> http://sourceware.org/git/?p=binutils.git;a=blob;f=gas/config/tc-or32.c;h=7234fb837e006f979c255f62206e39a9822046d2;hb=HEAD#l603
> ) when the instruction had the actual value of the label inserted into
> it.
>
> Is there any way to handle this using the CGEN description?
(Continue reading)

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Julius Baxter | 15 Jan 2012 04:24
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Delay slots in GNU sim

Hi,

I've been working on the OpenRISC CGEN description and have got the
assembler working and am now looking at getting a GNU sim port running
too.

I can see a lot of functionality working OK so far (I've based my
simulator port on the lm32 and m32r ports, which are both CGEN-based
implementations of the simulator) but one thing which is not working
are delay slots. They never appear to b executed when a branch is
going to be taken.

I'm yet to delve into the workings if the simulator to figure out why
it's not executing the delay slots, but I just wanted to ask if this
is a known issue with the particular configuration I'm using. The sim
port has "#define WITH_SCACHE_PBB 1", in the tconfig.in file and the
Makefile calls the mloop.c generation script with:

...
$(SHELL) $(srccom)/genmloop.sh \
                -mono -fast -pbb -full-switch -switch sem-switch.c \
                -cpu or1k32bef -infile $(srcdir)/mloop.in

...

My understanding is that this will generate a main loop for a "fast"
model with pseudo-basic-block processing. This is an "upgrade" over
the default "simple" model without pbb.

I'm wondering if delay slots not working are a known issue when
(Continue reading)

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Julius Baxter | 16 Jan 2012 08:49
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Re: Delay slots in GNU sim

On Sun, Jan 15, 2012 at 2:24 PM, Julius Baxter <juliusbaxter <at> gmail.com> wrote:
> Hi,
>
> I've been working on the OpenRISC CGEN description and have got the
> assembler working and am now looking at getting a GNU sim port running
> too.
>
> I can see a lot of functionality working OK so far (I've based my
> simulator port on the lm32 and m32r ports, which are both CGEN-based
> implementations of the simulator) but one thing which is not working
> are delay slots. They never appear to b executed when a branch is
> going to be taken.
>
> I'm yet to delve into the workings if the simulator to figure out why
> it's not executing the delay slots, but I just wanted to ask if this
> is a known issue with the particular configuration I'm using. The sim
> port has "#define WITH_SCACHE_PBB 1", in the tconfig.in file and the
> Makefile calls the mloop.c generation script with:
>
> ...
> $(SHELL) $(srccom)/genmloop.sh \
>                -mono -fast -pbb -full-switch -switch sem-switch.c \
>                -cpu or1k32bef -infile $(srcdir)/mloop.in
>
> ...
>
> My understanding is that this will generate a main loop for a "fast"
> model with pseudo-basic-block processing. This is an "upgrade" over
> the default "simple" model without pbb.
>
(Continue reading)

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youssef fahmi | 16 Jan 2012 09:37
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FW: Problem with instruction description


Hello,

I am working on the porting of binutils to a new architecture.
This processor has an instruction of the form: ld rx,[r1] + imm6 [load the 32 bit word at the address
calculated from the contents of r1 plus the 6 bit immediate value (multiplied by 4) ]
In summary:    rx <- mem[r1 + imm6 * 4]

I need to generate code for this instruction, but only in the case where the code generator in the compiler
generates a standard load, but with an offset appropriate for the imm6 value. That is to say the immediate
value would be less than 256 and be a multiple of 4 (word access).

This is the description that I am using at the moment:
(df​​-f imm6x4 "imm6x4" ()
    11 6 UINT
  ((value pc) (sra WI value (const 2)))
  ((value pc) (sll WI value (const 2))))
(dnop imm6x4 "imm6x4" () h-uint f-imm6x4)
(dni ldstack-r1-imm6x4 "ldstack r1#imm6x4"   ()   "ld $r1,[r1]+$imm6x4"   (+ (f-stack-opcode
#05) r1 imm6x4)   ()   ())   
However this description causes the "ld rx,[r1] + imm6" to be used whenever the immediate vallue is less
than 256, and not JUST when the offset is also a multiple of 4.
How do I alter this description so that it only operates when the immediate value is less than 256 AND ALSO a
multiple of 4.

I have already tried.... but this generates code with this instruction in these cases ;;; which are not
appropriate.How do I achieve this? 
I guess that I'll have to create an attribute to handle this, but I could not get an
attribute that suits me. is there a way to create an attribute of type integer, for example,
but with only specific integers not necessarily following.  
(Continue reading)

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youssef fahmi | 16 Jan 2012 15:32
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Problem with instruction description


Hello,
I'm sorry for the previous mail, I do not know why there were "Â" everywhere.
I am working on the porting of binutils to a new architecture.This processor has an instruction of the form:
ld rx,[r1] + imm6 [load the 32 bit word at the address calculated from the contents of r1 plus the 6 bit
immediate value (multiplied by 4) ]In summary: rx <- mem[r1 + imm6 * 4]
I need to generate code for this instruction, but only in the case where the code generator in the compiler
generates a standard load, but with an offset appropriate for the imm6 value. That is to say the
immediate value would be less than 256 and be a multiple of 4 (word access).
This is the description that I am using at the moment:(df f-imm6x4 "imm6x4" ()  11 6 UINT  ((value pc) (sra
WI value (const 2)))  ((value pc) (sll WI value (const 2))))(dnop imm6x4 "imm6x4" () h-uint
f-imm6x4)(dni ldstack-r1-imm6x4 "ldstack r1#imm6x4"    ()    "ld $r1,[r1]+$imm6x4" (+
(f-stack-opcode #05) r1 imm6x4)  ()    ())   However this description causes the "ld rx,[r1] +
imm6" to be used whenever the immediate vallue is less than 256, and not JUST when the offset is also a
multiple of 4.
How do I alter this description so that it only operates when the immediate value is less than 256 AND ALSO a
multiple of 4.
I have already tried.... but this generates code with this instruction in these cases which are not
appropriate.How do I achieve this? I guess that I'll have to create an attribute to handle this, but I
could not get an attribute that suits me. is there a way to create an attribute of type integer, for
example, but with only specific integers not necessarily following.  
Thanks in advance  for your answer.Youssef 
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Jose E. Marchesi | 19 Jan 2012 20:18
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Hi there


Hi.

Just wanted to say hello, since I just got subscribed :)

I am using cgen for the development of a LEON3 simulator, partly funded
by my employer.

--

-- 
Jose E. Marchesi         http://www.jemarch.net
GNU Project              http://www.gnu.org
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Frank Ch. Eigler | 19 Jan 2012 20:20
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Re: Hi there

Hi, Jose -

> I am using cgen for the development of a LEON3 simulator, partly funded
> by my employer.

Neat.  Are you starting from one of the other SPARC models?  Which
simulator framework are you planning to use (gdb/sim vs. sid)?

- FChE
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Jose E. Marchesi | 19 Jan 2012 22:01
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Re: Hi there


    > I am using cgen for the development of a LEON3 simulator, partly funded
    > by my employer.

    Neat.  Are you starting from one of the other SPARC models?

Probably yes.  I am currently reading the cgen/cpu/sparc*.cpu RTL files.
It looks like they are not being updated since long ago, and that they
are not being used in binutils.

I copied them into my local git repo (which will be public as soon as I
reach a stage where at least the ISA simulator runs) since I need to do
extensive modifications, such as explicitly supporting a V7 machine for
ERC32 and the models themselves.

    Which simulator framework are you planning to use (gdb/sim vs. sid)?

gdb.  I am still in the stage on getting familiar with the common sim
infrastructure, but it looks like it provides enough flexibility (in
terms of buses, signals, etc) for my purposes.

Besides, my company filed a copyright assignment for gdb, and I have got
a personal one in place as well :)

BTW, do I need to sign separated papers for CGEN?

--

-- 
Jose E. Marchesi         http://www.jemarch.net
GNU Project              http://www.gnu.org
(Continue reading)

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Gmane