Christian Svensson | 24 Apr 00:24 2014
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[PATCH] Addons for OpenRISC support

Hi,

We (OpenRISC) have recently begun upstreaming a lot of code. One of the first
things is our binutils port which depends on these CGEN modifications.

This patch has been living in the OpenRISC CGEN repository since 2012.
I would be delighted if it could be merged.

I'm submitting this patch but the author is Peter Gavin, one of the co-authors
of the binutils port.

2014-04-23  Peter Gavin  <pgavin <at> gmail.com>

        * sim-arch.scm: define WI, UWI, AI, & IAI using mode:c-type
        * add mul-o1flag (1's complement unsigned multiply overflow flag)
        and mul-o2flag (2's complement signed multiply overflow flag)
        * rtl-c.scm:
        (rem) add rem (reminder) function (needed for OR1K lf.rem.[sd])
        (mul-o1flag) new define-fn
        (mul-o2flag) ditto
        * rtx-funcs.scm:
        (rem) add rem (reminder) function (needed for OR1K lf.rem.[sd])
        (mul-o1flag) new drn
        (mul-o2flag) ditto

--- cgen.orig/rtl-c.scm 2010-08-30 16:51:27.000000000 +0000
+++ cgen/rtl-c.scm  2014-01-11 11:53:15.565783879 +0000
 <at>  <at>  -1746,6 +1746,14  <at>  <at> 
 (define-fn mul (*estate* options mode s1 s2)
   (s-binop *estate* "MUL" "*" mode s1 s2)
(Continue reading)

fche | 1 Apr 16:14 2014

new cgen snapshot available

A new automated cgen source snapshot is available
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1631769 bytes, cgen-snapshot-20140401 tag
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fche | 1 Mar 15:14 2014

new cgen snapshot available

A new automated cgen source snapshot is available
ftp://sourceware.org/pub/cgen/snapshots/cgen-20140301.tar.bz2
1631582 bytes, cgen-snapshot-20140301 tag
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Usha Gupta | 3 Feb 18:34 2014
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Help needed for porting opcodes for CISC architecture

Hi All ,

I am  new to CGEN and want to port binutils for a CISC  architecture
wherein the instruction length can vary from 1 byte to a maximum of
5-bytes.

I am having trouble porting opcodes using CGEN.

I have defined various hardware elements and instruction fields.

I am not sure what should be the values of

(default-insn-bitsize 8)
(base-insn-bitsize 16)
(default-insn-word-bitsize 16 )
(word-bitsize 16 )

As mentioned in the CGEN manual, I specified default-insn bitsize  as
8 (smallest instruction length) and rest of the values as 16 ( word
length is 2 bytes).

This works for 16-bit instructions where both the operands are
explicit in the instruction encoding.

Another important thing to mention here is that the machine does not
have a fixed length opcode.

Here are some of the instruction formats :

1-byte instruction:
(Continue reading)

fche | 1 Feb 15:14 2014

new cgen snapshot available

A new automated cgen source snapshot is available
ftp://sourceware.org/pub/cgen/snapshots/cgen-20140201.tar.bz2
1631596 bytes, cgen-snapshot-20140201 tag
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fche | 1 Jan 15:14 2014

new cgen snapshot available

A new automated cgen source snapshot is available
ftp://sourceware.org/pub/cgen/snapshots/cgen-20140101.tar.bz2
1631617 bytes, cgen-snapshot-20140101 tag
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fche | 1 Dec 15:13 2013

new cgen snapshot available

A new automated cgen source snapshot is available
ftp://sourceware.org/pub/cgen/snapshots/cgen-20131201.tar.bz2
1631809 bytes, cgen-snapshot-20131201 tag
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fche | 1 Nov 15:14 2013

new cgen snapshot available

A new automated cgen source snapshot is available
ftp://sourceware.org/pub/cgen/snapshots/cgen-20131101.tar.bz2
1632174 bytes, cgen-snapshot-20131101 tag
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fche | 1 Oct 16:14 2013

new cgen snapshot available

A new automated cgen source snapshot is available
ftp://sourceware.org/pub/cgen/snapshots/cgen-20131001.tar.bz2
1631519 bytes, cgen-snapshot-20131001 tag
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