Robert Jordens | 1 Mar 00:15 2015
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[M-Labs devel] [PATCH] pipistrello: remove unused, unconnected, commented-out pins

---
 mibuild/platforms/pipistrello.py | 2 --
 1 file changed, 2 deletions(-)

diff --git a/mibuild/platforms/pipistrello.py b/mibuild/platforms/pipistrello.py
index 6129f12..84c4b87 100644
--- a/mibuild/platforms/pipistrello.py
+++ b/mibuild/platforms/pipistrello.py
 <at>  <at>  -107,7 +107,6  <at>  <at>  _io = [
 	("sdram", 0,
 		Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6")),
 		Subsignal("ba", Pins("F2 F1")),
-		# Subsignal("cs_n", Pins("K6")), # NC
 		Subsignal("cke", Pins("H7")),
 		Subsignal("ras_n", Pins("L5")),
 		Subsignal("cas_n", Pins("K5")),
 <at>  <at>  -115,7 +114,6  <at>  <at>  _io = [
 		Subsignal("dq", Pins("L2 L1 K2 K1 H2 H1 J3 J1 M3 M1 N2 N1 T2 T1 U2 U1")),
 		Subsignal("dqs", Pins("L4 P2")),
 		Subsignal("dm", Pins("K3 K4")),
-		# Subsignal("rzq", Pins("N4")), # NC
 		IOStandard("MOBILE_DDR")
 	)
 ]
--

-- 
1.9.1

Robert Jordens | 1 Mar 00:01 2015
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[M-Labs devel] [PATCH] pipistrello: fix lpddr parameters, crg, flash, style

---
 targets/pipistrello.py | 76 +++++++++++++++++++++++++++++++++-----------------
 1 file changed, 50 insertions(+), 26 deletions(-)

diff --git a/targets/pipistrello.py b/targets/pipistrello.py
index e7bfe9e..3ca47de 100644
--- a/targets/pipistrello.py
+++ b/targets/pipistrello.py
 <at>  <at>  -4,14 +4,19  <at>  <at>  from migen.fhdl.std import *
 from migen.genlib.resetsync import AsyncResetSynchronizer

 from misoclib.mem import sdram
-from misoclib.mem.sdram.phy import gensdrphy
+from misoclib.mem.sdram.phy import s6ddrphy
 from misoclib.mem.flash import spiflash
 from misoclib.soc.sdram import SDRAMSoC

 class _CRG(Module):
 	def __init__(self, platform, clk_freq):
 		self.clock_domains.cd_sys = ClockDomain()
-		self.clock_domains.cd_sys_ps = ClockDomain()
+		self.clock_domains.cd_sdram_half = ClockDomain()
+		self.clock_domains.cd_sdram_full_wr = ClockDomain()
+		self.clock_domains.cd_sdram_full_rd = ClockDomain()
+
+		self.clk4x_wr_strb = Signal()
+		self.clk4x_rd_strb = Signal()

 		f0 = 50*1000*1000
 		clk50 = platform.request("clk50")
(Continue reading)

Robert Jordens | 28 Feb 23:55 2015
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[M-Labs devel] [PATCH 1/2] pipistrello: switch back to xc3sprog and fast (papilio) speed

---
 mibuild/platforms/pipistrello.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/mibuild/platforms/pipistrello.py b/mibuild/platforms/pipistrello.py
index 244cbf6..e8f95f7 100644
--- a/mibuild/platforms/pipistrello.py
+++ b/mibuild/platforms/pipistrello.py
 <at>  <at>  -1,7 +1,7  <at>  <at> 
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
 from mibuild.xilinx.ise import XilinxISEPlatform
-from mibuild.xilinx.programmer import FpgaProg
+from mibuild.xilinx.programmer import XC3SProg

 _io = [
 	("user_led", 0, Pins("V16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green near hdmi
 <at>  <at>  -119,7 +119,7  <at>  <at>  class Platform(XilinxISEPlatform):
 			lambda p: SimpleCRG(p, "clk50", None), _connectors)

 	def create_programmer(self):
-		return FpgaProg("bscan_spi_lx45_csg324.bit")
+		return XC3SProg("papilio", "bscan_spi_lx45_csg324.bit")

 	def do_finalize(self, fragment):
 		try:
--

-- 
1.9.1

(Continue reading)

Robert Jordens | 27 Feb 04:22 2015
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[M-Labs devel] [PATCH 1/3] add pipistrello platform

---
 mibuild/platforms/pipistrello.py | 128 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 128 insertions(+)
 create mode 100644 mibuild/platforms/pipistrello.py

diff --git a/mibuild/platforms/pipistrello.py b/mibuild/platforms/pipistrello.py
new file mode 100644
index 0000000..cd3d67f
--- /dev/null
+++ b/mibuild/platforms/pipistrello.py
 <at>  <at>  -0,0 +1,128  <at>  <at> 
+from mibuild.generic_platform import *
+from mibuild.crg import SimpleCRG
+from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx.programmer import XC3SProg
+
+_io = [
+	("user_led", 0, Pins("V16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green near hdmi
+	("user_led", 1, Pins("U16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red near hdmi
+	("user_led", 2, Pins("A16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at msd
+	("user_led", 3, Pins("A15"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at msd
+	("user_led", 4, Pins("A12"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at usb
+
+	("user_switch", 0, Pins("N14"), IOStandard("LVTTL"), Misc("PULLDOWN")),
+
+	("clk50", 0, Pins("H17"), IOStandard("LVTTL")),
+
+	("serial", 0,
+		Subsignal("tx", Pins("A10"), Misc("SLEW=SLOW")),
+		Subsignal("rx", Pins("A11"), Misc("PULLUP")),
(Continue reading)

Robert Jordens | 27 Feb 04:27 2015
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[M-Labs devel] [PATCH] xilinx/programmer: fix xc3sprog (GenericProgrammer)

---
 mibuild/xilinx/programmer.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/mibuild/xilinx/programmer.py b/mibuild/xilinx/programmer.py
index eb9f514..d659d2a 100644
--- a/mibuild/xilinx/programmer.py
+++ b/mibuild/xilinx/programmer.py
 <at>  <at>  -35,7 +35,7  <at>  <at>  class XC3SProg(GenericProgrammer):
 	needs_bitreverse = False

 	def __init__(self, cable, flash_proxy_basename=None):
-		Programmer.__init__(self, flash_proxy_basename)
+		GenericProgrammer.__init__(self, flash_proxy_basename)
 		self.cable = cable

 	def load_bitstream(self, bitstream_file):
--

-- 
1.9.1

Robert Jordens | 27 Feb 04:23 2015
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[M-Labs devel] [PATCH] add pipistrello target

---
 targets/pipistrello.py | 105 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 105 insertions(+)
 create mode 100644 targets/pipistrello.py

diff --git a/targets/pipistrello.py b/targets/pipistrello.py
new file mode 100644
index 0000000..069ff48
--- /dev/null
+++ b/targets/pipistrello.py
 <at>  <at>  -0,0 +1,105  <at>  <at> 
+from fractions import Fraction
+
+from migen.fhdl.std import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from misoclib import spiflash, sdram
+from misoclib.sdram.phy import gensdrphy
+from misoclib.gensoc import SDRAMSoC
+
+class _CRG(Module):
+	def __init__(self, platform, clk_freq):
+		self.clock_domains.cd_sys = ClockDomain()
+		self.clock_domains.cd_sys_ps = ClockDomain()
+
+		f0 = 50*1000*1000
+		clk50 = platform.request("clk50")
+		clk50a = Signal()
+		self.specials += Instance("IBUFG", i_I=clk50, o_O=clk50a)
+		clk50b = Signal()
(Continue reading)

Robert Jordens | 27 Feb 04:19 2015
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[M-Labs devel] [PATCH] gensoc: missing self.

---
 misoclib/gensoc/__init__.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/misoclib/gensoc/__init__.py b/misoclib/gensoc/__init__.py
index ae88052..46068cc 100644
--- a/misoclib/gensoc/__init__.py
+++ b/misoclib/gensoc/__init__.py
 <at>  <at>  -193,7 +193,7  <at>  <at>  class SDRAMSoC(GenSoC):
 				self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), sdramcon.bus)
 			elif (sdram_width < 32):
 				self.submodules.dc = wishbone.DownConverter(32, sdram_width)
-				self.submodules.intercon = wishbone.InterconnectPointToPoint(dc.wishbone_o, sdramcon.bus)
+				self.submodules.intercon = wishbone.InterconnectPointToPoint(self.dc.wishbone_o, sdramcon.bus)
 				self.add_wb_slave(mem_decoder(self.mem_map["sdram"]), self.dc.wishbone_i)
 			else:
 				raise NotImplementedError("Unsupported SDRAM width of {} > 32".format(sdram_width))
--

-- 
1.9.1

josh wilmarth | 8 Feb 10:32 2015
Picon

[M-Labs devel] milkymist one

looking for a milkymist one. will pay money.
<div><div dir="ltr">looking for a milkymist one. will pay money.</div></div>
Sébastien Bourdeauducq | 25 Jan 16:49 2015
Picon

[M-Labs devel] ARTIQ on NIST news

Hi,

NIST has published a press release on the experiment control system
we've been working on:
http://nist.gov/pml/div688/grp10/open-source-software-for-quantum-information.cfm

ARTIQ is fully open source and uses Migen/MiSoC for the gateware.

Sébastien
_______________________________________________
M-Labs devel mailing list
https://ssl.serverraum.org/lists/listinfo/devel
haimag ren | 15 Jan 02:02 2015
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[M-Labs devel] Tachyon DA's CVC Full 1364 Verilog HDL Compiled Simulator is now Open Source

 Tachyon DA's CVC Full 1364 Verilog HDL Compiled Simulator is now Open Source


What is CVC?
---------------

CVC is a full IEEE 1364 2005 compliant Verilog Hardware Description Language (HDL) simulator that compilesVerilog to native X86_64 machine instructions which are executed as a simple native Linux binary.  CVC is as least as fast as any commercial full 1364 2005 simulator.
CVC Features
Fast native compiled simulation.
Very large gate and RTL capacity with 64 bit CVC64.  64 bit simulation is faster than 32 bit on modern hardware at the cost of larger cvcsim binary files.
Best solution for machine generated Verilog simulation.
Implements new  X-propagation synthesizable Verilog expression evaluation algorithm.
Linux X86 support.
Ability to simulate in either compiled or interpreted mode.
Interpreted mode allows for fast elaboration of large designs during the initial design phase. Flow graph machine code generation and optimization steps are removed to speed up elaboration.
Then when simulation speed is important, CVC compiles into a native binary that executes faster than any available simulator.
Built in toggle coverage with per instance/bit and tick period control.
VCD/EVCD/FST design state dump formats.
Latest FST output for close GTKWave integration.  Options that allow using up to 2 additional X86 cores for parallel FST generation.
Full PLI (vpi_*, dpi_*, acc_*, tf_*) support.
Fastest vpi_ and no overhead dpi_ ABI interface to c/c++.
Fully IEEE Verilog 1364-2005 standard compliant.
2-state simulation.
C compiler style simple compilation to executable – no projects and no 3 step design loading.
<div>
<div>
<h1>
<span>&nbsp;Tachyon DA's CVC Full 1364 Verilog HDL Compiled Simulator is now Open Source</span><br>
</h1>
<br>
</div>
<div class="t_msgfontfix"><table cellspacing="0" cellpadding="0"><tr><td class="t_msgfont"><span>What is CVC?<br>---------------<br><br>CVC is a full IEEE 1364 2005 compliant Verilog Hardware Description Language (HDL) simulator that compilesVerilog to native X86_64 machine instructions which are executed as a simple native Linux binary.&nbsp;&nbsp;CVC is as least as fast as any commercial full 1364 2005 simulator.<br>CVC Features<br>Fast native compiled simulation.<br>Very large gate and RTL capacity with 64 bit CVC64.&nbsp;&nbsp;64 bit simulation is faster than 32 bit on modern hardware at the cost of larger cvcsim binary files.<br>Best solution for machine generated Verilog simulation.<br>Implements new&nbsp;&nbsp;X-propagation synthesizable Verilog expression evaluation algorithm.<br>Linux X86 support.<br>Ability to simulate in either compiled or interpreted mode.<br>Interpreted mode allows for fast elaboration of large designs during the initial design phase. Flow graph machine code generation and optimization steps are removed to speed up elaboration.<br>Then when simulation speed is important, CVC compiles into a native binary that executes faster than any available simulator.<br>Built in toggle coverage with per instance/bit and tick period control.<br>VCD/EVCD/FST design state dump formats.<br>Latest FST output for close GTKWave integration.&nbsp;&nbsp;Options that allow using up to 2 additional X86 cores for parallel FST generation.<br>Full PLI (vpi_*, dpi_*, acc_*, tf_*) support.<br>Fastest vpi_ and no overhead dpi_ ABI interface to c/c++.<br>Fully IEEE Verilog 1364-2005 standard compliant.<br>2-state simulation.<br>C compiler style simple compilation to executable &ndash; no projects and no 3 step design&nbsp;<span href="tag.php?name=loading" class="t_tag">loading</span>.</span></td></tr></table></div>
</div>
Andreas | 14 Jan 15:49 2015
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[M-Labs devel] WTB: The Milkymist One

Dear fellow Milkymist One users

I’m maybe looking for a second hand ”The Milkymist One” depending on price.

 

Any offers?

 

Kind regards

Andreas

 

<div><div class="WordSection1">
<p class="MsoNormal"><span lang="EN-US">Dear fellow Milkymist One users<p></p></span></p>
<p class="MsoNormal"><span lang="EN-US">I&rsquo;m maybe looking for a second hand &rdquo;The Milkymist One&rdquo; depending on price.<p></p></span></p>
<p class="MsoNormal"><span lang="EN-US"><p>&nbsp;</p></span></p>
<p class="MsoNormal"><span lang="EN-US">Any offers?<p></p></span></p>
<p class="MsoNormal"><span lang="EN-US"><p>&nbsp;</p></span></p>
<p class="MsoNormal"><span lang="EN-US">Kind regards<p></p></span></p>
<p class="MsoNormal"><span lang="EN-US">Andreas<p></p></span></p>
<p class="MsoNormal"><p>&nbsp;</p></p>
</div></div>

Gmane