Alain Péteut | 25 Apr 15:43 2015
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[M-Labs devel] [PATCH] Test examples

Add tests which simply run the examples using `subprocess.check_call`.

Alain Péteut (1):
  add examples tests

 migen/test/test_examples.py |  120 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 120 insertions(+)
 create mode 100644 migen/test/test_examples.py

--
1.7.10.4

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Alain Péteut | 25 Apr 00:08 2015
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[M-Labs devel] [PATCH] prefix test module file with `test_`

Unittest discover looks for certain regex pattern, this patch
fixes the module name so it is actually discovered.

Alain Péteut (1):
  prefix test module file with `test_`

 migen/test/asic_syntax.py      |   58 ----------------------------------------
 migen/test/test_asic_syntax.py |   58 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 58 insertions(+), 58 deletions(-)
 delete mode 100644 migen/test/asic_syntax.py
 create mode 100644 migen/test/test_asic_syntax.py

--
1.7.10.4

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Alain Péteut | 21 Apr 16:58 2015
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[M-Labs devel] [PATCH] add Travis CI badge

Add Travis CI badge to README.

Alain Péteut (1):
  add Travis CI badge

 README.md |    6 ++++++
 1 file changed, 6 insertions(+)

--
1.7.10.4

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Guy Hutchison | 20 Apr 18:53 2015
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[M-Labs devel] [PATCH 2/2] ASIC syntax test

New test file to validate changes for ASIC syntax.  Requires Verilator for running lint.
Attachment (asic_syntax_test.patch): application/octet-stream, 2804 bytes
<div><div dir="ltr">New test file to validate changes for ASIC syntax.&nbsp; Requires Verilator for running lint.</div></div>
Guy Hutchison | 20 Apr 18:51 2015
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[M-Labs devel] [PATCH 1/2] ASIC syntax verilog.py changes

Resubmit of patch for verilog.py changes for ASIC syntax support.

Removed all width overrides, replaced with additional parameter "special_comments" to convert which allows 3rd party comments to be inserted at the top of the file.

Attachment (asic_syntax_verilog.patch): application/octet-stream, 7096 bytes
<div><div dir="ltr">Resubmit of patch for verilog.py changes for ASIC syntax support.<div><br></div>
<div>Removed all width overrides, replaced with additional parameter "special_comments" to convert which allows 3rd party comments to be inserted at the top of the file.</div>
<div><br></div>
</div></div>
Tim 'mithro' Ansell | 20 Apr 12:57 2015

[M-Labs devel] [PATCH] misoc: Adding git submodule init to README

From: Tim Ansell <mithro@...>

Fixes https://github.com/m-labs/misoc/issues/8
---
 README | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/README b/README
index 4c19931..ab0fd02 100644
--- a/README
+++ b/README
 <at>  <at>  -45,6 +45,9  <at>  <at>  modules.

 [> Quick start guide
 --------------------
+0. (If cloning from git) Initialize the git submodules. 
+  `git submodule init; git submodule update`
+
 1. Install Python 3.3+, Migen and FPGA vendor's development tools.
   Get Migen from: https://github.com/m-labs/migen

--

-- 
2.2.0.rc0.207.ga3a616c

Alain Péteut | 20 Apr 09:19 2015
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[M-Labs devel] [PATCH 0/3] PEP8, mibuild/altera diff I/O

These patches add differential I/O support to mibuild/altera and
do some PEP8 cosmetic.

Alain Péteut (3):
  some PEP8 cosmetic
  add differential in/out support to mibuild/altera
  add I/O standard definitions to mibuild/altera

 mibuild/altera/__init__.py   |    5 +-
 mibuild/altera/_iostd.py     |   91 +++++++++++++++++++++++++++++++++++
 mibuild/altera/common.py     |   41 +++++++++++++++-
 mibuild/altera/platform.py   |    3 +-
 mibuild/altera/programmer.py |    6 ++-
 mibuild/altera/quartus.py    |  108 +++++++++++++++++++++++++++++-------------
 mibuild/generic_platform.py  |   89 +++++++++++++++++++++++++++-------
 7 files changed, 287 insertions(+), 56 deletions(-)
 create mode 100644 mibuild/altera/_iostd.py

--
1.7.10.4

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Tim 'mithro' Ansell | 19 Apr 08:54 2015

[M-Labs devel] [PATCH] misoc: Fixing minor warning in vpi/ipc.c

Hi,

This patch fixes a very minor warning that -Wall produces in vpi/ipc.c

These warnings seem to be the only current warnings, so after this patch, you
could turn on -Werror if you want to prevent warnings from creeping back in.

Tim 'mithro' Ansell (1):
  Fixing shadowing of global index function.

 vpi/ipc.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

--

-- 
2.2.0.rc0.207.ga3a616c

Alain Péteut | 17 Apr 17:52 2015
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[M-Labs devel] [PATCH] fix issue #12

Alain Péteut (1):
  fix issue #12

 setup.py |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--
1.7.10.4

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Sébastien Bourdeauducq | 17 Apr 16:31 2015
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Re: [M-Labs devel] [PATCH 1/2] Add mode switch to change output code generation

On 04/17/2015 10:10 PM, Guy Hutchison wrote:
> You can get bugs if your constant is larger than what you are trying to
> put it in to.  EDA tool will correctly throw away the upper bits, but if
> you really wanted to count to 1024 you're now not counting or counting
> forever.
> 
> These bugs are easily caught by lint tools, but only if the rest of the
> code consistently uses the correct width.

I don't really understand, can you provide a concrete example of this?

Migen should already output bit widths for constants that correspond to
the minimum number of bits required to represent the value.

Sébastien

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Guy Hutchison | 17 Apr 01:44 2015
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[M-Labs devel] [PATCH 2/2] Test case for asic_syntax

Added unit test for ASIC syntax (requires Verilator)

<div><div dir="ltr">Added unit test for ASIC syntax (requires Verilator)<div><br></div>
</div></div>

Gmane