William D. Jones | 2 Jul 04:46 2016
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[M-Labs devel] [PATCH] platform/icestick: Fix serial port pin assignments.

When I initially submitted IcesStick platform support, I misread the schematic
and assigned the incorrect FPGA pins to the FTDI chip.

Specifically, I used the FTDI pin numbers and not the FPGA pin numbers. Consequently,
any attempt to use the FTDI chip on IceStick errors out b/c the pin numbers are invalid
for a tq144 package, among other issues. This commit assigns the correct pins.
Tx/Rx operation was verified in gateware.

William D. Jones (1):
  platform/icestick: Fix serial port pin assignments.

 migen/build/platforms/icestick.py | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

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William D. Jones | 1 Jul 18:43 2016
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[M-Labs devel] [PATCH] lattice/icestorm: Timing analysis, yosys exit on error.

>> max(self.freq_constraints.values(), default=0.0)
>Oops... will fix tomorrow morning.

And by that I mean a month from now. Whoops! Let me know if there are any other
changes to be made.

If you are still not satisfied, then I will just abort timing analysis features for now until IceStorm matures.
I'd really like to get the yosys exit on error into the main tree, so I'll just make a separate patch if necessary.

William D. Jones (1):
  lattice/icestorm: Timing analysis, yosys exit on error.

 migen/build/lattice/icestorm.py | 54 +++++++++++++++++++++++++++++------------
 1 file changed, 38 insertions(+), 16 deletions(-)

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William D. Jones | 3 Jun 19:56 2016
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[M-Labs devel] [PATCH] lattice/icestorm: Timing analysis, yosys exit on error.

This patch is an improvement on the previous Lattice IceStorm patches. Among
other things, this patch corrects yosys behavior on error on Windows, adds
rudimentary timing analysis, and also includes formatting tweaks and dead code
removal. Additionally, I made arachne-pnr quiet by default, and yosys now writes
to a log file.

William D. Jones (1):
  lattice/icestorm: Timing analysis, yosys exit on error.

 migen/build/lattice/icestorm.py | 59 ++++++++++++++++++++++++++++++-----------
 1 file changed, 44 insertions(+), 15 deletions(-)

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William D. Jones | 19 May 01:31 2016
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[M-Labs devel] [PATCH] migen/build: Icestorm toolchain improvements.

The attached patch adds the requested comment for how clock constraints are
handled as IceStorm matures. I also changed the commit message to be more
specific.

William D. Jones (1):
  lattice/icestorm: Timing analysis, yosys exit on error.

 migen/build/lattice/icestorm.py | 24 +++++++++++++++++++++++-
 1 file changed, 23 insertions(+), 1 deletion(-)

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William D. Jones | 12 May 20:59 2016
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[M-Labs devel] [PATCH] IceStorm Toolchain Improvements

I have added a few modifications to the IceStorm builder, including:
* Add support for a global timing constraint.
* Use the icetime command to check whether the design meets global timing constraints.
* Yosys command now terminates properly on failure in Windows.
* Minor formatting changes.

William D. Jones (1):
  migen/build: Icestorm toolchain improvements.

 migen/build/lattice/icestorm.py | 41 +++++++++++++++++++++++++++--------------
 1 file changed, 27 insertions(+), 14 deletions(-)

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William D. Jones | 12 May 20:56 2016
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[M-Labs devel] [PATCH] iCEstick Dev Board Support

The following patch adds support for the Lattice iCEstick dev board using the
open source IceStorm toolchain. Currently, the IOStandard directives are
placeholders that do nothing and are meant for forward compatibility.

William D. Jones (1):
  migen/build: Add Lattice iCEstick dev board.

 migen/build/platforms/icestick.py | 58 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 migen/build/platforms/icestick.py

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William D. Jones | 8 May 02:37 2016
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[M-Labs devel] [PATCH] Add Icestorm toolchain to migen.build

The following patch adds support to Migen for the fully open-source IceStorm
FPGA workflow, including yosys, arachne-pnr, and icepack.

The following features are implemented but have tested (both should work fine):
1. Unix script generation.
2. Multiple verilog files.

Unlike other backends, sourcing is not implemented; it is assumed that the
Icestorm tools will be on your system path.

Because of limitations in Arachne PNR, only pin constraint assignment is
currently supported. As the toolchain matures, I will add additional directives
to the constraint file.

Pending approval of this patch, I will add support for the Lattice IceStick board.

William D. Jones (1):
  migen/build: Add Icestorm toolchain.

 migen/build/lattice/icestorm.py   | 126 ++++++++++++++++++++++++++++++++++++++
 migen/build/lattice/platform.py   |   5 +-
 migen/build/lattice/programmer.py |   7 +++
 3 files changed, 137 insertions(+), 1 deletion(-)
 create mode 100644 migen/build/lattice/icestorm.py

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(Continue reading)

William D. Jones | 22 Apr 19:18 2016
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[M-Labs devel] [PATCH] Fail gracefully when running build commands on Windows.

Improved version of my previous patch- less redundant code.

William D. Jones (1):
  Add "set -e" equivalent to Windows batch file.

 migen/build/xilinx/ise.py | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

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William D. Jones | 22 Apr 14:17 2016
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[M-Labs devel] [PATCH] Fail gracefully when running build commands on Windows.

Some time ago, I added the ability to generate batch files to migen.build, so
that users would not need to depend on a bash shell existing. While Windows
support for Unix utilities is coming around, it's still useful to support
the current behavior for those using strictly Windows tools.

Windows does not have an equivalent of "set -e" as bash does; if a command fails,
then the next command will run (which will also fail) until the end of the file.
This patch adds a commonly-accepted pattern for duplicating "set -e". Unix shell
scripts generated by migen.build are not affected.

William D. Jones (1):
  xilinx/ise: Add "set -e" equivalent to Windows batch file.

 migen/build/xilinx/ise.py | 22 ++++++++++++++++------
 1 file changed, 16 insertions(+), 6 deletions(-)

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FabienM | 11 Apr 09:51 2016
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[M-Labs devel] [PATCH] migen/build/platforms: adding apf6sp Armadeus Platform

Hello,

This is just a reminder for adding apf6sp platform in Migen.

The patch in attachment work well with this program to blink the led :

#!/usr/local/bin/python3.4
# -*- coding: utf-8 -*-

from migen import *
from migen.fhdl import *
from migen.build.generic_platform import Pins, IOStandard, Subsignal
from migen.build.platforms import apf6sp

ios = [ ("user_led", 0, Pins("HIROSE:D0")),]

plat = apf6sp.Platform()
plat.add_extension(ios)
led = plat.request("user_led", 0)  # led pin on apf6sp_dev

m = apf6sp.PciePllClockedModule(platform=plat)
counter = Signal(26)
m.comb += led.eq(counter[25])
m.sync += counter.eq(counter + 1)

plat.build(m)

Regards,
Fabien M (Martoni)

(Continue reading)

William D. Jones | 11 Apr 07:47 2016
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[M-Labs devel] [PATCH] Migen should source the Xilinx ISE toolchain by default on Windows.

On Windows, it is not likely that users of ISE toolchain will have the appropriate
environment variables set by default. Since the API change in MiSoC, users no longer
have the ability to override this behavior when building a target. The resulting
batch file generated by Migen will not be able to find any of the Xilinx tools.

Therefore, we should by default insert a call the Xilinx batch file to set up the
environment before running the tools. The call is required to prevent the child
batch file from terminating the parent batch file when the child is done.

For those who already have Xilinx tools on the path before building Migen gateware,
there is no difference in environment other than the Xilinx PATHS being duplicated
for the duration of the cmd.exe subprocess.

William D. Jones (1):
  xilinx/ise: Windows should source Xilinx toolchain by default (fixes
    MiSoC build failures).

 migen/build/xilinx/ise.py | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

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Gmane