Sébastien Bourdeauducq | 22 Jan 16:56 2016
Picon
Gravatar

[M-Labs devel] changes to packetized dataflow

Hi Florent & all,

do we agree on the following changes to the packetized endpoints:
* the SOP signal should be removed (can be derived from EOP/STB)
* EOP should be sent in a separate token with no data. This may limit 
performance when the packet size is small, but it is more flexible as we 
do not always know if the packet finished when sending a token of data.

Sebastien

Sébastien Bourdeauducq | 22 Jan 16:52 2016
Picon
Gravatar

[M-Labs devel] FOSDEM

Hi all,

as you may know, I'm speaking about Migen and MiSoC at FOSDEM this month:
https://fosdem.org/2016/schedule/track/eda/

I would like to speak about user projects in my presentation to show 
what the community are doing. It can range from a brief mention to 
several slides, depending on the scope of the project(s). So if you 
would like to be mentioned, please get in touch :)

Sebastien
Tim 'mithro' Ansell | 3 Jan 08:54 2016
Gravatar

[M-Labs devel] [PATCH] Exception now has helpful string.

Before;
```
  File "/usr/local/google/home/tansell/foss/timvideos/hdmi2usb/i2cslave/build/lib/python3.4/site-packages/migen-0.2-py3
.4.egg/migen/fhdl/structure.py", line 110, in __getitem__
    raise TypeError
TypeError
```

After;
```
  File
"/usr/local/google/home/tansell/foss/timvideos/hdmi2usb/i2cslave/build/lib/python3.4/site-packages/migen-0.2-py3.4.egg/migen/fhdl/structure.py",
line 110, in __getitem__
    raise TypeError("Can use type %s (%r) as key" % (type(key), key))
TypeError: Can use type <class 'migen.fhdl.structure.Signal'> (<Signal dbits at 0x7fd7836a2a90>) as key
```
---
 migen/fhdl/structure.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index d44a50e..0a8cc16 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
 <at>  <at>  -107,7 +107,8  <at>  <at>  class _Value(DUID):
                 return Cat(self[i] for i in range(start, stop, step))
             return _Slice(self, start, stop)
         else:
-            raise TypeError
+            raise TypeError("Can use type {} ({}) as key".format(
(Continue reading)

Sebastien Bourdeauducq | 23 Dec 15:25 2015
Picon
Gravatar

Re: [M-Labs devel] dataflow problems

On Wednesday, December 23, 2015 10:16 PM, Florent Kermarrec wrote:
> OK, then add bytes enable to your dataflow layout.

Are you proposing that the message generator produces tokens that are of 
this form:
<payload - 256 bits, variable> <enable - 1 bit, fixed to 1>

and the converter for e.g. 512-bit SDRAM words produces tokens:
<payload0> <enable0> <payload1> <enable1>
...and the converter resets its buffer to zero after producing a token, 
and a fortiori its enable outputs? So enable outputs that haven't 
received a token from the message generator stay at 0?

I guess that could work, though I do find it a bit hacky, and the DMA 
core has to signal the converter to flush (i.e. generate EOP) - and 
everything has to be synchronized correctly.

What about the SDRAM word size < 256 bit case?

Sebastien
Sebastien Bourdeauducq | 23 Dec 15:06 2015
Picon
Gravatar

Re: [M-Labs devel] dataflow problems

On Wednesday, December 23, 2015 09:44 PM, Florent Kermarrec wrote:
> In this case you need to use the sop/eop delimiters:
> - for the two cases: when converter detects stb/eop, it emits its output
> immediatly, you will have some garbage in the last SDRAM word if
> message_size is not multiple of SDRAM word size, but that's expected
> with your usecase (and I think message has a length field defined in it).

All messages have the same size (256 bits) and are transferred into the 
converter in a single cycle. In the case SDRAM word > 256 bits, garbage 
words are not acceptable, so the converter would need to e.g. output a 
"number of bytes valid" signal that the DMA core needs to use to 
generate the Wishbone "sel" signal and update its message counter 
correctly. How does EOP improve things in the case SDRAM word < 256 bits?

Sebastien
Sebastien Bourdeauducq | 23 Dec 14:22 2015
Picon
Gravatar

[M-Labs devel] dataflow problems

Hi Florent,

I have written a module that uses the dataflow components in a rather 
simple way:
https://github.com/m-labs/artiq/blob/master/artiq/gateware/rtio/analyzer.py

It takes a source of messages and DMAs it to a ringbuffer in SDRAM, 
using Converter to adapt the messages to the SDRAM word size. The 
dataflow stuff looks nice at first sight and solves the problem almost 
correctly.

But when the DMA is stopped:
* if the message size is smaller than the SDRAM word size, in some cases 
one or more messages that have been emitted are 'stuck' in the converter 
and won't be present in the ringbuffer.
* if the message size is larger than the SDRAM word size, the last 
message gets corrupted if it was being written.

How would you solve this?

I have the impression that in many cases, dataflow solves most of the 
problem but some small but important details like this make it in 
reality unusable or very hacky. Does it make sense to keep the dataflow 
modules in misoc? Are there cases where they are really useful and do 
not require hacks?

Sebastien
Robert Jordens | 22 Dec 01:13 2015
Picon

[M-Labs devel] [PATCH] sim: lower specials, closes #34

---
 migen/fhdl/tools.py   | 43 ++++++++++++++++++++++++++++++++++++++++++-
 migen/fhdl/verilog.py | 46 ++--------------------------------------------
 migen/sim/core.py     |  9 ++++++++-
 3 files changed, 52 insertions(+), 46 deletions(-)

diff --git a/migen/fhdl/tools.py b/migen/fhdl/tools.py
index ddc135c..1ad4646 100644
--- a/migen/fhdl/tools.py
+++ b/migen/fhdl/tools.py
 <at>  <at>  -1,5 +1,5  <at>  <at> 
 from migen.fhdl.structure import *
-from migen.fhdl.structure import _Slice, _Assign
+from migen.fhdl.structure import _Slice, _Assign, _Fragment
 from migen.fhdl.visit import NodeVisitor, NodeTransformer
 from migen.fhdl.bitcontainer import value_bits_sign
 from migen.util.misc import flat_iteration
 <at>  <at>  -296,3 +296,44  <at>  <at>  def rename_clock_domain(f, old, new):
         pass
     else:
         cd.rename(new)
+
+
+def call_special_classmethod(overrides, obj, method, *args, **kwargs):
+    cl = obj.__class__
+    if cl in overrides:
+        cl = overrides[cl]
+    if hasattr(cl, method):
+        return getattr(cl, method)(obj, *args, **kwargs)
+    else:
(Continue reading)

Robert Jordens | 22 Dec 01:11 2015
Picon

[M-Labs devel] [PATCH] sim: lower specials, closes #34

---
 migen/fhdl/tools.py   | 43 ++++++++++++++++++++++++++++++++++++++++++-
 migen/fhdl/verilog.py | 44 +-------------------------------------------
 migen/sim/core.py     |  9 ++++++++-
 3 files changed, 51 insertions(+), 45 deletions(-)

diff --git a/migen/fhdl/tools.py b/migen/fhdl/tools.py
index ddc135c..62fa819 100644
--- a/migen/fhdl/tools.py
+++ b/migen/fhdl/tools.py
 <at>  <at>  -1,5 +1,5  <at>  <at> 
 from migen.fhdl.structure import *
-from migen.fhdl.structure import _Slice, _Assign
+from migen.fhdl.structure import _Slice, _Assign, _Fragment
 from migen.fhdl.visit import NodeVisitor, NodeTransformer
 from migen.fhdl.bitcontainer import value_bits_sign
 from migen.util.misc import flat_iteration
 <at>  <at>  -296,3 +296,44  <at>  <at>  def rename_clock_domain(f, old, new):
         pass
     else:
         cd.rename(new)
+
+
+def _call_special_classmethod(overrides, obj, method, *args, **kwargs):
+    cl = obj.__class__
+    if cl in overrides:
+        cl = overrides[cl]
+    if hasattr(cl, method):
+        return getattr(cl, method)(obj, *args, **kwargs)
+    else:
(Continue reading)

William D. Jones | 4 Dec 06:41 2015
Picon
Picon

[M-Labs devel] [PATCH] Prevent OpenOCD from escaping characters in Windows paths.

Python's os.path facilities will return paths using backslashes on Windows
(even though they are for the most part interchangable). This patch adds braces
around all paths to prevent OpenOCD's TCL command parser from interpreting
escape characters.

William D. Jones (1):
  Prevent backslashes in (Windows) paths from being escaped by OpenOCD's
    TCL implementation.

 migen/build/openocd.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

--

-- 
2.3.5

Robert Jordens | 19 Nov 03:21 2015
Picon

[M-Labs devel] [PATCH] csr/Config: remove add_constant; Config is no Module

---
 misoc/integration/config.py   | 2 +-
 misoc/integration/soc_core.py | 6 +-----
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/misoc/integration/config.py b/misoc/integration/config.py
index c04fc4d..13eeb42 100644
--- a/misoc/integration/config.py
+++ b/misoc/integration/config.py
 <at>  <at>  -2,7 +2,7  <at>  <at>  from migen import *

 from misoc.interconnect.csr import AutoCSR, CSRConstant

-class Config(Module, AutoCSR):
+class Config(AutoCSR):
     def __setitem__(self, key, value):
         setattr(self, key, CSRConstant(value, name=key))

diff --git a/misoc/integration/soc_core.py b/misoc/integration/soc_core.py
index c69b71b..8398284 100644
--- a/misoc/integration/soc_core.py
+++ b/misoc/integration/soc_core.py
 <at>  <at>  -72,7 +72,7  <at>  <at>  class SoCCore(Module):
         self._wb_masters = []
         self._wb_slaves = []

-        self.submodules.config = Config()
+        self.config = Config()

         if cpu_type == "lm32":
(Continue reading)

Robert Jordens | 18 Nov 03:02 2015
Picon

[M-Labs devel] [PATCH 1/2] csr: add CSRConstant and related support

---
 misoc/integration/soc_core.py | 2 ++
 misoc/interconnect/csr.py     | 9 +++++++++
 misoc/interconnect/csr_bus.py | 4 ++++
 3 files changed, 15 insertions(+)

diff --git a/misoc/integration/soc_core.py b/misoc/integration/soc_core.py
index 66c14c8..cb18b35 100644
--- a/misoc/integration/soc_core.py
+++ b/misoc/integration/soc_core.py
 <at>  <at>  -183,6 +183,8  <at>  <at>  class SoCCore(Module):
             self.add_csr_region(name, (self.mem_map["csr"] + 0x800*mapaddr) | self.shadow_base,
self.csr_data_width, csrs)
         for name, memory, mapaddr, mmap in self.csrbankarray.srams:
             self.add_csr_region(name + "_" + memory.name_override, (self.mem_map["csr"] + 0x800*mapaddr) |
self.shadow_base, self.csr_data_width, memory)
+        for name, constant in self.csrbankarray.constants:
+            self.add_constant((name + "_" + constant.name).upper(), constant.value)

         # Interrupts
         for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
diff --git a/misoc/interconnect/csr.py b/misoc/interconnect/csr.py
index 8183b2e..5bfbbe1 100644
--- a/misoc/interconnect/csr.py
+++ b/misoc/interconnect/csr.py
 <at>  <at>  -12,6 +12,14  <at>  <at>  class _CSRBase(DUID):
         self.size = size

 
+class CSRConstant(Constant):
(Continue reading)


Gmane