Guy Hutchison | 12 May 20:41 2015
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[M-Labs devel] [PATCH]: Doc example for case statement

Added code fragment to documentation and supporting Python example
<div><div dir="ltr">Added code fragment to documentation and supporting Python example</div></div>
Sébastien Bourdeauducq | 11 May 07:33 2015
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Re: [M-Labs devel] [PATCH]: Example of instance usage

On 05/07/2015 12:49 AM, Guy Hutchison wrote:
> Are there guidelines on how to make output names stable?

Use name_override - signals that use name_override are registered first
in the namespace and will not be renamed if they are no conflicts
between them. See the build_namespace function in fhdl/namer.py.

> +    convert(sub, sub.io, name='ChildModule').write('ChildModule.v')

There are still some single quotes left...

Sébastien

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William D. Jones | 8 May 07:32 2015
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[M-Labs devel] [PATCH] Rebase- add Windows simulation support

This patch supercedes the previous patches I submitted to add Windows simulation
support. The patch has been updated so that Python code is in PEP8 style and my
additions to the C code match the style used. If there any other formatting changes
to make, please let me know.

William D. Jones (1):
  Add simulation support to Windows using TCP sockets (hardcoded port
    50007- sends packet length at beginning)

 migen/sim/generic.py |  12 +++-
 migen/sim/ipc.py     |  69 +++++++++++++++---
 vpi/Makefile         |   6 +-
 vpi/ipc.c            | 196 +++++++++++++++++++++++++++++++++++++++++----------
 4 files changed, 235 insertions(+), 48 deletions(-)

--

-- 
2.3.5

Robert Jordens | 8 May 02:18 2015
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[M-Labs devel] [PATCH] ise: move -user_new_parser to xst_opt

---
 mibuild/xilinx/ise.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/mibuild/xilinx/ise.py b/mibuild/xilinx/ise.py
index 2fe6933..7f46abc 100644
--- a/mibuild/xilinx/ise.py
+++ b/mibuild/xilinx/ise.py
 <at>  <at>  -54,7 +54,6  <at>  <at>  def _build_xst_files(device, sources, vincpaths, build_name, xst_opt):

     xst_contents = """run
 -ifn {build_name}.prj
--use_new_parser yes
 -top top
 {xst_opt}
 -ofn {build_name}.ngc
 <at>  <at>  -133,6 +132,7  <at>  <at>  bitgen {bitgen_opt} {build_name}.ncd {build_name}.bit
 class XilinxISEToolchain:
     def __init__(self):
         self.xst_opt = """-ifmt MIXED
+-use_new_parser yes
 -opt_mode SPEED
 -register_balancing yes"""
         self.map_opt = "-ol high -w"
--

-- 
1.9.1

Guy Hutchison | 7 May 00:26 2015
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[M-Labs devel] [PATCH]: Update to fhdl doc

Update FHDL documentation section:

 - Add documentation of [some] options to convert section
 - Added genlib section
 - Added documentation for FSM and Hamming blocks to genlib section

Attachment (fhdl.patch): application/octet-stream, 3687 bytes
<div><div dir="ltr">Update FHDL documentation section:<div><br></div>
<div>&nbsp;- Add documentation of [some] options to convert section</div>
<div>&nbsp;- Added genlib section</div>
<div>&nbsp;- Added documentation for FSM and Hamming blocks to genlib section</div>
<div><br></div>
</div></div>
Guy Hutchison | 6 May 01:12 2015
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[M-Labs devel] [PATCH]: Example of instance usage

Example of using instance special
Attachment (instance.patch): application/octet-stream, 4226 bytes
<div><div dir="ltr">Example of using instance special</div></div>
William D. Jones | 5 May 11:22 2015
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[M-Labs devel] [PATCH 0/2] Migen- Add simulation support for Windoiws

The following two commits add support for Migen simulations on Windows OSes. The
IPC protocol is altered to use SOCK_STREAM instead of SOCK_SEQPACKET, which 
Windows does not currently provide. The workaround used here is to send the length
of the incoming data ahead of time and have Windows poll for data until the
expected data length has been received. This mimics the non-blocking behavior
of POSIX IPC, and in practice should not be a problem barring hardware or OS
bugs beyond our control :).

William D. Jones (2):
  Add simulation support to Windows using TCP sockets (hardcoded port
    50007)
  Modify TCP/IP IPC for Windows simulations so that each packet (in bot
    directions) sends the expected length of the packet ahead of time.
    If running on Windows (Python and compiled VPI code), the socket
    send and recv routines will run (possibly more than once) until at
    least the expected number of bytes has been received.

 migen/sim/generic.py |  11 ++-
 migen/sim/ipc.py     |  67 +++++++++++++++---
 vpi/Makefile         |   6 +-
 vpi/ipc.c            | 195 +++++++++++++++++++++++++++++++++++++++++----------
 4 files changed, 231 insertions(+), 48 deletions(-)

--

-- 
2.3.5

Guy Hutchison | 2 May 06:09 2015
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[M-Labs devel] How do you get names of default clk and reset signals?

Is there a way to get the name/signal of the default (or first) clk and reset signal in a module?

If I create an instance of a module:
class sd_input(Module):
    def __init__(self, width=8):
        foo = Signal()
        self.c_srdy = Signal()
        self.c_drdy = Signal()
        self.c_data = Signal(width)
        self.p_srdy = Signal()
        self.p_drdy = Signal()
        self.p_data = Signal(width)
        i = Instance("sd_input",
                     p_width=width,
                     i_c_srdy=self.c_srdy,
                     o_c_drdy=self.c_drdy,
                     i_c_data=self.c_data,
                     o_p_srdy=self.p_srdy,
                     i_p_drdy=self.p_drdy,
                     o_p_data=self.p_data)
        self.specials += i

I would like to hook up the instance to the parent module's clock and reset nets without hard coding them.

If the module doesn't have any sync blocks, is there a way to force it to have a clock domain?

- Guy
<div><div dir="ltr">Is there a way to get the name/signal of the default (or first) clk and reset signal in a module?<div><br></div>
<div>If I create an instance of a module:</div>
<div>
<div>class sd_input(Module):</div>
<div>&nbsp; &nbsp; def __init__(self, width=8):</div>
<div>&nbsp; &nbsp; &nbsp; &nbsp; foo = Signal()</div>
<div>&nbsp; &nbsp; &nbsp; &nbsp; self.c_srdy = Signal()</div>
<div>&nbsp; &nbsp; &nbsp; &nbsp; self.c_drdy = Signal()</div>
<div>&nbsp; &nbsp; &nbsp; &nbsp; self.c_data = Signal(width)</div>
<div>&nbsp; &nbsp; &nbsp; &nbsp; self.p_srdy = Signal()</div>
<div>&nbsp; &nbsp; &nbsp; &nbsp; self.p_drdy = Signal()</div>
<div>&nbsp; &nbsp; &nbsp; &nbsp; self.p_data = Signal(width)</div>
<div>&nbsp; &nbsp; &nbsp; &nbsp; i = Instance("sd_input",</div>
<div>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;p_width=width,</div>
<div>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;i_c_srdy=self.c_srdy,</div>
<div>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;o_c_drdy=self.c_drdy,</div>
<div>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;i_c_data=self.c_data,</div>
<div>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;o_p_srdy=self.p_srdy,</div>
<div>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;i_p_drdy=self.p_drdy,</div>
<div>&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp;o_p_data=self.p_data)</div>
<div>&nbsp; &nbsp; &nbsp; &nbsp; self.specials += i</div>
</div>
<div><br></div>
<div>I would like to hook up the instance to the parent module's clock and reset nets without hard coding them.</div>
<div><br></div>
<div>If the module doesn't have any sync blocks, is there a way to force it to have a clock domain?</div>
<div><br></div>
<div>- Guy</div>
</div></div>
iamsparticle | 1 May 20:41 2015
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[M-Labs devel] [PATCH] Add flash chip parameters to Pipistrello target

From: Zach Smith <IAmSparticle@...>

Hi-

Artiq runtime builds have been failing since (Artiq) 4d31194.
Without having SPI_FLASH_PAGE_SIZE set in (MiSoC)/targets/pipistrello.py,
fs_read() was never compiled causing kloader to fail to link properly.

Setting the proper values here fixes this.

 -Zach

Zach Smith (1):
  targets/pipistrello: add flash sizes

 targets/pipistrello.py | 2 ++
 1 file changed, 2 insertions(+)

--

-- 
1.9.1

Alain Péteut | 30 Apr 11:17 2015
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[M-Labs devel] [PATCH] python setup.py build_sphinx support

This patch enables `python setup.py build_sphinx` support by specifying
the required metadata in `setup.cfg`.

Alain Péteut (1):
  add build_sphinx support for setup.py

 setup.cfg | 3 +++
 1 file changed, 3 insertions(+)
 create mode 100644 setup.cfg

--
2.1.4

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Guy Hutchison | 28 Apr 16:48 2015
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[M-Labs devel] [PATCH]: Documentation on FSM

Short write-up of FSM module with simple example

Attachment (fsm_doc.patch): application/octet-stream, 1649 bytes
<div><div dir="ltr">Short write-up of FSM module with simple example<div><br></div>
</div></div>

Gmane