Yann Sionneau | 18 Apr 17:37 2014

[M-Labs devel] Fix issues in LM32 MMU documentation

Hello M-labs,

Could someone apply this patch [0] to https://github.com/m-labs/lm32/ please?



[0] -- https://github.com/fallen/lm32/commit/4e434fc066ea2cca32a4369d21fdb6a922eeb3a0


Yann Sionneau
Yann Sionneau | 15 Apr 23:10 2014

[M-Labs devel] lm32 mmu asid design and support for it in qemu


Now that NetBSD kernel boots on qemu up to rootfs mounting, I've
embedded an initramfs with a dummy rootfs in the kernel itself.

The kernel then tries to create a new thread for the init program and
naturally wants to allocate an ASID for it.

At first I didn't want to implement ASIDs but after a bit of thoughts
it does not seem so difficult and moreover NetBSD internals are taking
for granted that the TLB supports ASIDs, at least if I want to re-use
MIPS (now generic) tlb code written by matt <at> netbsd.

Indeed, there is already a generic code in NetBSD to handle software
managed TLBs like MIPS or LM32 one. But this code takes for granted
that the TLB has ASIDs.

OK, let's have ASIDs !

So the idea would be to extend PSW to hold the "current_asid" value
for instance PSW[16:12] could hold "current_asid"
Then we need a way to tell which ASID is a TLB entry when inserting it
in the TLB.
Let's use TLBVADDR[11:7] for that!

Then, there is one last trouble, it seems that NetBSD code switches
the ASID while still being in the kernel code... before the actual
context switch. (
(Continue reading)

Sébastien Bourdeauducq | 14 Apr 00:41 2014

[M-Labs devel] a simple example of a custom MiSoC design


for demo/documentation purposes, I've put together a simple example of
how to customize MiSoC:

The code in this repository takes a simple MiSoC base design and adds a
core that blinks a LED at a frequency controllable from the CPU via a
CSR. The repository also contains example software to control the
frequency from the serial console. It can be run on the Papilio Pro, a
small entry-level Spartan-6 LX9 board

Carl J. Treudler | 11 Apr 15:37 2014

[M-Labs devel] Empty or truncated vcd-file

I found some strange behavior of migen when writing the simulation's
output to a vcd-file. The vcd-file is either truncated or completly empty.
Attached to this mail is a tar-file that contains three examples showing
the behavior(s) and some corner-cases that trigger it.

Greetings, Calle

Attachment (empty-vcd-behavior.tar.gz): application/x-gzip, 4347 bytes
I found some strange behavior of migen when writing the simulation's
output to a vcd-file. The vcd-file is either truncated or completly empty.
Attached to this mail is a tar-file that contains three examples showing
the behavior(s) and some corner-cases that trigger it.

Greetings, Calle

Sébastien Bourdeauducq | 8 Apr 15:52 2014

Re: [M-Labs devel] Migen: RTL or Algorithmic?


please note the new mailing list address devel@...

On 04/08/2014 03:36 PM, Khobatha Setetemela wrote:
> Does this imply that the level of abstraction in Migen's FHDL formal
> modelling system is behavioural (algorithmic) and not RTL?

FHDL allows you to describe simple "algorithms", in the sense that you
can have arithmetic/logic operations and conditional structures that
operate on signals and trigger combinatorially or synchronously.
Those algorithms can be easily synthesized to gateware, but FHDL is a
very limited algorithmic language - for example there are no loops.
That's why FHDL can be called "RTL", though it's a slightly confusing name.

FHDL programs ("fragments") can be easily built using a much more
complete and powerful algorithmic language - Python - and that's what
makes the strength of FHDL.

> FHDL models hardware circuits using the notion of combinatorial and
> synchronous statements, and modules. I tend to view it as, in principle,
> still at RTL than algorithmic level.By algorithmic (behavioural)
> generation, C/C++-to-gates such as Xilinx's Vivado HLS and LegUp HLS
> come to mind, not Migen.

Indeed, FHDL is not implementing C/C++/Python/etc. algorithms into
gateware, contrary to those traditional HLS tools.
But Migen contains a module called Pytholite that does this and uses
FHDL as back-end. It's still very limited and far from doing as much as
traditional HLS tools do, but it's conceptually the same idea.
(Continue reading)

Robert Jordens | 4 Apr 06:19 2014

[M-Labs devel] [PATCH 1/4] genlib/fifo: add SyncFIFOClassic and SyncFIFOBuffered

 migen/genlib/fifo.py | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/migen/genlib/fifo.py b/migen/genlib/fifo.py
index 703e7d3..5059694 100644
--- a/migen/genlib/fifo.py
+++ b/migen/genlib/fifo.py
 <at>  <at>  -132,6 +132,55  <at>  <at>  class SyncFIFO(Module, _FIFOInterface):
 			self.readable.eq(self.level != 0)

+class SyncFIFOClassic(Module, _FIFOInterface):
+	def __init__(self, width_or_layout, depth):
+		_FIFOInterface.__init__(self, width_or_layout, depth)
+		self.submodules.fifo = fifo = SyncFIFO(width_or_layout, depth)
+		self.writable = fifo.writable
+		self.din_bits = fifo.din_bits
+		self.din = fifo.din
+		self.we = fifo.we
+		self.readable = fifo.readable
+		self.re = fifo.re
+		self.flush = fifo.flush
+		self.level = fifo.level
+		###
+		self.sync += [
+				If(self.re & self.readable,
(Continue reading)

Alain Péteut | 31 Mar 00:25 2014

Re: [M-Labs devel] mibuild Subsignal() name

Dear all,


I'm creating a `mibuild` `Platform` for the ArriaIIGX PCIe DevBoard I'm currently working with.
Now I have trouble to identify the name for a `Subsignal()` used as clock in 
`CRC_SE()`, which is a thin wrapper of `SimpleCRG()`.
I've tried the `Record()` style with the `/` as separator, but this 
didn't work out.

The fragment looks like this:
(`pcie_refclk`, 0, 
    Subsignal('p', Pin('AE29')),
    Subsignal('n', Pin('AE30')),

then later

lambda p: CRG_SE(p, 'pcie_refclk/p', None, 10.0)

Thanks for any hints! 

Best regards,

Yann Sionneau | 26 Mar 22:32 2014

[M-Labs devel] M-labs popularity


Just to let you know that M-Labs (and Sébastien Bourdeauducq) appears in 
a document given very recently to the French minister of innovation and 
digital economy.
This document lists "the 100 top French developers".

While the choices made in this document can sometimes be questionable, 
it is very pleasant to see that M-labs and Sebastien are listed :)

(French) Online news site link (PDF of the document at the bottom of the 
page, M-labs in page 137-138) : 
(French) the report given to the minister : 

Sorry for the "french links".



Robert Jordens | 24 Mar 16:32 2014

[M-Labs devel] [PATCH 1/3] test/support: fix default ncycles

 migen/test/support.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/migen/test/support.py b/migen/test/support.py
index 394cc42..51a8970 100644
--- a/migen/test/support.py
+++ b/migen/test/support.py
 <at>  <at>  -17,6 +17,6  <at>  <at>  class SimCase:
 	def test_to_verilog(self):

-	def run_with(self, cb, ncycles=-1):
+	def run_with(self, cb, ncycles=None):
 		self.tb.callback = cb
 		run_simulation(self.tb, ncycles=ncycles)


Yann Sionneau | 20 Mar 10:38 2014

[M-Labs devel] NetBSD kernel booting on lm32


I am very happy to announce that the NetBSD/lm32 project is making good 
progress :)

So far NetBSD kernel boots up to searching for Root Device on Qemu : 

Yesterday I tried for the first time to boot it on real hardware, 
Milkymist One board ( http://m-labs.hk/m1.html ) featuring the 
Mikymist-legacy SoC with MMU enabled LM32 softcore, after a bit of 
rework of the uart driver it booted up to irq being enabled : 
https://asciinema.org/a/8288 http://pastebin.com/5X10ampa

Next steps (don't hesitate if you think you can help) :

- Use non-cached mappings for memory mapped registers instead of 
flushing caches
- Find out why no irq handlers are registered when running on real HW
- Find out how I can generate a root fs from just an ELF file (which 
would be a statically linked shell binary called "init")
- Find out how I can embed the previously generated root fs in the 
kernel (ramdisk) and boot on it
- Port some libc ... and then it's endless I guess for userspace
- Add some device drivers (ethernet, audio, framebuffer)

At some point I will add a port to the new Milkymist SoC called "MiSoC" 
which is almost no different in software point of view, except memory 
mapping for SoC registers.

(Continue reading)

Robert Jordens | 20 Mar 00:47 2014

[M-Labs devel] [PATCH 1/2] bus/csr: new simulation api

 migen/bus/csr.py | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/migen/bus/csr.py b/migen/bus/csr.py
index 14708fd..ca55367 100644
--- a/migen/bus/csr.py
+++ b/migen/bus/csr.py
 <at>  <at>  -30,30 +30,30  <at>  <at>  class Initiator(Module):
 		self.read_data_ready = False
 		self.done = False
-	def do_simulation(self, s):
+	def do_simulation(self, selfp):
 		if not self.done:
 			if self.transaction is not None:
 				if isinstance(self.transaction, TRead):
 					if self.read_data_ready:
-						self.transaction.data = s.rd(self.bus.dat_r)
+						self.transaction.data = selfp.bus.dat_r
 						self.transaction = None
 						self.read_data_ready = False
 						self.read_data_ready = True
-					s.wr(self.bus.we, 0)
+					selfp.bus.we = 0
 					self.transaction = None
 			if self.transaction is None:
(Continue reading)