Robert Jordens | 26 Mar 21:12 2015
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[M-Labs devel] [PATCH 1/2] pipistrello: add por reset counter

* this is a temporary fix that should be removed once the
combination of bitstream-in-flash, mor1kx, bios-in-flash works
---
 targets/pipistrello.py | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/targets/pipistrello.py b/targets/pipistrello.py
index d12a1a2..d43a584 100644
--- a/targets/pipistrello.py
+++ b/targets/pipistrello.py
 <at>  <at>  -58,7 +58,12  <at>  <at>  class _CRG(Module):
 		)
 		self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys.clk)
 		reset = platform.request("user_btn")
-		self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | reset)
+		self.clock_domains.cd_por = ClockDomain()
+		por = Signal(max=1 << 11, reset=(1 << 11) - 1)
+		self.sync.por += If(por > 0, por.eq(por - 1))
+		self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
+		self.specials += AsyncResetSynchronizer(self.cd_por, reset)
+		self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | (por > 0))
 		self.specials += Instance("BUFG", i_I=pll[2], o_O=self.cd_sdram_half.clk)
 		self.specials += Instance("BUFPLL", p_DIVIDE=4,
 							i_PLLIN=pll[0], i_GCLK=self.cd_sys.clk,
--

-- 
1.9.1

Robert Jordens | 20 Mar 22:10 2015
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[M-Labs devel] [PATCH 1/2] sim: keep track of unreferenced items

* items that are never referenced in any statements do not end up in the
namespace or in the verilog

* this memorizes items if they can not be found in the namespace and keeps
track of their values
---
 migen/sim/generic.py | 44 +++++++++++++++++++++++++++++++++-----------
 1 file changed, 33 insertions(+), 11 deletions(-)

diff --git a/migen/sim/generic.py b/migen/sim/generic.py
index b290405..2977cf9 100644
--- a/migen/sim/generic.py
+++ b/migen/sim/generic.py
 <at>  <at>  -103,6 +103,7  <at>  <at>  class Simulator:

 		self.sim_functions = fragment.sim
 		self.active_sim_functions = set(f for f in fragment.sim if not hasattr(f, "passive") or not f.passive)
+		self.unreferenced = {}

 	def run(self, ncycles=None):
 		counter = 0
 <at>  <at>  -140,28 +141,43  <at>  <at>  class Simulator:
 				except KeyError:
 					pass

+	def get_unreferenced(self, item, index):
+		try:
+			return self.unreferenced[(item, index)]
+		except KeyError:
+			if isinstance(item, Memory):
(Continue reading)

Robert Jordens | 20 Mar 04:13 2015
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[M-Labs devel] [PATCH] SimActor: allow busy Signal to remain unref'd

* if the busy signal is never used, it will be stripped
  and can not be accessed in simulation

* also add unittest this and generic DFG, SimActors
---
 migen/actorlib/sim.py    |  6 ++++-
 migen/test/test_actor.py | 65 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 70 insertions(+), 1 deletion(-)
 create mode 100644 migen/test/test_actor.py

diff --git a/migen/actorlib/sim.py b/migen/actorlib/sim.py
index dcb9e5e..84f87a5 100644
--- a/migen/actorlib/sim.py
+++ b/migen/actorlib/sim.py
 <at>  <at>  -97,7 +97,11  <at>  <at>  class SimActor(Module):
 		self.submodules.token_exchanger = TokenExchanger(generator, self)

 	def do_simulation(self, selfp):
-		selfp.busy = self.token_exchanger.busy
+		try:
+			selfp.busy = self.token_exchanger.busy
+		except KeyError:
+			# unreferenced signals are lost
+			pass
 	do_simulation.passive = True

 def _dumper_gen(prefix):
diff --git a/migen/test/test_actor.py b/migen/test/test_actor.py
new file mode 100644
index 0000000..d3856a0
(Continue reading)

Robert Jordens | 20 Mar 03:00 2015
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[M-Labs devel] [PATCH] test_actor: unittest dataflow and simulation actors

This started as a test case for a potential bug with

	InsertReset(SimActor(gen), ["sys"])

which fails in simulation with:

KeyError: <Signal busy at 0x7f1f53bace10>

But inserting a reset into a module that does not even have the specified
clock domain is probably not a bug...

The test case is useful nonetheless.
---
 migen/test/test_actor.py | 49 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 migen/test/test_actor.py

diff --git a/migen/test/test_actor.py b/migen/test/test_actor.py
new file mode 100644
index 0000000..1697560
--- /dev/null
+++ b/migen/test/test_actor.py
 <at>  <at>  -0,0 +1,49  <at>  <at> 
+import unittest
+
+from migen.fhdl.std import *
+from migen.flow.actor import *
+from migen.flow.transactions import *
+from migen.flow.network import *
+from migen.actorlib.sim import *
(Continue reading)

Robert Jordens | 19 Mar 18:36 2015
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[M-Labs devel] [PATCH 1/2] pipistrello: fix flash, ddram pin naming

---
 targets/pipistrello.py | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/targets/pipistrello.py b/targets/pipistrello.py
index c2c58a0..35073b1 100644
--- a/targets/pipistrello.py
+++ b/targets/pipistrello.py
 <at>  <at>  -67,7 +67,7  <at>  <at>  class _CRG(Module):
 		]
 		clk_sdram_half_shifted = Signal()
 		self.specials += Instance("BUFG", i_I=pll[3], o_O=clk_sdram_half_shifted)
-		clk = platform.request("sdram_clock")
+		clk = platform.request("ddram_clock")
 		self.specials += Instance("ODDR2", p_DDR_ALIGNMENT="NONE",
 			p_INIT=0, p_SRTYPE="SYNC",
 			i_D0=1, i_D1=0, i_S=0, i_R=0, i_CE=1,
 <at>  <at>  -113,7 +113,7  <at>  <at>  class BaseSoC(SDRAMSoC):
 				read_time=32,
 				write_time=16
 			)
-			self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("sdram"),
+			self.submodules.ddrphy = s6ddrphy.S6DDRPHY(platform.request("ddram"),
 				"LPDDR", rd_bitslip=1, wr_bitslip=3, dqs_ddr_alignment="C1")
 			self.comb += [
 				self.ddrphy.clk4x_wr_strb.eq(self.crg.clk4x_wr_strb),
 <at>  <at>  -124,9 +124,8  <at>  <at>  class BaseSoC(SDRAMSoC):
 	""")
 			self.register_sdram_phy(self.ddrphy, sdram_geom, sdram_timing)

(Continue reading)

Robert Jordens | 19 Mar 18:27 2015
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[M-Labs devel] [PATCH 1/2] pipistrello: compress and load bitstream at 6MHz

---
 mibuild/platforms/pipistrello.py | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/mibuild/platforms/pipistrello.py b/mibuild/platforms/pipistrello.py
index dc9bebd..9c2aed2 100644
--- a/mibuild/platforms/pipistrello.py
+++ b/mibuild/platforms/pipistrello.py
 <at>  <at>  -97,13 +97,13  <at>  <at>  _io = [
 		IOStandard("LVTTL")
 	),

-	("sdram_clock", 0,
+	("ddram_clock", 0,
 		Subsignal("p", Pins("G3")),
 		Subsignal("n", Pins("G1")),
 		IOStandard("MOBILE_DDR")
 	),

-	("sdram", 0,
+	("ddram", 0,
 		Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6")),
 		Subsignal("ba", Pins("F2 F1")),
 		Subsignal("cke", Pins("H7")),
 <at>  <at>  -130,6 +130,7  <at>  <at>  class Platform(XilinxPlatform):

 	def __init__(self):
 		XilinxPlatform.__init__(self, "xc6slx45-csg324-2", _io, _connectors)
+		self.toolchain.bitgen_opt += " -g Compress -g ConfigRate:6"

(Continue reading)

Robert Jordens | 6 Mar 22:56 2015
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[M-Labs devel] [PATCH] vivado: permit resources without pins

This is required if the LOC is done by another, external constraints set,
as in the case of the Zynq Processing System Instance.
---
 mibuild/xilinx/vivado.py | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/mibuild/xilinx/vivado.py b/mibuild/xilinx/vivado.py
index 4974717..418ec2b 100644
--- a/mibuild/xilinx/vivado.py
+++ b/mibuild/xilinx/vivado.py
 <at>  <at>  -19,9 +19,11  <at>  <at>  def _format_constraint(c):
 		return "set_property DRIVE " + str(c.strength)
 	elif isinstance(c, Misc):
 		return "set_property " + c.misc.replace("=", " ")
+	else:
+		raise ValueError("unknown constraint %s" % c)

-def _format_xdc(signame, pin, others, resname):
-	fmt_c = [_format_constraint(c) for c in ([Pins(pin)] + others)]
+def _format_xdc(signame, resname, *constraints):
+	fmt_c = [_format_constraint(c) for c in constraints]
 	fmt_r = resname[0] + ":" + str(resname[1])
 	if resname[2] is not None:
 		fmt_r += "." + resname[2]
 <at>  <at>  -35,9 +37,11  <at>  <at>  def _build_xdc(named_sc, named_pc):
 	for sig, pins, others, resname in named_sc:
 		if len(pins) > 1:
 			for i, p in enumerate(pins):
-				r += _format_xdc(sig + "[" + str(i) + "]", p, others, resname)
+				r += _format_xdc(sig + "[" + str(i) + "]", resname, Pins(p), *others)
(Continue reading)

Robert Jordens | 1 Mar 00:15 2015
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[M-Labs devel] [PATCH] pipistrello: remove unused, unconnected, commented-out pins

---
 mibuild/platforms/pipistrello.py | 2 --
 1 file changed, 2 deletions(-)

diff --git a/mibuild/platforms/pipistrello.py b/mibuild/platforms/pipistrello.py
index 6129f12..84c4b87 100644
--- a/mibuild/platforms/pipistrello.py
+++ b/mibuild/platforms/pipistrello.py
 <at>  <at>  -107,7 +107,6  <at>  <at>  _io = [
 	("sdram", 0,
 		Subsignal("a", Pins("J7 J6 H5 L7 F3 H4 H3 H6 D2 D1 F4 D3 G6")),
 		Subsignal("ba", Pins("F2 F1")),
-		# Subsignal("cs_n", Pins("K6")), # NC
 		Subsignal("cke", Pins("H7")),
 		Subsignal("ras_n", Pins("L5")),
 		Subsignal("cas_n", Pins("K5")),
 <at>  <at>  -115,7 +114,6  <at>  <at>  _io = [
 		Subsignal("dq", Pins("L2 L1 K2 K1 H2 H1 J3 J1 M3 M1 N2 N1 T2 T1 U2 U1")),
 		Subsignal("dqs", Pins("L4 P2")),
 		Subsignal("dm", Pins("K3 K4")),
-		# Subsignal("rzq", Pins("N4")), # NC
 		IOStandard("MOBILE_DDR")
 	)
 ]
--

-- 
1.9.1

Robert Jordens | 1 Mar 00:01 2015
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[M-Labs devel] [PATCH] pipistrello: fix lpddr parameters, crg, flash, style

---
 targets/pipistrello.py | 76 +++++++++++++++++++++++++++++++++-----------------
 1 file changed, 50 insertions(+), 26 deletions(-)

diff --git a/targets/pipistrello.py b/targets/pipistrello.py
index e7bfe9e..3ca47de 100644
--- a/targets/pipistrello.py
+++ b/targets/pipistrello.py
 <at>  <at>  -4,14 +4,19  <at>  <at>  from migen.fhdl.std import *
 from migen.genlib.resetsync import AsyncResetSynchronizer

 from misoclib.mem import sdram
-from misoclib.mem.sdram.phy import gensdrphy
+from misoclib.mem.sdram.phy import s6ddrphy
 from misoclib.mem.flash import spiflash
 from misoclib.soc.sdram import SDRAMSoC

 class _CRG(Module):
 	def __init__(self, platform, clk_freq):
 		self.clock_domains.cd_sys = ClockDomain()
-		self.clock_domains.cd_sys_ps = ClockDomain()
+		self.clock_domains.cd_sdram_half = ClockDomain()
+		self.clock_domains.cd_sdram_full_wr = ClockDomain()
+		self.clock_domains.cd_sdram_full_rd = ClockDomain()
+
+		self.clk4x_wr_strb = Signal()
+		self.clk4x_rd_strb = Signal()

 		f0 = 50*1000*1000
 		clk50 = platform.request("clk50")
(Continue reading)

Robert Jordens | 28 Feb 23:55 2015
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[M-Labs devel] [PATCH 1/2] pipistrello: switch back to xc3sprog and fast (papilio) speed

---
 mibuild/platforms/pipistrello.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/mibuild/platforms/pipistrello.py b/mibuild/platforms/pipistrello.py
index 244cbf6..e8f95f7 100644
--- a/mibuild/platforms/pipistrello.py
+++ b/mibuild/platforms/pipistrello.py
 <at>  <at>  -1,7 +1,7  <at>  <at> 
 from mibuild.generic_platform import *
 from mibuild.crg import SimpleCRG
 from mibuild.xilinx.ise import XilinxISEPlatform
-from mibuild.xilinx.programmer import FpgaProg
+from mibuild.xilinx.programmer import XC3SProg

 _io = [
 	("user_led", 0, Pins("V16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green near hdmi
 <at>  <at>  -119,7 +119,7  <at>  <at>  class Platform(XilinxISEPlatform):
 			lambda p: SimpleCRG(p, "clk50", None), _connectors)

 	def create_programmer(self):
-		return FpgaProg("bscan_spi_lx45_csg324.bit")
+		return XC3SProg("papilio", "bscan_spi_lx45_csg324.bit")

 	def do_finalize(self, fragment):
 		try:
--

-- 
1.9.1

(Continue reading)

Robert Jordens | 27 Feb 04:22 2015
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[M-Labs devel] [PATCH 1/3] add pipistrello platform

---
 mibuild/platforms/pipistrello.py | 128 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 128 insertions(+)
 create mode 100644 mibuild/platforms/pipistrello.py

diff --git a/mibuild/platforms/pipistrello.py b/mibuild/platforms/pipistrello.py
new file mode 100644
index 0000000..cd3d67f
--- /dev/null
+++ b/mibuild/platforms/pipistrello.py
 <at>  <at>  -0,0 +1,128  <at>  <at> 
+from mibuild.generic_platform import *
+from mibuild.crg import SimpleCRG
+from mibuild.xilinx.ise import XilinxISEPlatform
+from mibuild.xilinx.programmer import XC3SProg
+
+_io = [
+	("user_led", 0, Pins("V16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green near hdmi
+	("user_led", 1, Pins("U16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red near hdmi
+	("user_led", 2, Pins("A16"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # green at msd
+	("user_led", 3, Pins("A15"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at msd
+	("user_led", 4, Pins("A12"), IOStandard("LVTTL"), Drive(8), Misc("SLEW=QUIETIO")), # red at usb
+
+	("user_switch", 0, Pins("N14"), IOStandard("LVTTL"), Misc("PULLDOWN")),
+
+	("clk50", 0, Pins("H17"), IOStandard("LVTTL")),
+
+	("serial", 0,
+		Subsignal("tx", Pins("A10"), Misc("SLEW=SLOW")),
+		Subsignal("rx", Pins("A11"), Misc("PULLUP")),
(Continue reading)


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