William D. Jones | 22 Apr 19:18 2016
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[M-Labs devel] [PATCH] Fail gracefully when running build commands on Windows.

Improved version of my previous patch- less redundant code.

William D. Jones (1):
  Add "set -e" equivalent to Windows batch file.

 migen/build/xilinx/ise.py | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

--
2.6.3
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William D. Jones | 22 Apr 14:17 2016
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[M-Labs devel] [PATCH] Fail gracefully when running build commands on Windows.

Some time ago, I added the ability to generate batch files to migen.build, so
that users would not need to depend on a bash shell existing. While Windows
support for Unix utilities is coming around, it's still useful to support
the current behavior for those using strictly Windows tools.

Windows does not have an equivalent of "set -e" as bash does; if a command fails,
then the next command will run (which will also fail) until the end of the file.
This patch adds a commonly-accepted pattern for duplicating "set -e". Unix shell
scripts generated by migen.build are not affected.

William D. Jones (1):
  xilinx/ise: Add "set -e" equivalent to Windows batch file.

 migen/build/xilinx/ise.py | 22 ++++++++++++++++------
 1 file changed, 16 insertions(+), 6 deletions(-)

--
2.6.3
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FabienM | 11 Apr 09:51 2016
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[M-Labs devel] [PATCH] migen/build/platforms: adding apf6sp Armadeus Platform

Hello,

This is just a reminder for adding apf6sp platform in Migen.

The patch in attachment work well with this program to blink the led :

#!/usr/local/bin/python3.4
# -*- coding: utf-8 -*-

from migen import *
from migen.fhdl import *
from migen.build.generic_platform import Pins, IOStandard, Subsignal
from migen.build.platforms import apf6sp

ios = [ ("user_led", 0, Pins("HIROSE:D0")),]

plat = apf6sp.Platform()
plat.add_extension(ios)
led = plat.request("user_led", 0)  # led pin on apf6sp_dev

m = apf6sp.PciePllClockedModule(platform=plat)
counter = Signal(26)
m.comb += led.eq(counter[25])
m.sync += counter.eq(counter + 1)

plat.build(m)

Regards,
Fabien M (Martoni)

(Continue reading)

William D. Jones | 11 Apr 07:47 2016
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[M-Labs devel] [PATCH] Migen should source the Xilinx ISE toolchain by default on Windows.

On Windows, it is not likely that users of ISE toolchain will have the appropriate
environment variables set by default. Since the API change in MiSoC, users no longer
have the ability to override this behavior when building a target. The resulting
batch file generated by Migen will not be able to find any of the Xilinx tools.

Therefore, we should by default insert a call the Xilinx batch file to set up the
environment before running the tools. The call is required to prevent the child
batch file from terminating the parent batch file when the child is done.

For those who already have Xilinx tools on the path before building Migen gateware,
there is no difference in environment other than the Xilinx PATHS being duplicated
for the duration of the cmd.exe subprocess.

William D. Jones (1):
  xilinx/ise: Windows should source Xilinx toolchain by default (fixes
    MiSoC build failures).

 migen/build/xilinx/ise.py | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

--
2.6.3
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Tim 'mithro' Ansell | 25 Mar 15:18 2016
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[M-Labs devel] [PATCH 0/2] Couple of small mibuild fixes.

These two patches fix a couple of small issues in mibuild.

The first one prevents unnecessary rebuilding of the C code by only updating
the files when the contents change.

The second one makes sure the prj file output is deterministic.

Tim 'mithro' Ansell (2):
  mibuild: Don't modify file if contents hasn't changed.
  mibuild: Make source file and include path listing deterministic.

 migen/build/tools.py      | 3 +++
 migen/build/xilinx/ise.py | 8 ++++----
 2 files changed, 7 insertions(+), 4 deletions(-)

--

-- 
2.8.0.rc3.226.g39d4020

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Tim 'mithro' Ansell | 25 Mar 15:11 2016
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[M-Labs devel] [PATCH] build/xilinx/ise: Use separate TNM_NET for period and TIG constraints.

Because ISE is retarded, if you have anything other than period constraints on
a TNM_NET (such as a TIG), then it is unable to trace the constraints through
any of the clock elements like PLLs and DCMs. It will generate the following
warning instead;

> ConstraintSystem - TNM : *** was distributed to a DCM but new TNM constraints
> were not derived. The requirement for derived TNM constraints is that the
> distributed TNM is referenced by no more than a single PERIOD constraint.
> Non-PERIOD referencers are also not allowed.

The requirements for the TNM to be derived is described at
[Timing Constraints User Guide - UG612 (v 11.1.1) April 29, 2009](http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ug612.pdf):

 * The TNM group is used in exactly one PERIOD specification.
 * The TNM group is not used in any FROM-TO or OFFSET specifications.
 * The TNM group is not referenced in any user group definition.

The fix is described in http://www.xilinx.com/support/answers/40007.html ||
http://www.xilinx.com/support/answers/37782.html

Create two TNM Groups for your input clock. One used for the FROM-TO
constraints and the other for the PERIOD propagation.

Fixes https://github.com/m-labs/migen/issues/43
---
 migen/build/xilinx/ise.py | 25 ++++++++++++++++++++-----
 1 file changed, 20 insertions(+), 5 deletions(-)

diff --git a/migen/build/xilinx/ise.py b/migen/build/xilinx/ise.py
index 6d6394f..f4c299f 100644
(Continue reading)

FabienM | 22 Mar 17:19 2016
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[M-Labs devel] [PATCH] migen/build/altera/quartus.py: generating rbf bitstream

Hi,

Here is a patch to generate rbf bitstream format in quartus.py platforms.

Fabien M (Martoni)
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FabienM | 22 Mar 13:34 2016
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[M-Labs devel] [PATCH] Better code documentation an errors messages

Hello,

Here a little patches propositions to improve error message and module
documentation.

Regards,
Fabien M (Martoni)
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FabienM | 17 Mar 14:43 2016
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[M-Labs devel] [PATCH] migen/build/platforms: adding apf6sp Armadeus Platform

Hi all,

Please find in attachment a patch for adding apf6sp platform in Migen.
It's a draft for the moment, because I don't know how to add the clock.
The clock used for the design is generated by the PCIe hardware block
generated by QSys/Quartus (coreclkout). And I don't know how to describe
this in migen platform.

The apf6_sp is a module made by Armadeus System with an i.mx6 plugged on
a CycloneV with the PCI express bus (1xlane).
The CycloneV has it's own DDR3 memory.

http://www.armadeus.com/english/products-processor_boards-apf6_sp.html

Martoni
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Tim Ansell | 15 Mar 08:20 2016
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[M-Labs devel] Students, get paid to hack on MiSoC over summer! (Google Summer of Code)

Hi everyone,

The TimVideos.us project has been accepted into the Google Summer of Code. As our HDMI2USB project is based on MiSoC, we are very interested in students who are proposing ideas related to MiSoC & migen.

You can read more at https://hdmi2usb.tv/gsoc/hdmi2usb/2016/03/14/gsoc-2016/ and I've also included the full announcement below. Please help forward it to anyone who might be interested!

Tim 'mithro' Ansell

---------- Forwarded message ----------
From: Tim Ansell <mithro <at> mithis.com>
Date: 15 March 2016 at 17:33
Subject: TimVideos.us and Google Summer of Code 2016!

Hello everyone!

The TimVideos.us project is happy to announce that it has been selected to participate in the Google Summer of Code for 2016 (GSoC). GSoC is a program where students are paid to contribute to selected open source projects over the northern hemisphere summer, flip bits not burgers!

The application period is now open and students have until 25 March 19:00 UTC to apply to work with the TimVideos.us project. The list of proposal ideas includes contributing to the HDMI2USB and things related to the Numato Opsis.


Due to the focus on hardware, we are very interested in students who are interested in things like VHDL/Verilog and other HDLs, embedded C programming and operating systems and electronic circuit/PCB design. Some possible ideas include;

If you are interested in applying, your first point of call should be our Google Summer of Code page. Even if you can’t apply to GSoC, you can also help us by forwarding this message to anyone you might think who is interested!

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S├ębastien Bourdeauducq | 11 Mar 08:10 2016
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Re: [M-Labs devel] Converter

Hi Florent,

thanks for your MiSoC stream/converter cleanups, looks very good. I have 
committed your last patch.

Regarding the new converter:
* I would remove the first-level user field handling from the Converter, 
and make the Converter receive and send a single field of raw bits. The 
current "stride" iteration over each user field is inflexible, it looks 
arbitrary (i.e. an ad-hoc feature to support byte enable signals in the 
Ethernet core) and it makes the converter do two things at the same 
time. It should be the responsibility of the user to cast their desired 
fields to and from the Converter's raw bit fields. MiSoC may provide a 
convenience StrideConverter module to handle first-level user fields as 
it is done now (the module should consist in a bunch of combinatorial 
slices/concatenations + invokation of the Converter).

The point here is a modular and flexible design, with one component 
doing one single thing. The "cast to/from raw bits" part of 
StrideConverter may even be broken down into a separate StrideCast 
module if you want.

* The Converter should have an option to indicate the number of valid 
chunks transmitted. When this option is enabled, a new field is appended 
to its output, and it contains:
    - for _UpConverter: the number of valid input tokens in the output 
(typically more than 1).
    - for _DownConverter: 1 for the last data chunk generated from an 
input token (the receiver has just got a full input token), 0 for all 
intermediate chunks.
    - for _IdentityConverter: the constant 1.

The Converter is where this problem of partially valid data is 
introduced, it is natural that it should provide a nice mechanism for 
dealing with it. The ARTIQ analyzer, for example, can definitely make 
good use of that.

OK to keep data valid when EOP=1 if that:
* avoids any performance problems with small packets
* stays closer to AXI
* makes your other cores simpler, and avoids the work of refactoring them

For the ARTIQ analyzer, we can make the MessageEncoder generate a 
message of new type ("analyzer stopped") with EOP=1. Software would 
ignore it in most cases (the impact on performance/memory consumption is 
negligible) and it may be a bit useful for debugging.

Sebastien

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