Florent Kermarrec | 21 Aug 13:48 2014
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[M-Labs devel] [PATCH] bscan_spi bistream for KC705 and BIOS in SPI flash

Hi,

here are the patchs to move the BIOS on the KC705 target in the SPI flash.
The bscan_spi is generated with bscan_xc7_spi.vhd of XC3SPROG.

The only strange thing is that dummy parameter of SpiFlash needs to be configured to 11 instead of 15 otherwise we miss the first 2 bytes.

I've check the configuration register of the SPI flash of my board and it has the default value. So there maybe something wrong on the dummy cycle calculation in SpiFlash.

This has been tested on board with XC3SPROG and cable <at> 30Mhz.

Regards,

Florent
Attachment (migen-0001-kc705-add-spiflash-pins.patch): application/octet-stream, 1122 bytes
Attachment (bscan_spi_kc705.tar.gz): application/x-gzip, 111 KiB
<div><div dir="ltr">Hi,<div><br></div>
<div>here are the patchs to move the BIOS on the KC705 target in the SPI flash.</div>
<div>The bscan_spi is generated with&nbsp;bscan_xc7_spi.vhd of XC3SPROG.</div>
<div><br></div>
<div>The only strange thing is that dummy parameter of SpiFlash needs to be configured to 11 instead of 15 otherwise we miss the first 2 bytes.</div>

<div><br></div>
<div>I've check the configuration register of the SPI flash of my board and it has the default value. So there maybe something wrong on the dummy cycle calculation in SpiFlash.</div>
<div><br></div>
<div>

This has been tested on board with XC3SPROG and cable <at> 30Mhz.</div>
<div><br></div>
<div>Regards,</div>
<div><br></div>
<div>Florent</div>
</div></div>
Florent Kermarrec | 20 Aug 17:35 2014
Picon

[M-Labs devel] XC3SPROG loading time on KC705

Hi,

as tested by Sebastien, programmation of the bitstream on the KC705 take a long time with XC3SPROG default configuration:

Using Libftdi, Using JTAG frequency   1.500 MHz from undivided clock
JTAG chainpos: 0 Device IDCODE = 0x33651093 Desc: XC7K325T
Created from NCD file: top;UserID=0XFFFFFFFF
Target device: 7k325tffg900
Created: 2014/08/20 12:38:28
Bitstream length: 91548896 bits
done. Programming time 61919.7 ms

This is due the size of the bistream on the KC705 and the 1.500MHz clock used.

Frequency can be changed with the -J option, but if it's greater than max frequency of the cable it will use that one.

Strangely in cablelist.txt we see:
# Use 1500000 for all cable connected cables and max for all on board cables
[...]
jtaghs1       ftdi    1500000 0x0403:0x6010:Digilent Adept USB Device:0:0x80:0x80:0x00:0x0

while digilent say it can support 30MHz:

with:
jtaghs1       ftdi    3000000 0x0403:0x6010:Digilent Adept USB Device:0:0x80:0x80:0x00:0x0

we are then able to use higher frequencies, but 7.5MHz seems to be already a good compromise:

Using Libftdi, Using JTAG frequency   7.500 MHz from undivided clock
JTAG chainpos: 0 Device IDCODE = 0x33651093 Desc: XC7K325T
Created from NCD file: top;UserID=0XFFFFFFFF
Target device: 7k325tffg900
Created: 2014/08/20 12:38:28
Bitstream length: 91548896 bits
done. Programming time 13395.4 ms

It seems that the cable database can be defined in a environment variable ($CABLEDB).
What do you suggest? Include our cablelist.txt in mibuild (with only the cable we used) and
setting it as an environment variable in XC3SProg __init__?

Now we can also compress the generated bitstream with vivado, which give us:

Using Libftdi, Using JTAG frequency   7.500 MHz from undivided clock
JTAG chainpos: 0 Device IDCODE = 0x33651093 Desc: XC7K325T
Created from NCD file: top;UserID=0XFFFFFFFF
Target device: 7k325tffg900
Created: 2014/08/20 16:56:31
Bitstream length: 18139744 bits
done. Programming time 2490.7 ms

The patch in attachment allows bitstream compression.

Regards,

Florent
<div><div dir="ltr">Hi,<div><br></div>
<div>as tested by Sebastien, programmation of the bitstream on the KC705 take a long time with XC3SPROG default configuration:</div>
<div><br></div>
<div>
<div>Using Libftdi, Using JTAG frequency &nbsp; 1.500 MHz from undivided clock</div>

<div>JTAG chainpos: 0 Device IDCODE = 0x33651093<span class="">	</span>Desc: XC7K325T</div>
<div>Created from NCD file: top;UserID=0XFFFFFFFF</div>
<div>Target device: 7k325tffg900</div>

<div>Created: 2014/08/20 12:38:28</div>
<div>Bitstream length: 91548896 bits</div>
<div>done. Programming time 61919.7 ms</div>
</div>
<div><br></div>
<div>This is due the size of the bistream on the KC705 and the 1.500MHz clock used.</div>

<div><br></div>
<div>Frequency can be changed with the -J option, but if it's greater than max frequency of the cable it will use that one.</div>
<div><br></div>
<div>Strangely in cablelist.txt we see:</div>
<div><div># Use 1500000 for all cable connected cables and max for all on board cables<br>
</div></div>
<div>[...]</div>
<div>jtaghs1 &nbsp; &nbsp; &nbsp; ftdi &nbsp; &nbsp;1500000 0x0403:0x6010:Digilent Adept USB Device:0:0x80:0x80:0x00:0x0<br>
</div>
<div><br></div>
<div>while digilent say it can support 30MHz:</div>
<div>

<a href="http://www.digilentinc.com/Data/Products/JTAG-HS1/JTAG-HS1_rm.pdf">http://www.digilentinc.com/Data/Products/JTAG-HS1/JTAG-HS1_rm.pdf</a><br>
</div>
<div><br></div>
<div>with:<br>
</div>
<div><div>jtaghs1 &nbsp; &nbsp; &nbsp; ftdi &nbsp; &nbsp;3000000 0x0403:0x6010:Digilent Adept USB Device:0:0x80:0x80:0x00:0x0<br>
</div></div>
<div><br></div>
<div>we are then able to use higher frequencies, but 7.5MHz seems to be already a good compromise:</div>
<div><br></div>
<div>
<div>Using Libftdi, Using JTAG frequency &nbsp; 7.500 MHz from undivided clock</div>

<div>JTAG chainpos: 0 Device IDCODE = 0x33651093<span class="">	</span>Desc: XC7K325T</div>
<div>Created from NCD file: top;UserID=0XFFFFFFFF</div>
<div>Target device: 7k325tffg900</div>

<div>Created: 2014/08/20 12:38:28</div>
<div>Bitstream length: 91548896 bits</div>
<div>done. Programming time 13395.4 ms</div>
</div>
<div><br></div>
<div>It seems that the cable database can be defined in a environment variable ($CABLEDB).</div>

<div>What do you suggest? Include our cablelist.txt in mibuild (with only the cable we used) and</div>
<div>setting it as an environment variable in&nbsp;XC3SProg __init__?</div>
<div><br></div>
<div>Now we can also compress the generated bitstream with vivado, which give us:</div>

<div><br></div>
<div>
<div>Using Libftdi, Using JTAG frequency &nbsp; 7.500 MHz from undivided clock</div>
<div>JTAG chainpos: 0 Device IDCODE = 0x33651093<span class="">	</span>Desc: XC7K325T</div>

<div>Created from NCD file: top;UserID=0XFFFFFFFF</div>
<div>Target device: 7k325tffg900</div>
<div>Created: 2014/08/20 16:56:31</div>
<div>Bitstream length: 18139744 bits</div>
<div>done. Programming time 2490.7 ms</div>

</div>
<div><br></div>
<div>The patch in attachment allows bitstream compression.</div>
<div><br></div>
<div>Regards,</div>
<div><br></div>
<div>Florent</div>
</div></div>
Robert Jordens | 17 Aug 22:56 2014
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[M-Labs devel] [PATCH 1/5] vivado: make tcl a list of commands, add reporting

---
 mibuild/xilinx_vivado.py | 29 ++++++++++++++++++-----------
 1 file changed, 18 insertions(+), 11 deletions(-)

diff --git a/mibuild/xilinx_vivado.py b/mibuild/xilinx_vivado.py
index 83dd4ed..9cb192f 100644
--- a/mibuild/xilinx_vivado.py
+++ b/mibuild/xilinx_vivado.py
 <at>  <at>  -42,19 +42,26  <at>  <at>  def _build_xdc(named_sc, named_pc):
 	return r

 def _build_files(device, sources, vincpaths, build_name):
-	tcl_contents = ""
+	tcl = []
 	for filename, language in sources:
-		tcl_contents += "add_files " + filename.replace("\\", "/") + "\n"
+		tcl.append("add_files " + filename.replace("\\", "/"))

-	tcl_contents += "read_xdc %s.xdc\n" %build_name
-	tcl_contents += "synth_design -top top -part %s -include_dirs {%s}\n" %(device, " ".join(vincpaths))
-	tcl_contents += "place_design\n"
-	tcl_contents += "route_design\n"
-	tcl_contents += "report_timing_summary -file %s_timing.rpt\n" %(build_name)
-	tcl_contents += "report_utilization -file %s_utilization.rpt\n" %(build_name)
-	tcl_contents += "write_bitstream -force %s.bit \n" %build_name
-	tcl_contents += "quit\n"	
-	tools.write_to_file(build_name + ".tcl", tcl_contents)
+	tcl.append("read_xdc %s.xdc" %build_name)
+	tcl.append("synth_design -top top -part %s -include_dirs {%s}" %(device, " ".join(vincpaths)))
+	tcl.append("report_utilization -file %s_utilization_synth.rpt" %(build_name))
+	tcl.append("place_design")
+	tcl.append("report_utilization -file %s_utilization_place.rpt" %(build_name))
+	tcl.append("report_io -file %s_io.rpt" %(build_name))
+	tcl.append("report_control_sets -verbose -file %s_control_sets.rpt" %(build_name))
+	tcl.append("report_clock_utilization -file %s_clock_utilization.rpt" %(build_name))
+	tcl.append("route_design")
+	tcl.append("report_route_status -file %s_route_status.rpt" %(build_name))
+	tcl.append("report_drc -file %s_drc.rpt" %(build_name))
+	tcl.append("report_timing_summary -file %s_timing.rpt" %(build_name))
+	tcl.append("report_power -file %s_power.rpt" %(build_name))
+	tcl.append("write_bitstream -force %s.bit " %build_name)
+	tcl.append("quit")
+	tools.write_to_file(build_name + ".tcl", "\n".join(tcl))

 def _run_vivado(build_name, vivado_path, source, ver=None):
 	if sys.platform == "win32" or sys.platform == "cygwin":
--

-- 
1.9.1

Yann Sionneau | 31 Jul 00:34 2014
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[M-Labs devel] [PATCH] Add support for high speed UART

Hello, 

This patch adds support for higher baudrates on MiSoC UART, the following have been tested:

9600, 115200, 3 Mbps, 3.5 Mbps and 4 Mbps have been tested on M1 board
9600, 115200 and 3 Mbps have been tested on Papilio-pro board

Description of changes:

- Using phase accumulator to generate desired frequency
- The generated frequency is not baudrate*16 anymore but just baudrate
- Each RX and TX have their own phase accumulator because they need to be able to send and receive at the same
time and their reset value is different
- RX start bit detection is now faster, at system clock speed instead of baudrate*16 speed, this allows to be
more accurate
- RX phase accumulator only starts incrementing once the falling edge of the start bit is detected. The
initial value of this accumulator is half the value necessary to generate the RX clock pulse so that this
pulse is shifted from half a bit period in order to sample received bits in the middle. When not receiving
(rx_busy == 0), the accumulator stops incrementing
- TX phase accumulator only stars when there is a byte to send, it starts from value 0. We avoid a free-running
accumulator in order to have a precise duration for the start bit and therefore not have transmission
errors. A free-running TX accumulator would leed to arbitrary short start bits
- Adding simulation test bench for RX and TX that you can execute by doing cd misoclib/uart && python __init__.py
- The tuning_word (and therefore the baudrate) is tunable by software via CSR

---
 misoclib/uart/__init__.py | 217 ++++++++++++++++++++++++++++++++++------------
 1 file changed, 160 insertions(+), 57 deletions(-)

diff --git a/misoclib/uart/__init__.py b/misoclib/uart/__init__.py
index 25530d6..58d833a 100644
--- a/misoclib/uart/__init__.py
+++ b/misoclib/uart/__init__.py
 <at>  <at>  -2,55 +2,52  <at>  <at>  from migen.fhdl.std import *
 from migen.genlib.cdc import MultiReg
 from migen.bank.description import *
 from migen.bank.eventmanager import *
+from migen.genlib.record import Record
+from migen.sim.generic import Simulator, TopLevel
+from migen.sim import icarus

 class UART(Module, AutoCSR):
 	def __init__(self, pads, clk_freq, baud=115200):
-		self._rxtx = CSR(8)
-		self._divisor = CSRStorage(16, reset=int(clk_freq/baud/16))
-		
+		self._r_rxtx = CSR(8)
+
 		self.submodules.ev = EventManager()
 		self.ev.tx = EventSourceProcess()
 		self.ev.rx = EventSourcePulse()
 		self.ev.finalize()
-	
+
+		# Tuning word value
+		tuning_word=int((baud/clk_freq)*2**32)
+		self._r_tuning_word = CSRStorage(32, reset=tuning_word)
+
 		###

+		uart_clk_rxen = Signal()
+		uart_clk_txen = Signal()
+		phase_accumulator_rx = Signal(32)
+		phase_accumulator_tx = Signal(32)
+
 		pads.tx.reset = 1

-		enable16 = Signal()
-		enable16_counter = Signal(16)
-		self.comb += enable16.eq(enable16_counter == 0)
-		self.sync += [
-			enable16_counter.eq(enable16_counter - 1),
-			If(enable16,
-				enable16_counter.eq(self._divisor.storage - 1))
-		]
-		
 		# TX
 		tx_reg = Signal(8)
 		tx_bitcount = Signal(4)
-		tx_count16 = Signal(4)
 		tx_busy = self.ev.tx.trigger
 		self.sync += [
-			If(self._rxtx.re,
-				tx_reg.eq(self._rxtx.r),
+			If(self._r_rxtx.re,
+				tx_reg.eq(self._r_rxtx.r),
 				tx_bitcount.eq(0),
-				tx_count16.eq(1),
 				tx_busy.eq(1),
 				pads.tx.eq(0)
-			).Elif(enable16 & tx_busy,
-				tx_count16.eq(tx_count16 + 1),
-				If(tx_count16 == 0,
-					tx_bitcount.eq(tx_bitcount + 1),
-					If(tx_bitcount == 8,
-						pads.tx.eq(1)
-					).Elif(tx_bitcount == 9,
-						pads.tx.eq(1),
-						tx_busy.eq(0)
-					).Else(
-						pads.tx.eq(tx_reg[0]),
-						tx_reg.eq(Cat(tx_reg[1:], 0))
-					)
+			).Elif(uart_clk_txen & tx_busy,
+				tx_bitcount.eq(tx_bitcount + 1),
+				If(tx_bitcount == 8,
+					pads.tx.eq(1)
+				).Elif(tx_bitcount == 9,
+					pads.tx.eq(1),
+					tx_busy.eq(0)
+				).Else(
+					pads.tx.eq(tx_reg[0]),
+					tx_reg.eq(Cat(tx_reg[1:], 0))
 				)
 			)
 		]
 <at>  <at>  -61,39 +58,145  <at>  <at>  class UART(Module, AutoCSR):
 		rx_r = Signal()
 		rx_reg = Signal(8)
 		rx_bitcount = Signal(4)
-		rx_count16 = Signal(4)
 		rx_busy = Signal()
 		rx_done = self.ev.rx.trigger
-		rx_data = self._rxtx.w
+		rx_data = self._r_rxtx.w
 		self.sync += [
 			rx_done.eq(0),
-			If(enable16,
-				rx_r.eq(rx),
-				If(~rx_busy,
-					If(~rx & rx_r, # look for start bit
-						rx_busy.eq(1),
-						rx_count16.eq(7),
-						rx_bitcount.eq(0)
-					)
-				).Else(
-					rx_count16.eq(rx_count16 + 1),
-					If(rx_count16 == 0,
-						rx_bitcount.eq(rx_bitcount + 1),
-
-						If(rx_bitcount == 0,
-							If(rx, # verify start bit
-								rx_busy.eq(0)
-							)
-						).Elif(rx_bitcount == 9,
-							rx_busy.eq(0),
-							If(rx, # verify stop bit
-								rx_data.eq(rx_reg),
-								rx_done.eq(1)
-							)
-						).Else(
-							rx_reg.eq(Cat(rx_reg[1:], rx))
+			rx_r.eq(rx),
+			If(~rx_busy,
+				If(~rx & rx_r, # look for start bit
+					rx_busy.eq(1),
+					rx_bitcount.eq(0),
+				)
+			).Else(
+				If(uart_clk_rxen,
+					rx_bitcount.eq(rx_bitcount + 1),
+					If(rx_bitcount == 0,
+						If(rx, # verify start bit
+							rx_busy.eq(0)
 						)
+					).Elif(rx_bitcount == 9,
+						rx_busy.eq(0),
+						If(rx, # verify stop bit
+							rx_data.eq(rx_reg),
+							rx_done.eq(1)
+						)
+					).Else(
+						rx_reg.eq(Cat(rx_reg[1:], rx))
 					)
 				)
 			)
 		]
+
+
+		self.sync += [
+				If(rx_busy,
+					Cat(phase_accumulator_rx, uart_clk_rxen).eq(phase_accumulator_rx + self._r_tuning_word.storage)
+				).Else(
+					Cat(phase_accumulator_rx, uart_clk_rxen).eq(2**31)
+				),
+
+				If(tx_busy,
+					Cat(phase_accumulator_tx, uart_clk_txen).eq(phase_accumulator_tx + self._r_tuning_word.storage)
+				).Else(
+					Cat(phase_accumulator_tx, uart_clk_txen).eq(0)
+				)
+			     ]
+
+class UARTTB(Module):
+	def __init__(self):
+		MHz=1000000
+		self.clk_freq=83333333
+		self.baud = 3*MHz
+		self.pads = Record([("rx", 1), ("tx", 1)])
+		self.submodules.slave = UART(self.pads, self.clk_freq, self.baud)
+
+	def wait_for(self, ns_time):
+		freq_in_ghz = self.clk_freq/(10**9)
+		period = 1/freq_in_ghz
+		num_loops = int(ns_time/period)
+		for i in range(num_loops+1):
+			yield
+
+	def gen_simulation(self, selfp):
+
+		baud_in_ghz = self.baud/(10**9)
+		uart_period = int(1/baud_in_ghz)
+		half_uart_period = int(1/(2*baud_in_ghz))
+
+		# Set TX an RX lines idle
+		selfp.pads.tx = 1
+		selfp.pads.rx = 1
+		yield
+
+		# First send a few characters
+
+		tx_string = "01234"
+		print("Sending string: " + tx_string)
+		for c in tx_string:
+			while selfp.slave.ev.tx.trigger == 1:
+				yield
+			selfp.slave._r_rxtx.r = ord(c)
+			selfp.slave._r_rxtx.re = 1
+			yield
+			selfp.slave._r_rxtx.re = 0
+
+			yield from self.wait_for(half_uart_period)
+
+			if selfp.pads.tx:
+				print("FAILURE: no start bit sent")
+
+			val = 0
+			for i in range(8):
+				yield from self.wait_for(uart_period)
+				val >>= 1
+				if selfp.pads.tx:
+					val |= 0x80
+
+			yield from self.wait_for(uart_period)
+
+			if selfp.pads.tx == 0:
+				print("FAILURE: no stop bit sent")
+
+			if ord(c) != val:
+				print("FAILURE: sent decimal value "+str(val)+" (char "+chr(val)+") instead of "+c)
+			else:
+				print("SUCCESS: sent "+c)
+
+		# Then receive a character
+
+		rx_string = '5'
+		print("Receiving character "+rx_string)
+		rx_value = ord(rx_string)
+		for i in range(11):
+			if (i == 0):
+				# start bit
+				selfp.pads.rx = 0
+			elif (i == 9):
+				# stop bit
+				selfp.pads.rx = 1
+			elif (i == 10):
+				selfp.pads.rx = 1
+				break
+			else:
+				selfp.pads.rx = 1 if (rx_value & 1) else 0
+				rx_value >>= 1
+			yield from self.wait_for(uart_period)
+
+		rx_value = ord(rx_string)
+		received_value = selfp.slave._r_rxtx.w
+		if (received_value == rx_value):
+			print("RX SUCCESS: ")
+		else:
+			print("RX FAILURE: ")
+
+		print("received "+chr(received_value))
+
+		while True:
+			yield
+
+
+if __name__ == "__main__":
+	with Simulator(UARTTB(), TopLevel("top.vcd", clk_period=int(1/0.08333333)),
icarus.Runner(keep_files=False)) as s:
+		s.run(20000)
--

-- 
2.0.1

Florent Kermarrec | 28 Jul 12:19 2014
Picon

[M-Labs devel] [PATCH] move programmer to mibuild, add IMPACT, add KC705 ddram pins & init

Hi, 

since some of you seems to have the KC705, here are some small patchs that can be useful (exceptially for the programmer).

I find more convenient to have programmer.py in mibuild, so I moved it and added a programmer parameter to platforms. Hope it's OK...

Florent
Attachment (migen-0003-kc705-add-ddram-pins.patch): application/octet-stream, 3007 bytes
Attachment (misoc-0001-move-programmer-to-mibuild.patch): application/octet-stream, 5045 bytes
<div><div dir="ltr">Hi,&nbsp;<div><br></div>
<div>since some of you seems to have the KC705, here are some small patchs that can be useful (exceptially for the programmer).</div>
<div><br></div>
<div>I find more convenient to have programmer.py in mibuild, so I moved it and added a programmer parameter to platforms. Hope it's OK...</div>

<div><br></div>
<div>Florent</div>
</div></div>
Robert Jordens | 28 Jul 03:30 2014
Picon

[M-Labs devel] [PATCH] mibuild.xilinx_vivado: support settingsXX.sh

* in the process refactor the version search, the architecture bit width
 detection, the settings search and all also for xilinx_ise
* use distutils.version.StrictVersion
---
 mibuild/tools.py         | 16 +++++++++++++++-
 mibuild/xilinx_ise.py    | 28 +++++++---------------------
 mibuild/xilinx_tools.py  | 27 +++++++++++++++++++++++++++
 mibuild/xilinx_vivado.py | 13 ++++++-------
 4 files changed, 55 insertions(+), 29 deletions(-)
 create mode 100644 mibuild/xilinx_tools.py

diff --git a/mibuild/tools.py b/mibuild/tools.py
index 35efca7..eb63fb4 100644
--- a/mibuild/tools.py
+++ b/mibuild/tools.py
 <at>  <at>  -1,4 +1,5  <at>  <at> 
-import os
+import os, struct
+from distutils.version import StrictVersion

 def mkdir_noerror(d):
 	try:
 <at>  <at>  -21,3 +22,16  <at>  <at>  def write_to_file(filename, contents, force_unix=False):
 	f = open(filename, "w", newline=newline)
 	f.write(contents)
 	f.close()
+
+def arch_bits():
+	return struct.calcsize("P")*8
+
+def versions(path):
+	for n in os.listdir(path):
+		full = os.path.join(path, n)
+		if not os.path.isdir(full):
+			continue
+		try:
+			yield StrictVersion(n)
+		except ValueError:
+			continue
diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index 56bd414..12a5862 100644
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
 <at>  <at>  -1,5 +1,4  <at>  <at> 
-import os, struct, subprocess, sys
-from decimal import Decimal
+import os, subprocess, sys

 from migen.fhdl.std import *
 from migen.fhdl.specials import SynthesisDirective
 <at>  <at>  -7,7 +6,7  <at>  <at>  from migen.genlib.cdc import *
 from migen.fhdl.structure import _Fragment

 from mibuild.generic_platform import *
-from mibuild import tools
+from mibuild import tools, xilinx_tools

 def _format_constraint(c):
 	if isinstance(c, Pins):
 <at>  <at>  -89,34 +88,21  <at>  <at>  synth_xilinx -arch {arch} -top top -edif {build_name}.edif""".format(arch=arch,
 	if r != 0:
 		raise OSError("Subprocess failed")

-def _is_valid_version(path, v):
-	try: 
-		Decimal(v)
-		return os.path.isdir(os.path.join(path, v))
-	except:
-		return False
-
 def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt,
-		bitgen_opt, ise_commands, map_opt, par_opt):
+		bitgen_opt, ise_commands, map_opt, par_opt, ver=None):
 	if sys.platform == "win32" or sys.platform == "cygwin":
 		source = False
 	build_script_contents = "# Autogenerated by mibuild\nset -e\n"
 	if source:
-		vers = [ver for ver in os.listdir(ise_path) if _is_valid_version(ise_path, ver)]
-		tools_version = max(vers)
-		bits = struct.calcsize("P")*8
-		
-		xilinx_settings_file = os.path.join(ise_path, tools_version, "ISE_DS", "settings{0}.sh".format(bits))
-		if not os.path.exists(xilinx_settings_file) and bits == 64:
-			# if we are on 64-bit system but the toolchain isn't, try the 32-bit env.
-			xilinx_settings_file = os.path.join(ise_path, tools_version, "ISE_DS", "settings32.sh")
-		build_script_contents += "source " + xilinx_settings_file + "\n"
+		settings = xilinx_tools.settings(ise_path, ver, "ISE_DS")
+		build_script_contents += "source " + settings + "\n"
 	if mode == "edif":
 		ext = "edif"
 	else:
 		ext = "ngc"
 		build_script_contents += """
-xst -ifn {build_name}.xst"""
+xst -ifn {build_name}.xst
+"""

 	build_script_contents += """
 ngdbuild {ngdbuild_opt} -uc {build_name}.ucf {build_name}.{ext} {build_name}.ngd
diff --git a/mibuild/xilinx_tools.py b/mibuild/xilinx_tools.py
new file mode 100644
index 0000000..98c2e21
--- /dev/null
+++ b/mibuild/xilinx_tools.py
 <at>  <at>  -0,0 +1,27  <at>  <at> 
+import os
+from distutils.version import StrictVersion
+
+from mibuild import tools
+
+def settings(path, ver=None, sub=None):
+	vers = list(tools.versions(path))
+	if ver is None:
+		ver = max(vers)
+	else:
+		ver = StrictVersion(ver)
+		assert ver in vers
+
+	full = os.path.join(path, str(ver))
+	if sub:
+		full = os.path.join(full, sub)
+
+	search = [64, 32]
+	if tools.arch_bits() == 32:
+		search.reverse()
+
+	for b in search:
+		settings = os.path.join(full, "settings{0}.sh".format(b))
+		if os.path.exists(settings):
+			return settings
+
+	raise ValueError("no settings file found")
diff --git a/mibuild/xilinx_vivado.py b/mibuild/xilinx_vivado.py
index 7149da5..c229ba1 100644
--- a/mibuild/xilinx_vivado.py
+++ b/mibuild/xilinx_vivado.py
 <at>  <at>  -7,7 +7,7  <at>  <at>  from migen.fhdl.std import *
 from migen.fhdl.structure import _Fragment

 from mibuild.generic_platform import *
-from mibuild import tools
+from mibuild import tools, xilinx_tools

 def _format_constraint(c):
 	if isinstance(c, Pins):
 <at>  <at>  -56,15 +56,14  <at>  <at>  def _build_files(device, sources, vincpaths, build_name):
 	tcl_contents += "quit\n"	
 	tools.write_to_file(build_name + ".tcl", tcl_contents)

-def _run_vivado(build_name, vivado_path, source):
+def _run_vivado(build_name, vivado_path, source, ver=None):
 	if sys.platform == "win32" or sys.platform == "cygwin":
 		source = False
 	build_script_contents = "# Autogenerated by mibuild\nset -e\n"
 	if source:
-		raise NotImplementedError
-	build_script_contents += """
-vivado -mode tcl -source {build_name}.tcl
-""".format(build_name=build_name)
+		settings = xilinx_tools.settings(vivado_path, ver)
+		build_script_contents += "source " + settings + "\n"
+	build_script_contents += "vivado -mode tcl -source " + build_name + ".tcl\n"
 	build_script_file = "build_" + build_name + ".sh"
 	tools.write_to_file(build_script_file, build_script_contents, force_unix=True)

 <at>  <at>  -80,7 +79,7  <at>  <at>  class XilinxVivadoPlatform(GenericPlatform):
 		return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)

 	def build(self, fragment, build_dir="build", build_name="top",
-			vivado_path="/opt/Xilinx", source=True, run=True):
+			vivado_path="/opt/Xilinx/Vivado", source=True, run=True):
 		tools.mkdir_noerror(build_dir)
 		os.chdir(build_dir)

--

-- 
1.9.1

Robert Jordens | 27 Jul 04:06 2014
Picon

[M-Labs devel] [PATCH] mibuild.xilinx_vivado: support sourcing settingsXX.sh

---
 mibuild/xilinx_vivado.py | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/mibuild/xilinx_vivado.py b/mibuild/xilinx_vivado.py
index 7149da5..f19dbe4 100644
--- a/mibuild/xilinx_vivado.py
+++ b/mibuild/xilinx_vivado.py
 <at>  <at>  -1,7 +1,7  <at>  <at> 
 # This file is Copyright (c) 2014 Florent Kermarrec <florent@...>
 # License: BSD

-import os, subprocess, sys
+import os, subprocess, sys, struct

 from migen.fhdl.std import *
 from migen.fhdl.structure import _Fragment
 <at>  <at>  -56,12 +56,29  <at>  <at>  def _build_files(device, sources, vincpaths, build_name):
 	tcl_contents += "quit\n"	
 	tools.write_to_file(build_name + ".tcl", tcl_contents)

+def _is_valid_version(path, v):
+	try:
+		return float(v)
+	except:
+		return False
+
 def _run_vivado(build_name, vivado_path, source):
 	if sys.platform == "win32" or sys.platform == "cygwin":
 		source = False
 	build_script_contents = "# Autogenerated by mibuild\nset -e\n"
 	if source:
-		raise NotImplementedError
+		vers = [ver for ver in os.listdir(vivado_path)
+				if _is_valid_version(vivado_path, ver)]
+		tools_version = max(vers)
+		bits = struct.calcsize("P")*8
+
+		xilinx_settings_file = os.path.join(vivado_path, tools_version,
+				"settings{0}.sh".format(bits))
+		if not os.path.exists(xilinx_settings_file) and bits == 64:
+			# if we are on 64-bit system but the toolchain isn't, try the 32-bit env.
+			xilinx_settings_file = os.path.join(vivado_path, tools_version,
+					"settings32.sh")
+		build_script_contents += "source " + xilinx_settings_file + "\n"
 	build_script_contents += """
 vivado -mode tcl -source {build_name}.tcl
 """.format(build_name=build_name)
 <at>  <at>  -80,7 +97,7  <at>  <at>  class XilinxVivadoPlatform(GenericPlatform):
 		return GenericPlatform.get_verilog(self, *args, special_overrides=so, **kwargs)

 	def build(self, fragment, build_dir="build", build_name="top",
-			vivado_path="/opt/Xilinx", source=True, run=True):
+			vivado_path="/opt/Xilinx/Vivado", source=True, run=True):
 		tools.mkdir_noerror(build_dir)
 		os.chdir(build_dir)

--

-- 
1.9.1

Robert Jordens | 25 Jul 07:45 2014
Picon

[M-Labs devel] [PATCH] migen.fhdl.structure: add Signal.like(other)

This is a convenience method. Signal(flen(other)) is used frequently but that
drops the signedness. Signal((other.nbits, other.signed)) would be correct but
is long.
---
 migen/fhdl/structure.py | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 7ab4254..aa33888 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
 <at>  <at>  -274,6 +274,20  <at>  <at>  class Signal(Value):
 	def __repr__(self):
 		return "<Signal " + (self.backtrace[-1][0] or "anonymous") + " at " + hex(id(self)) + ">"

+	 <at> classmethod
+	def like(cls, other):
+		"""Create Signal based on another.
+
+		Parameters
+		----------
+		other : Value
+			Object to base this Signal on.
+
+		See `migen.fhdl.bitcontainer.value_bits_sign`() for details.
+		"""
+		from migen.fhdl.bitcontainer import value_bits_sign
+		return cls(value_bits_sign(other))
+
 class ClockSignal(Value):
 	"""Clock signal for a given clock domain

--

-- 
1.9.1

Florent Kermarrec | 24 Jul 14:40 2014
Picon

[M-Labs devel] [PATCH] migen/sim/generic: use kwargs to pass parameters to icarus.Runner

Hi,

In my case I need to pass "extra_files" parameter to icarus.Runner but using kwargs seems better
than adding all parameters manually.

Florent
<div><div dir="ltr">Hi,<div><br></div>
<div>In my case I need to pass "extra_files" parameter to icarus.Runner but using kwargs seems better</div>
<div>than adding all parameters manually.</div>
<div><br></div>
<div>Florent</div>

</div></div>
Yann Sionneau | 20 Jul 22:07 2014
Picon

[M-Labs devel] update scripts.git

Hello everybody,

Can someone push the attached commit to scripts.git please?

This fixes the compilation of the toolchain on Debian Jessie (8) which is having the same issue as https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=746831 .

I just copied the fix available over there https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=patch;h=27b829ee701e29804216b3803fbaeb629be27491 for GDB and binutils.

Cheers!

--
Yann Sionneau
commit 21c9b99c046dd91dd4279c91bcb7e6d8c7005eb6
Author: Yann Sionneau <yann.sionneau <at> gmail.com>
Date:   Sun Jul 20 22:01:23 2014 +0200

    Fix toolchain compilation on Debian 8 Jessie

diff --git a/compile-lm32-rtems/Makefile b/compile-lm32-rtems/Makefile
index 6a7dbe9..2fc3685 100644
--- a/compile-lm32-rtems/Makefile
+++ b/compile-lm32-rtems/Makefile
 <at>  <at>  -95,7 +95,8  <at>  <at>  gcc-$(GCC_CORE_VERSION)/newlib: .unzip.ok
 	cd newlib-$(NEWLIB_VERSION) && \
 	 patch -p1 < ../$(RTEMS_PATCHES_DIR)/$(NEWLIB_PATCH)
 	cd gdb-$(GDB_VERSION) && \
-	 patch -p1 < ../$(RTEMS_PATCHES_DIR)/$(GDB_PATCH)
+	 patch -p1 < ../$(RTEMS_PATCHES_DIR)/$(GDB_PATCH) && patch -p1 < ../$(MM1_PATCHES_DIR)/gdb-fix-errors-in-bfd-header.patch
+	cd binutils-$(BINUTILS_VERSION) && patch -p1 < ../$(MM1_PATCHES_DIR)/binutils-fix-errors-in-bfd-header.patch
 	touch $ <at> 

 .unzip.ok: $(DL)/$(BINUTILS).ok $(DL)/$(GCC_CORE).ok $(DL)/$(NEWLIB).ok $(DL)/$(GDB).ok
$(DL)/$(MPFR).ok $(DL)/$(MPC).ok $(DL)/$(GMP).ok
diff --git
a/compile-lm32-rtems/milkymist-one-patches/binutils-fix-errors-in-bfd-header.patch b/compile-lm32-rtems/milkymist-one-patches/binutils-fix-errors-in-bfd-header.patch
new file mode 100644
index 0000000..e05b4eb
--- /dev/null
+++ b/compile-lm32-rtems/milkymist-one-patches/binutils-fix-errors-in-bfd-header.patch
 <at>  <at>  -0,0 +1,86  <at>  <at> 
+diff -Naur dl/binutils-2.23.90/bfd/bfd-in2.h binutils-2.23.90/bfd/bfd-in2.h
+--- dl/binutils-2.23.90/bfd/bfd-in2.h	2013-08-27 00:18:06.000000000 +0200
++++ binutils-2.23.90/bfd/bfd-in2.h	2014-07-20 19:53:16.982522896 +0200
+ <at>  <at>  -299,9 +299,6  <at>  <at> 
+ 
+ #define bfd_is_com_section(ptr) (((ptr)->flags & SEC_IS_COMMON) != 0)
+ 
+-#define bfd_set_section_vma(bfd, ptr, val) (((ptr)->vma = (ptr)->lma = (val)),
((ptr)->user_set_vma = TRUE), TRUE)
+-#define bfd_set_section_alignment(bfd, ptr, val) (((ptr)->alignment_power = (val)),TRUE)
+-#define bfd_set_section_userdata(bfd, ptr, val) (((ptr)->userdata = (val)),TRUE)
+ /* Find the address one past the end of SEC.  */
+ #define bfd_get_section_limit(bfd, sec) \
+   (((bfd)->direction != write_direction && (sec)->rawsize != 0	\
+ <at>  <at>  -524,7 +521,6  <at>  <at> 
+ 
+ #define bfd_get_symbol_leading_char(abfd) ((abfd)->xvec->symbol_leading_char)
+ 
+-#define bfd_set_cacheable(abfd,bool) (((abfd)->cacheable = bool), TRUE)
+ 
+ extern bfd_boolean bfd_cache_close
+   (bfd *abfd);
+ <at>  <at>  -1583,6 +1579,28  <at>  <at> 
+   } map_head, map_tail;
+ } asection;
+ 
++static inline bfd_boolean
++bfd_set_section_vma(bfd *abfd ATTRIBUTE_UNUSED, asection *ptr, bfd_vma val)
++{
++	ptr->vma = ptr->lma = val;
++	ptr->user_set_vma = TRUE;
++	return TRUE;
++}
++
++static inline bfd_boolean
++bfd_set_section_userdata(bfd *abfd ATTRIBUTE_UNUSED, asection *ptr, void *val)
++{
++	ptr->userdata = val;
++	return TRUE;
++}
++
++static inline bfd_boolean
++bfd_set_section_alignment(bfd *abfd ATTRIBUTE_UNUSED, asection *ptr, unsigned int val)
++{
++	ptr->alignment_power = val;
++	return TRUE;
++}
++
+ /* Relax table contains information about instructions which can
+    be removed by relaxation -- replacing a long address with a
+    short address.  */
+ <at>  <at>  -6227,6 +6245,14  <at>  <at> 
+   unsigned int selective_search : 1;
+ };
+ 
++static inline bfd_boolean
++bfd_set_cacheable(bfd *abfd, bfd_boolean val)
++{
++	abfd->cacheable = val;
++	return TRUE;
++}
++
++
+ typedef enum bfd_error
+ {
+   bfd_error_no_error = 0,
+diff -Naur dl/binutils-2.23.90/bfd/bfd-in.h binutils-2.23.90/bfd/bfd-in.h
+--- dl/binutils-2.23.90/bfd/bfd-in.h	2013-08-21 09:28:37.000000000 +0200
++++ binutils-2.23.90/bfd/bfd-in.h	2014-07-20 19:46:31.576450617 +0200
+ <at>  <at>  -292,9 +292,6  <at>  <at> 
+ 
+ #define bfd_is_com_section(ptr) (((ptr)->flags & SEC_IS_COMMON) != 0)
+ 
+-#define bfd_set_section_vma(bfd, ptr, val) (((ptr)->vma = (ptr)->lma = (val)),
((ptr)->user_set_vma = TRUE), TRUE)
+-#define bfd_set_section_alignment(bfd, ptr, val) (((ptr)->alignment_power = (val)),TRUE)
+-#define bfd_set_section_userdata(bfd, ptr, val) (((ptr)->userdata = (val)),TRUE)
+ /* Find the address one past the end of SEC.  */
+ #define bfd_get_section_limit(bfd, sec) \
+   (((bfd)->direction != write_direction && (sec)->rawsize != 0	\
+ <at>  <at>  -517,7 +514,6  <at>  <at> 
+ 
+ #define bfd_get_symbol_leading_char(abfd) ((abfd)->xvec->symbol_leading_char)
+ 
+-#define bfd_set_cacheable(abfd,bool) (((abfd)->cacheable = bool), TRUE)
+ 
+ extern bfd_boolean bfd_cache_close
+   (bfd *abfd);
diff --git a/compile-lm32-rtems/milkymist-one-patches/gdb-fix-errors-in-bfd-header.patch b/compile-lm32-rtems/milkymist-one-patches/gdb-fix-errors-in-bfd-header.patch
new file mode 100644
index 0000000..814aa23
--- /dev/null
+++ b/compile-lm32-rtems/milkymist-one-patches/gdb-fix-errors-in-bfd-header.patch
 <at>  <at>  -0,0 +1,88  <at>  <at> 
+diff -Naur dl/gdb-7.5.1/bfd/bfd-in2.h gdb-7.5.1/bfd/bfd-in2.h
+--- dl/gdb-7.5.1/bfd/bfd-in2.h	2012-07-13 17:47:23.000000000 +0200
++++ gdb-7.5.1/bfd/bfd-in2.h	2014-07-20 20:48:58.056706292 +0200
+ <at>  <at>  -301,9 +301,6  <at>  <at> 
+ 
+ #define bfd_is_com_section(ptr) (((ptr)->flags & SEC_IS_COMMON) != 0)
+ 
+-#define bfd_set_section_vma(bfd, ptr, val) (((ptr)->vma = (ptr)->lma = (val)),
((ptr)->user_set_vma = TRUE), TRUE)
+-#define bfd_set_section_alignment(bfd, ptr, val) (((ptr)->alignment_power = (val)),TRUE)
+-#define bfd_set_section_userdata(bfd, ptr, val) (((ptr)->userdata = (val)),TRUE)
+ /* Find the address one past the end of SEC.  */
+ #define bfd_get_section_limit(bfd, sec) \
+   (((bfd)->direction != write_direction && (sec)->rawsize != 0	\
+ <at>  <at>  -526,8 +523,6  <at>  <at> 
+ 
+ #define bfd_get_symbol_leading_char(abfd) ((abfd)->xvec->symbol_leading_char)
+ 
+-#define bfd_set_cacheable(abfd,bool) (((abfd)->cacheable = bool), TRUE)
+-
+ extern bfd_boolean bfd_cache_close
+   (bfd *abfd);
+ /* NB: This declaration should match the autogenerated one in libbfd.h.  */
+ <at>  <at>  -1533,6 +1528,29  <at>  <at> 
+   } map_head, map_tail;
+ } asection;
+ 
++static inline bfd_boolean
++bfd_set_section_vma(bfd *abfd ATTRIBUTE_UNUSED, asection *ptr, bfd_vma val)
++{
++	ptr->vma = ptr->lma = val;
++	ptr->user_set_vma = TRUE;
++	return TRUE;
++}
++
++static inline bfd_boolean
++bfd_set_section_userdata(bfd *abfd ATTRIBUTE_UNUSED, asection *ptr, void *val)
++{
++	ptr->userdata = val;
++	return TRUE;
++}
++
++static inline bfd_boolean
++bfd_set_section_alignment(bfd *abfd ATTRIBUTE_UNUSED, asection *ptr, unsigned int val)
++{
++	ptr->alignment_power = val;
++	return TRUE;
++}
++
++
+ /* Relax table contains information about instructions which can
+    be removed by relaxation -- replacing a long address with a 
+    short address.  */
+ <at>  <at>  -5709,6 +5727,13  <at>  <at> 
+   unsigned int selective_search : 1;
+ };
+ 
++static inline bfd_boolean
++bfd_set_cacheable(bfd *abfd, bfd_boolean val)
++{
++	abfd->cacheable = val;
++	return TRUE;
++}
++
+ typedef enum bfd_error
+ {
+   bfd_error_no_error = 0,
+diff -Naur dl/gdb-7.5.1/bfd/bfd-in.h gdb-7.5.1/bfd/bfd-in.h
+--- dl/gdb-7.5.1/bfd/bfd-in.h	2012-06-04 16:35:20.000000000 +0200
++++ gdb-7.5.1/bfd/bfd-in.h	2014-07-20 20:48:04.153025696 +0200
+ <at>  <at>  -294,9 +294,6  <at>  <at> 
+ 
+ #define bfd_is_com_section(ptr) (((ptr)->flags & SEC_IS_COMMON) != 0)
+ 
+-#define bfd_set_section_vma(bfd, ptr, val) (((ptr)->vma = (ptr)->lma = (val)),
((ptr)->user_set_vma = TRUE), TRUE)
+-#define bfd_set_section_alignment(bfd, ptr, val) (((ptr)->alignment_power = (val)),TRUE)
+-#define bfd_set_section_userdata(bfd, ptr, val) (((ptr)->userdata = (val)),TRUE)
+ /* Find the address one past the end of SEC.  */
+ #define bfd_get_section_limit(bfd, sec) \
+   (((bfd)->direction != write_direction && (sec)->rawsize != 0	\
+ <at>  <at>  -519,8 +516,6  <at>  <at> 
+ 
+ #define bfd_get_symbol_leading_char(abfd) ((abfd)->xvec->symbol_leading_char)
+ 
+-#define bfd_set_cacheable(abfd,bool) (((abfd)->cacheable = bool), TRUE)
+-
+ extern bfd_boolean bfd_cache_close
+   (bfd *abfd);
+ /* NB: This declaration should match the autogenerated one in libbfd.h.  */
commit 21c9b99c046dd91dd4279c91bcb7e6d8c7005eb6
Author: Yann Sionneau <yann.sionneau <at> gmail.com>
Date:   Sun Jul 20 22:01:23 2014 +0200

    Fix toolchain compilation on Debian 8 Jessie

diff --git a/compile-lm32-rtems/Makefile b/compile-lm32-rtems/Makefile
index 6a7dbe9..2fc3685 100644
--- a/compile-lm32-rtems/Makefile
+++ b/compile-lm32-rtems/Makefile
 <at>  <at>  -95,7 +95,8  <at>  <at>  gcc-$(GCC_CORE_VERSION)/newlib: .unzip.ok
 	cd newlib-$(NEWLIB_VERSION) && \
 	 patch -p1 < ../$(RTEMS_PATCHES_DIR)/$(NEWLIB_PATCH)
 	cd gdb-$(GDB_VERSION) && \
-	 patch -p1 < ../$(RTEMS_PATCHES_DIR)/$(GDB_PATCH)
+	 patch -p1 < ../$(RTEMS_PATCHES_DIR)/$(GDB_PATCH) && patch -p1 < ../$(MM1_PATCHES_DIR)/gdb-fix-errors-in-bfd-header.patch
+	cd binutils-$(BINUTILS_VERSION) && patch -p1 < ../$(MM1_PATCHES_DIR)/binutils-fix-errors-in-bfd-header.patch
 	touch $ <at> 

 .unzip.ok: $(DL)/$(BINUTILS).ok $(DL)/$(GCC_CORE).ok $(DL)/$(NEWLIB).ok $(DL)/$(GDB).ok
$(DL)/$(MPFR).ok $(DL)/$(MPC).ok $(DL)/$(GMP).ok
diff --git
a/compile-lm32-rtems/milkymist-one-patches/binutils-fix-errors-in-bfd-header.patch b/compile-lm32-rtems/milkymist-one-patches/binutils-fix-errors-in-bfd-header.patch
new file mode 100644
index 0000000..e05b4eb
--- /dev/null
+++ b/compile-lm32-rtems/milkymist-one-patches/binutils-fix-errors-in-bfd-header.patch
 <at>  <at>  -0,0 +1,86  <at>  <at> 
+diff -Naur dl/binutils-2.23.90/bfd/bfd-in2.h binutils-2.23.90/bfd/bfd-in2.h
+--- dl/binutils-2.23.90/bfd/bfd-in2.h	2013-08-27 00:18:06.000000000 +0200
++++ binutils-2.23.90/bfd/bfd-in2.h	2014-07-20 19:53:16.982522896 +0200
+ <at>  <at>  -299,9 +299,6  <at>  <at> 
+ 
+ #define bfd_is_com_section(ptr) (((ptr)->flags & SEC_IS_COMMON) != 0)
+ 
+-#define bfd_set_section_vma(bfd, ptr, val) (((ptr)->vma = (ptr)->lma = (val)),
((ptr)->user_set_vma = TRUE), TRUE)
+-#define bfd_set_section_alignment(bfd, ptr, val) (((ptr)->alignment_power = (val)),TRUE)
+-#define bfd_set_section_userdata(bfd, ptr, val) (((ptr)->userdata = (val)),TRUE)
+ /* Find the address one past the end of SEC.  */
+ #define bfd_get_section_limit(bfd, sec) \
+   (((bfd)->direction != write_direction && (sec)->rawsize != 0	\
+ <at>  <at>  -524,7 +521,6  <at>  <at> 
+ 
+ #define bfd_get_symbol_leading_char(abfd) ((abfd)->xvec->symbol_leading_char)
+ 
+-#define bfd_set_cacheable(abfd,bool) (((abfd)->cacheable = bool), TRUE)
+ 
+ extern bfd_boolean bfd_cache_close
+   (bfd *abfd);
+ <at>  <at>  -1583,6 +1579,28  <at>  <at> 
+   } map_head, map_tail;
+ } asection;
+ 
++static inline bfd_boolean
++bfd_set_section_vma(bfd *abfd ATTRIBUTE_UNUSED, asection *ptr, bfd_vma val)
++{
++	ptr->vma = ptr->lma = val;
++	ptr->user_set_vma = TRUE;
++	return TRUE;
++}
++
++static inline bfd_boolean
++bfd_set_section_userdata(bfd *abfd ATTRIBUTE_UNUSED, asection *ptr, void *val)
++{
++	ptr->userdata = val;
++	return TRUE;
++}
++
++static inline bfd_boolean
++bfd_set_section_alignment(bfd *abfd ATTRIBUTE_UNUSED, asection *ptr, unsigned int val)
++{
++	ptr->alignment_power = val;
++	return TRUE;
++}
++
+ /* Relax table contains information about instructions which can
+    be removed by relaxation -- replacing a long address with a
+    short address.  */
+ <at>  <at>  -6227,6 +6245,14  <at>  <at> 
+   unsigned int selective_search : 1;
+ };
+ 
++static inline bfd_boolean
++bfd_set_cacheable(bfd *abfd, bfd_boolean val)
++{
++	abfd->cacheable = val;
++	return TRUE;
++}
++
++
+ typedef enum bfd_error
+ {
+   bfd_error_no_error = 0,
+diff -Naur dl/binutils-2.23.90/bfd/bfd-in.h binutils-2.23.90/bfd/bfd-in.h
+--- dl/binutils-2.23.90/bfd/bfd-in.h	2013-08-21 09:28:37.000000000 +0200
++++ binutils-2.23.90/bfd/bfd-in.h	2014-07-20 19:46:31.576450617 +0200
+ <at>  <at>  -292,9 +292,6  <at>  <at> 
+ 
+ #define bfd_is_com_section(ptr) (((ptr)->flags & SEC_IS_COMMON) != 0)
+ 
+-#define bfd_set_section_vma(bfd, ptr, val) (((ptr)->vma = (ptr)->lma = (val)),
((ptr)->user_set_vma = TRUE), TRUE)
+-#define bfd_set_section_alignment(bfd, ptr, val) (((ptr)->alignment_power = (val)),TRUE)
+-#define bfd_set_section_userdata(bfd, ptr, val) (((ptr)->userdata = (val)),TRUE)
+ /* Find the address one past the end of SEC.  */
+ #define bfd_get_section_limit(bfd, sec) \
+   (((bfd)->direction != write_direction && (sec)->rawsize != 0	\
+ <at>  <at>  -517,7 +514,6  <at>  <at> 
+ 
+ #define bfd_get_symbol_leading_char(abfd) ((abfd)->xvec->symbol_leading_char)
+ 
+-#define bfd_set_cacheable(abfd,bool) (((abfd)->cacheable = bool), TRUE)
+ 
+ extern bfd_boolean bfd_cache_close
+   (bfd *abfd);
diff --git a/compile-lm32-rtems/milkymist-one-patches/gdb-fix-errors-in-bfd-header.patch b/compile-lm32-rtems/milkymist-one-patches/gdb-fix-errors-in-bfd-header.patch
new file mode 100644
index 0000000..814aa23
--- /dev/null
+++ b/compile-lm32-rtems/milkymist-one-patches/gdb-fix-errors-in-bfd-header.patch
 <at>  <at>  -0,0 +1,88  <at>  <at> 
+diff -Naur dl/gdb-7.5.1/bfd/bfd-in2.h gdb-7.5.1/bfd/bfd-in2.h
+--- dl/gdb-7.5.1/bfd/bfd-in2.h	2012-07-13 17:47:23.000000000 +0200
++++ gdb-7.5.1/bfd/bfd-in2.h	2014-07-20 20:48:58.056706292 +0200
+ <at>  <at>  -301,9 +301,6  <at>  <at> 
+ 
+ #define bfd_is_com_section(ptr) (((ptr)->flags & SEC_IS_COMMON) != 0)
+ 
+-#define bfd_set_section_vma(bfd, ptr, val) (((ptr)->vma = (ptr)->lma = (val)),
((ptr)->user_set_vma = TRUE), TRUE)
+-#define bfd_set_section_alignment(bfd, ptr, val) (((ptr)->alignment_power = (val)),TRUE)
+-#define bfd_set_section_userdata(bfd, ptr, val) (((ptr)->userdata = (val)),TRUE)
+ /* Find the address one past the end of SEC.  */
+ #define bfd_get_section_limit(bfd, sec) \
+   (((bfd)->direction != write_direction && (sec)->rawsize != 0	\
+ <at>  <at>  -526,8 +523,6  <at>  <at> 
+ 
+ #define bfd_get_symbol_leading_char(abfd) ((abfd)->xvec->symbol_leading_char)
+ 
+-#define bfd_set_cacheable(abfd,bool) (((abfd)->cacheable = bool), TRUE)
+-
+ extern bfd_boolean bfd_cache_close
+   (bfd *abfd);
+ /* NB: This declaration should match the autogenerated one in libbfd.h.  */
+ <at>  <at>  -1533,6 +1528,29  <at>  <at> 
+   } map_head, map_tail;
+ } asection;
+ 
++static inline bfd_boolean
++bfd_set_section_vma(bfd *abfd ATTRIBUTE_UNUSED, asection *ptr, bfd_vma val)
++{
++	ptr->vma = ptr->lma = val;
++	ptr->user_set_vma = TRUE;
++	return TRUE;
++}
++
++static inline bfd_boolean
++bfd_set_section_userdata(bfd *abfd ATTRIBUTE_UNUSED, asection *ptr, void *val)
++{
++	ptr->userdata = val;
++	return TRUE;
++}
++
++static inline bfd_boolean
++bfd_set_section_alignment(bfd *abfd ATTRIBUTE_UNUSED, asection *ptr, unsigned int val)
++{
++	ptr->alignment_power = val;
++	return TRUE;
++}
++
++
+ /* Relax table contains information about instructions which can
+    be removed by relaxation -- replacing a long address with a 
+    short address.  */
+ <at>  <at>  -5709,6 +5727,13  <at>  <at> 
+   unsigned int selective_search : 1;
+ };
+ 
++static inline bfd_boolean
++bfd_set_cacheable(bfd *abfd, bfd_boolean val)
++{
++	abfd->cacheable = val;
++	return TRUE;
++}
++
+ typedef enum bfd_error
+ {
+   bfd_error_no_error = 0,
+diff -Naur dl/gdb-7.5.1/bfd/bfd-in.h gdb-7.5.1/bfd/bfd-in.h
+--- dl/gdb-7.5.1/bfd/bfd-in.h	2012-06-04 16:35:20.000000000 +0200
++++ gdb-7.5.1/bfd/bfd-in.h	2014-07-20 20:48:04.153025696 +0200
+ <at>  <at>  -294,9 +294,6  <at>  <at> 
+ 
+ #define bfd_is_com_section(ptr) (((ptr)->flags & SEC_IS_COMMON) != 0)
+ 
+-#define bfd_set_section_vma(bfd, ptr, val) (((ptr)->vma = (ptr)->lma = (val)),
((ptr)->user_set_vma = TRUE), TRUE)
+-#define bfd_set_section_alignment(bfd, ptr, val) (((ptr)->alignment_power = (val)),TRUE)
+-#define bfd_set_section_userdata(bfd, ptr, val) (((ptr)->userdata = (val)),TRUE)
+ /* Find the address one past the end of SEC.  */
+ #define bfd_get_section_limit(bfd, sec) \
+   (((bfd)->direction != write_direction && (sec)->rawsize != 0	\
+ <at>  <at>  -519,8 +516,6  <at>  <at> 
+ 
+ #define bfd_get_symbol_leading_char(abfd) ((abfd)->xvec->symbol_leading_char)
+ 
+-#define bfd_set_cacheable(abfd,bool) (((abfd)->cacheable = bool), TRUE)
+-
+ extern bfd_boolean bfd_cache_close
+   (bfd *abfd);
+ /* NB: This declaration should match the autogenerated one in libbfd.h.  */
Robert Jordens | 19 Jul 07:19 2014
Picon

[M-Labs devel] [PATCH 2/2] flow.plumbing: spelling

---
 migen/flow/plumbing.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/migen/flow/plumbing.py b/migen/flow/plumbing.py
index cb8abf4..2e2ea98 100644
--- a/migen/flow/plumbing.py
+++ b/migen/flow/plumbing.py
 <at>  <at>  -65,7 +65,7  <at>  <at>  class Multiplexer(Module):
 		
 		###

-		case = {}
+		cases = {}
 		for i, sink in enumerate(sinks):
 			cases[i] = Record.connect(sink, self.source)
 		self.comb += Case(self.sel, cases)
--

-- 
1.9.1


Gmane