[PATCH] libpfm3: Add support for up to 6 counters (AMD Family 15h cpus)

Though Family 15h support has been added earlier, there was a
limitation to use only 4 counters. This patch implements support for
up to 6 counters.

Signed-off-by: Robert Richter <robert.richter <at> amd.com>
---
 lib/pfmlib_amd64.c      |   27 +++++++++++++++++----------
 lib/pfmlib_amd64_priv.h |   31 +++++++++++++++++++++----------
 2 files changed, 38 insertions(+), 20 deletions(-)

diff --git a/lib/pfmlib_amd64.c b/lib/pfmlib_amd64.c
index ab417e3..0194269 100644
--- a/lib/pfmlib_amd64.c
+++ b/lib/pfmlib_amd64.c
 <at>  <at>  -72,8 +72,10  <at>  <at> 
  * 	1 -> PMD1 -> PERCTR1 -> MSR  <at>  0xc0010005
  * 	...
  */
-#define AMD64_SEL_BASE	0xc0010000
-#define AMD64_CTR_BASE	0xc0010004
+#define AMD64_SEL_BASE		0xc0010000
+#define AMD64_CTR_BASE		0xc0010004
+#define AMD64_SEL_BASE_F15H	0xc0010200
+#define AMD64_CTR_BASE_F15H	0xc0010201

 static struct {
 	amd64_rev_t	revision;
 <at>  <at>  -213,6 +215,7  <at>  <at>  pfm_amd64_setup(amd64_rev_t revision)
 		amd64_support.pme_count	= amd64_fam15h_table.num;
 		amd64_pmu.cpu_clks	= amd64_fam15h_table.cpu_clks;

[PATCH] POWER7: update events to latest spec and fix some description errors

Update the POWER7 event set to the latest event specification.

A number of new events have been added, and a number of existing
events have been updated with corrected descriptions.  Also, many
events have been renamed to be more consistent and make it easier
on the tools.

A previous version of the automatic code generation tool corrupted
the event descriptions when the description contained one or more
commas.  This led to incorrect descriptions for many events.  This
patch fixes that issue.

Since this file is automatically generated, the patch is not minimal,
and in addition to that, some of the events whose description has
been corrected, moved relative to where they used to be.

Signed-off-by: Corey Ashford <cjashfor <at> linux.vnet.ibm.com>
---
 lib/events/power7_events.h | 1464 ++++++++++++++++++++++++--------------------
 1 files changed, 802 insertions(+), 662 deletions(-)

diff --git a/lib/events/power7_events.h b/lib/events/power7_events.h
index e2fe9f5..004e868 100644
--- a/lib/events/power7_events.h
+++ b/lib/events/power7_events.h
 <at>  <at>  -20,14 +20,14  <at>  <at> 
 * hand.
 *
 */
-#define POWER7_PME_PM_NEST_4 0

[PATCH] libpfm4: Add AMD Family 15h cpu support 15h cpus)

>From 5b9675cdec1eda745702352044728e03ac65c04e Mon Sep 17 00:00:00 2001
From: Stephane Eranian <eranian <at> google.com>
Date: Mon, 4 Apr 2011 13:38:30 -0400
Subject: [PATCH] libpfm4: Add AMD Family 15h cpu support

This patch is based on the already published libpfm3 patch except that
northbridge events are dropped. These events need to live in a
separate event table.

Signed-off-by: Robert Richter <robert.richter <at> amd.com>
---
 include/perfmon/pfmlib.h         |    2 +
 lib/Makefile                     |    2 +-
 lib/events/amd64_events_fam15h.h | 1198 ++++++++++++++++++++++++++++++++++++++
 lib/pfmlib_amd64.c               |    4 +-
 lib/pfmlib_amd64_priv.h          |    6 +-
 lib/pfmlib_common.c              |    1 +
 lib/pfmlib_priv.h                |    1 +
 7 files changed, 1211 insertions(+), 3 deletions(-)
 create mode 100644 lib/events/amd64_events_fam15h.h

diff --git a/include/perfmon/pfmlib.h b/include/perfmon/pfmlib.h
index e1b80b9..bfcf1b0 100644
--- a/include/perfmon/pfmlib.h
+++ b/include/perfmon/pfmlib.h
 <at>  <at>  -142,6 +142,8  <at>  <at>  typedef enum {
 	PFM_PMU_TORRENT,		/* IBM Torrent hub chip */

 	PFM_PMU_INTEL_SNB,		/* Intel Sandy Bridge (single socket) */
+	PFM_PMU_AMD64_FAM15H_INTERLAGOS,/* AMD AMD64 Fam15h Interlagos */

[PATCH] POWER arch: fix event descriptions for PPC970/970MP, POWER4/5/5+/6

There was a bug in the script that translates the POWER arch event
tables to libpfm4 source.  The bug caused event descriptions that
contained commas to be processed improperly, and the result was
mangled short and long description fields.

This patch fixes those descriptions.  The corrected script
re-processed the original event files and produced new code for
PPC970, PPC970MP, POWER4, POWER5, POWER5+, and POWER6.

Signed-off-by: Corey Ashford <cjashfor <at> linux.vnet.ibm.com>
---
 lib/events/power4_events.h   |   12 +++---
 lib/events/power5+_events.h  |   20 +++++-----
 lib/events/power5_events.h   |   20 +++++-----
 lib/events/power6_events.h   |   76 +++++++++++++++++++++---------------------
 lib/events/ppc970_events.h   |   12 +++---
 lib/events/ppc970mp_events.h |   12 +++---
 6 files changed, 76 insertions(+), 76 deletions(-)

diff --git a/lib/events/power4_events.h b/lib/events/power4_events.h
index 728c773..90b10a9 100644
--- a/lib/events/power4_events.h
+++ b/lib/events/power4_events.h
 <at>  <at>  -707,8 +707,8  <at>  <at>  static const pme_power_entry_t power4_pe[] = {
 	[ POWER4_PME_PM_FPU0_ALL ] = {
 		.pme_name = "PM_FPU0_ALL",
 		.pme_code = 0x103,
-		.pme_short_desc = "FPU0 executed add",
-		.pme_long_desc = " mult",
+		.pme_short_desc = "FPU0 executed add, mult, sub, cmp or sel instruction",

[PATCH] perf_event: fix cgrp event scheduling bug in perf_enable_on_exec()

There is a bug in perf_event_enable_on_exec() when cgroup
events are active on a CPU. The cgroup events may be scheduled
twice causing event state corruptions which eventually may lead
to kernel panics. The reason is that the function needs to first
schedule out the cgroup events, just like for the per-thread events.
The cgroup event are scheduled back in automatically from the
perf_event_context_sched_in() function.

The patch also adds a WARN_ON_ONCE() is perf_cgroup_switch()
to catch any bogus state.

Signed-off-by: Stephane Eranian <eranian <at> google.com>
---

diff --git a/kernel/perf_event.c b/kernel/perf_event.c
index 27960f1..badeb0a 100644
--- a/kernel/perf_event.c
+++ b/kernel/perf_event.c
 <at>  <at>  -364,6 +364,7  <at>  <at>  void perf_cgroup_switch(struct task_struct *task, int mode)
 			}

 			if (mode & PERF_CGROUP_SWIN) {
+				WARN_ON_ONCE(cpuctx->cgrp);
 				/* set cgrp before ctxsw in to
 				 * allow event_filter_match() to not
 				 * have to pass task around
 <at>  <at>  -2423,6 +2424,14  <at>  <at>  static void perf_event_enable_on_exec(struct perf_event_context *ctx)
 	if (!ctx || !ctx->nr_events)
 		goto out;

Re: [PATCH] POWER arch: fix event descriptions for PPC970/970MP, POWER4/5/5+/6

Corey,

Both patches applied as one.
Thanks.

On Tue, Apr 5, 2011 at 11:29 AM, Corey Ashford
<cjashfor <at> linux.vnet.ibm.com> wrote:
> There was a bug in the script that translates the POWER arch event
> tables to libpfm4 source.  The bug caused event descriptions that
> contained commas to be processed improperly, and the result was
> mangled short and long description fields.
>
> This patch fixes those descriptions.  The corrected script
> re-processed the original event files and produced new code for
> PPC970, PPC970MP, POWER4, POWER5, POWER5+, and POWER6.
>
> Signed-off-by: Corey Ashford <cjashfor <at> linux.vnet.ibm.com>
> ---
>  lib/events/power4_events.h   |   12 +++---
>  lib/events/power5+_events.h  |   20 +++++-----
>  lib/events/power5_events.h   |   20 +++++-----
>  lib/events/power6_events.h   |   76 +++++++++++++++++++++---------------------
>  lib/events/ppc970_events.h   |   12 +++---
>  lib/events/ppc970mp_events.h |   12 +++---
>  6 files changed, 76 insertions(+), 76 deletions(-)
>
> diff --git a/lib/events/power4_events.h b/lib/events/power4_events.h
> index 728c773..90b10a9 100644
> --- a/lib/events/power4_events.h
> +++ b/lib/events/power4_events.h

Re: [PATCH] POWER arch: fix event descriptions for PPC970/970MP, POWER4/5/5+/6

On 04/05/2011 09:13 PM, stephane eranian wrote:
> Corey,
> 
> Both patches applied as one.
> Thanks.
> 

Thanks for the quick reply, Stephane.  It's good to get these fixed 

- Corey

------------------------------------------------------------------------------
Xperia(TM) PLAY
It's a major breakthrough. An authentic gaming
smartphone on the nation's most reliable network.
And it wants your games.
http://p.sf.net/sfu/verizon-sfdev

Can pfmon report the data address of the sampled instruction?

------------------------------------------------------------------------------
Xperia(TM) PLAY
It's a major breakthrough. An authentic gaming
smartphone on the nation's most reliable network.
And it wants your games.
http://p.sf.net/sfu/verizon-sfdev

_______________________________________________
perfmon2-devel mailing list
perfmon2-devel <at> lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/perfmon2-devel

libpfm4 AMD Fam14h (bobcat) processor support available

Hi,

Just wanted to let everyone know that I have added libpfm4
support for the AMD Fam14h APU, a.k.a. Bocat.

Simply pull from git.

Event table is based on published spec dated March 2011.

------------------------------------------------------------------------------
Benefiting from Server Virtualization: Beyond Initial Workload 
Consolidation -- Increasing the use of server virtualization is a top
priority.Virtualization can reduce costs, simplify management, and improve 
application availability and disaster protection. Learn more about boosting 
the value of server virtualization. http://p.sf.net/sfu/vmware-sfdev2dev

Re: libpfm4 and AMD Bobcat processors

Rahul,

I have added full support for Fam14h processors. Simply pull
libpfm4 from git and you will get it.

On Tue, Mar 22, 2011 at 10:03 PM, stephane eranian
<eranian <at> googlemail.com> wrote:
> Rahul,
>
> At first glance, looks like the 2.6.35 kernel would work on Family 14h.
> So you're just missing the libpfm4 support, which should not be too
> difficult to add. Looks like fam14h is very close fam10h.
>
>
> On Tue, Mar 22, 2011 at 10:52 PM, Rahul Garg <rahulgarg44 <at> gmail.com> wrote:
>> Ok thanks for the info. I am a little unclear about the kernel. Will I need
>> to update the kernel to newer version to use libpfm4 with this processor
>> (when the support is available in libpfm4)? I was hoping to use 2.6.35 due
>> to other constraints.
>> Thanks for all your work! Have been a happy user of libpfm on other
>> processors.
>> rahul
>> On Tue, Mar 22, 2011 at 5:44 PM, stephane eranian <eranian <at> googlemail.com>
>> wrote:
>>>
>>> Looks like the BKDG just came out a few days ago:
>>>
>>> http://support.amd.com/us/Processor_TechDocs/43170.pdf
>>>
>>> Need to look into the PMU description.
>>>
>>> Also note that beyond libpfm4, the kernel would need to be updated
>>> to support Fam14h.
>>>
>>>
>>> On Tue, Mar 22, 2011 at 10:41 PM, stephane eranian
>>> <eranian <at> googlemail.com> wrote:
>>> > Hi,
>>> >
>>> > Is the spec of Fam 14h available?
>>> >
>>> >
>>> > On Tue, Mar 22, 2011 at 10:37 PM, Rahul Garg <rahulgarg44 <at> gmail.com>
>>> > wrote:
>>> >> Hi.
>>> >>
>>> >> Bobcat is AMD Family 14h. Some products based on it include AMD E-350
>>> >> Fusion
>>> >> APU, E-240 APU and C-50 APU etc.
>>> >>
>>> >>
>>> >> rahul
>>> >>
>>> >> On Tue, Mar 22, 2011 at 5:26 PM, stephane eranian
>>> >> <eranian <at> googlemail.com>
>>> >> wrote:
>>> >>>
>>> >>> Hi,
>>> >>>
>>> >>> On Tue, Mar 22, 2011 at 10:22 PM, Rahul Garg <rahulgarg44 <at> gmail.com>
>>> >>> wrote:
>>> >>> > Hi everyone.
>>> >>> >
>>> >>> > I was wondering if libpfm4 supports this processor? I don't have a
>>> >>> > machine
>>> >>> > yet so cannot test this myself :(
>>> >>> >
>>> >>> I don't know much about Bobcat. It is unlcear to me whether it is
>>> >>> based on
>>> >>> Family 10h or 15h micro-architecture?
>>> >>>
>>> >>> libpfm4 will supports both. Fam15h is in progres..
>>> >>>
>>> >>> > rahul
>>> >>> >
>>> >>> >
>>> >>> >
>>> >>> > ------------------------------------------------------------------------------
>>> >>> > Enable your software for Intel(R) Active Management Technology to
>>> >>> > meet
>>> >>> > the
>>> >>> > growing manageability and security demands of your customers.
>>> >>> > Businesses
>>> >>> > are taking advantage of Intel(R) vPro (TM) technology - will your
>>> >>> > software
>>> >>> > be a part of the solution? Download the Intel(R) Manageability
>>> >>> > Checker
>>> >>> > today! http://p.sf.net/sfu/intel-dev2devmar
>>> >>> > _______________________________________________
>>> >>> > perfmon2-devel mailing list
>>> >>> > perfmon2-devel <at> lists.sourceforge.net
>>> >>> > https://lists.sourceforge.net/lists/listinfo/perfmon2-devel
>>> >>> >
>>> >>> >
>>> >>
>>> >>
>>> >
>>
>>
>

------------------------------------------------------------------------------
Benefiting from Server Virtualization: Beyond Initial Workload 
Consolidation -- Increasing the use of server virtualization is a top
priority.Virtualization can reduce costs, simplify management, and improve 
application availability and disaster protection. Learn more about boosting 
the value of server virtualization. http://p.sf.net/sfu/vmware-sfdev2dev