Corey Ashford | 1 Dec 2009 01:20
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Re: Question about the plm field in perf_event_attr

Hi Stephane,

stephane eranian wrote:
> Corey,
> 
> On Wed, Nov 25, 2009 at 8:56 PM, Corey Ashford
> <cjashfor <at> linux.vnet.ibm.com> wrote:
>>> Ok, I see. The issue here is that you are assuming that attribute values
>>> are all integers. The way it is setup right now, an attribute can have any
>>> type, incl. a string.
>> In my original email, I had a parenthetical question/comment about
>> attributes which have string values.  In the libpfm code, though, the
>> attribute type appears only to have the choices of umask, boolean, or
>> integer:
>>
>> typedef enum {
>>        PFM_ATTR_NONE=0,        /* no attribute */
>>        PFM_ATTR_UMASK,         /* unit mask */
>>        PFM_ATTR_MOD_BOOL,      /* register modifier */
>>        PFM_ATTR_MOD_INTEGER,   /* register modifier */
>>
>>        PFM_ATTR_MAX            /* end-marker */
>> } pfm_attr_t;
>>
>> So I am sure I am missing something somewhere.
>>
> This could be extended with PFM_ATTR_MOD_STRING for instance.
> 
>> That said, we could also support strings by returning, in the array, a
>> pointer to the string instead of a boolean/integer value.  In this case, it
(Continue reading)

Corey Ashford | 1 Dec 2009 01:52
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Re: Question about the plm field in perf_event_attr

Hi Stephane,

stephane eranian wrote:
> Corey,
> 
> I had a second thought on all of this while you are enjoying your long
> week-end ;->
> 
> 
> I think we could use your proposed structure and call as a substitute
> for most of the attribute entry points such as:
>    pfm_get_event_attr_name()
>    pfm_get_event_attr_desc()
>    pfm_get_event_attr_code()
>    pfm_get_event_attr_type()
> 
> struct pfm_attr_info_t {
>    char *name;
>    char *desc;
>    pfm_attr_t type;
>    struct {
>         int is_default:1; /* boolean */
>         int mandatory:1; /* 1 = mandatory, 0 = optional */
>         int reserved:30;
>    }
>    int idx; <<<
>    uint64_t code; <<<
>    int size; <<< /* for future extension */
>    union {
>        uint64_t dfl_64; <<<
(Continue reading)

Corey Ashford | 1 Dec 2009 02:02
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Re: Question about the plm field in perf_event_attr

Typo correction below:

>>>    pfm_attr_t type;
>>>    int has_default; /* boolean */
>> I don't get has_default?
> 
> Just means, this attribute as a default value.  In other words, if this boolean

has_default == 1 means that this attribute *has* a default value. ...

> is false, you must explicitly supply the attribute, e.g. ':e=0'.  If it is true, 
> the following union contains the default value.

--

-- 
Regards,

- Corey

Corey Ashford
Software Engineer
IBM Linux Technology Center, Linux Toolchain
Beaverton, OR
503-578-3507
cjashfor <at> us.ibm.com

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(Continue reading)

stephane eranian | 1 Dec 2009 15:21

Re: kernel panic with monitoring DRAM events



On Mon, Nov 30, 2009 at 4:50 PM, David Nellans <dnellans <at> cs.utah.edu> wrote:
Hi Stephane,

I have been working with Manu - thus the follow up in another thread.

Using system-wide monitoring alleviates the problem as I mentioned in another email.

Its not clear how we can use two monitoring processes for a single 8-thread app without using
system-wide monitoring since each session only tracks what we're launching.  Maybe I'm confused
by terminology.

We got the numbers we were looking for using system-wide monitoring so we're
happy campers, but do let us know if there is anything you'd like us to try to track down any
issues you see for debugging, etc.


Multiplexing of Northbridge events does not work with the current 2.6.30 code base. I was suggesting
you keep using system-wide but instead use two separate runs.
 
pfmon --with-header --outfile=test1 --pin-command -u -eDRAM_ACCESSES_PAGE:HIT,DRAM_ACCESSES_PAGE:MISS,DRAM_ACCESSES_PAGE:CONFLICT,DRAM_ACCESSES_PAGE:ALL  $PASEC_COMMAND

pfmon --with-header --outfile=test2  --pin-command -u -eDRAM_ACCESSES_PAGE:DCT1_PAGE_HIT,DRAM_ACCESSES_PAGE:DCT1_PAGE_MISS,DRAM_ACCESSES_PAGE:DCT1_PAGE_CONFLICT,DRAM_ACCESSES_PAGE:ALL   $PASEC_COMMAND


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David Nellans | 1 Dec 2009 16:20
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Re: kernel panic with monitoring DRAM events



Multiplexing of Northbridge events does not work with the current 2.6.30 code base. I was suggesting
you keep using system-wide but instead use two separate runs.
 
pfmon --with-header --outfile=test1 --pin-command -u -eDRAM_ACCESSES_PAGE:HIT,DRAM_ACCESSES_PAGE:MISS,DRAM_ACCESSES_PAGE:CONFLICT,DRAM_ACCESSES_PAGE:ALL  $PASEC_COMMAND

pfmon --with-header --outfile=test2  --pin-command -u -eDRAM_ACCESSES_PAGE:DCT1_PAGE_HIT,DRAM_ACCESSES_PAGE:DCT1_PAGE_MISS,DRAM_ACCESSES_PAGE:DCT1_PAGE_CONFLICT,DRAM_ACCESSES_PAGE:ALL   $PASEC_COMMAND

Unfortunately running 2 separate instances (4 threads each) of PARSEC isn't possible as it results in different memory working sets than a single 8 thread instance.  We chose to just use
the system-wide command (so it wouldn't panic) on a single memory controller and average our results across multiple runs looking at the different controllers.

cheers
-dave



-----------------------------
David W Nellans
dnellans <at> cs.utah.edu
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stephane eranian | 4 Dec 2009 12:16

updated F_SETOWN_EX support

Hi,

The F_SETOWN_EX support is officially out with the
release of 2.6.32.

I am glad this problem is finally solved.

But there is a small catch. During the review process, people
pointed out that the values used for the new fcntl() commands
were conflicting with existing commands on i386. Thus, they
were changed.

I have updated both libpfm and the 2.6.30 perfmon GIT tree
to match upstream.

The following changes were made:

-#define F_SETOWN_EX	12
-#define F_GETOWN_EX	13
+#define F_SETOWN_EX     15
+#define F_GETOWN_EX     16

-#define F_OWNER_GID	2
+#define F_OWNER_PGRP    2

Given that those constant are not yet in libc nor kernel-headers, most
likely they were hardcoded into applications. The change requires those
applications to be updated. Recompilation is NOT enough.

Please update your code if you were already using this new feature.

Thanks.

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stephane eranian | 4 Dec 2009 16:37

Re: Question about the plm field in perf_event_attr

Corey,

Sorry for the delay, busy week.

I think this is getting quite complicated.

Let's go back to the problem we were trying to solve.

The idea is to have an API for tools to discover what are the
default settings for each possible event. Today, some attributes
may be omitted by users in which case the library may pick
some default or simply fail,e.g., unit masks.

It seems we would like to relax some of the constraints a little
bit. For instance, we would like the library to pick a default
unit mask for some events. I seem to recall Oprofile does that.

For other attributes such as modifiers (edge, invert, anythread,)
or priv level, we would like the library to pick some defaults as
well. Note that it already does that, all modifiers are 0, unless
hardcoded by the events or unit masks.

In either case, we need an API to query the defaults, such that
a tool could at least print the full event name string when it prints
the final count. That way, the user would know what was actually
measured. For instance, if I pass UOPS_ISSUED, it is interesting
to know that UOPS_ISSUED:ANY was actually measured.

There could be multiple default unit masks per event. For instance,
On Intel X86, certain events have unit masks "groups":

        { .name = "L2_LD",
          .code = 0x29,
          .flags = INTEL_X86_CSPEC|INTEL_X86_MESI,
          .cntmsk = 0x3,
         .modmsk = INTEL_V2_ATTRS,
          .desc =  "L2 cache reads",
          .umasks = {
                INTEL_CORE_MESI_UMASKS,
                INTEL_CORE_SPECIFICITY_UMASKS,
                INTEL_CORE_HW_PREFETCH_UMASKS
           },

Where:
#define INTEL_CORE_SPECIFICITY_UMASKS \
                { .uname = "SELF",\
                  .udesc = "This core",\
                  .ucode = 0x40\
                },\
                { .uname = "BOTH_CORES",\
                  .udesc = "Both cores",\
                  .ucode = 0xc0\
                }

#define INTEL_CORE_HW_PREFETCH_UMASKS \
                { .uname = "ANY",\
                  .udesc = "All inclusive",\
                  .ucode = 0x30\
                },\
                { .uname = "PREFETCH",\
                  .udesc = "Hardware prefetch only",\
                  .ucode = 0x10\
                }

In this particular case, a reasonable default would be

L2_LD:ANY:MESI:CORE_SELF:u=1:k=0:i=0:e=0:c=0

I think the only reasonable approach would be for the
tool to iterate over all the attributes and query 'default'
information. So here, it would return:

M: is_dfl=0
E: is_dfl=0
S: is_dfl=0
I: is_dfl=0
MESI: is_dfl=1 value=0xf (unit mask value)
CORE_BOTH: is_dfl=0
CORE_SELF: is_dfl=1
u: is_dfl=1 value=1
k: is_dfl=0
i: is_dfl=0
e: is_dfl=0
c: is_dfl=0

Now how do we go about implementing this?
I have avoided passing complex data structures to libpfm thus far.
The main reason is extensibility and simplicity. The downside
is you have lots of simple calls. We could continue down that
path and add a call just to return the default setting information.
Alternatively, we could go with what I proposed in an earlier
message, basically two calls, one for events, one for attributes
which cover all existing functionalities + the default settings.

If we go with a dedicated call, then we either have to pass
a struct and a pointer to a boolean (is_default) and a void *
to get the value out.

I have been toying with the structure approach using the following:
typedef struct {
        const char *name;
        const char *desc;
        pfm_pmu_t pmu;
        int idx;
        int nattrs;
        int size;
        uint64_t code;
        uint64_t reserved[9];
} pfm_event_info_t;

typedef struct {
        const char *name;
        const char *desc;
        pfm_attr_t type;
        struct {
                int is_dfl:1; /* is default */
                int reserved:31;
        };
        int idx;
        int size;
        uint64_t code;
        union {
                uint64_t dfl_val64;
                const char *dfl_str;
                int dfl_bool;
                int dfl_int;
        };
        uint64_t reserved1[6];
} pfm_event_attr_info_t;

int pfm_get_event_info(int idx, pfm_event_info_t *info, size_t sz);
int pfm_get_event_attr_info(int idx, int attr_idx,
pfm_event_attr_info_t *info, size_t sz);

Advantage is that this is clearly more compact, a couple of calls and you get
everything you need. The more I think about it, the more I think this could be
a workable solution. The type of values is already well covered. There are
reserved field for future extensions. The size parameter is to enable extensions
the way they do it with perf_events.

What do you think?

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Corey Ashford | 4 Dec 2009 23:16
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Re: Question about the plm field in perf_event_attr

Hi Stephane,

This looks very interesting.  A couple of comments/questions
below:

stephane eranian wrote:
> Corey,
>...
> I think this is getting quite complicated.
> 
> Let's go back to the problem we were trying to solve.
> 
> The idea is to have an API for tools to discover what are the
> default settings for each possible event. Today, some attributes
> may be omitted by users in which case the library may pick
> some default or simply fail,e.g., unit masks.
> 
> It seems we would like to relax some of the constraints a little
> bit. For instance, we would like the library to pick a default
> unit mask for some events. I seem to recall Oprofile does that.
> 
> For other attributes such as modifiers (edge, invert, anythread,)
> or priv level, we would like the library to pick some defaults as
> well. Note that it already does that, all modifiers are 0, unless
> hardcoded by the events or unit masks.
> 
> In either case, we need an API to query the defaults, such that
> a tool could at least print the full event name string when it prints
> the final count. That way, the user would know what was actually
> measured. For instance, if I pass UOPS_ISSUED, it is interesting
> to know that UOPS_ISSUED:ANY was actually measured.
> 
> There could be multiple default unit masks per event. For instance,
> On Intel X86, certain events have unit masks "groups":
> 
>         { .name = "L2_LD",
>           .code = 0x29,
>           .flags = INTEL_X86_CSPEC|INTEL_X86_MESI,
>           .cntmsk = 0x3,
>           .modmsk = INTEL_V2_ATTRS,
>           .desc =  "L2 cache reads",
>           .umasks = {
>                 INTEL_CORE_MESI_UMASKS,
>                 INTEL_CORE_SPECIFICITY_UMASKS,
>                 INTEL_CORE_HW_PREFETCH_UMASKS
>            },
> 
> Where:
> #define INTEL_CORE_SPECIFICITY_UMASKS \
>                 { .uname = "SELF",\

I assume this is supposed to be
                     .uname = "CORE_SELF",\

>                   .udesc = "This core",\
>                   .ucode = 0x40\
>                 },\
>                 { .uname = "BOTH_CORES",\

and
                     .uname = "CORE_BOTH",\

>                   .udesc = "Both cores",\
>                   .ucode = 0xc0\
>                 }
> 
> #define INTEL_CORE_HW_PREFETCH_UMASKS \
>                 { .uname = "ANY",\
>                   .udesc = "All inclusive",\
>                   .ucode = 0x30\
>                 },\
>                 { .uname = "PREFETCH",\
>                   .udesc = "Hardware prefetch only",\
>                   .ucode = 0x10\
>                 }
> 
> In this particular case, a reasonable default would be
> 
> L2_LD:ANY:MESI:CORE_SELF:u=1:k=0:i=0:e=0:c=0
> 
> I think the only reasonable approach would be for the
> tool to iterate over all the attributes and query 'default'
> information. So here, it would return:
> 
> M: is_dfl=0
> E: is_dfl=0
> S: is_dfl=0
> I: is_dfl=0
> MESI: is_dfl=1 value=0xf (unit mask value)
> CORE_BOTH: is_dfl=0
> CORE_SELF: is_dfl=1
> u: is_dfl=1 value=1
> k: is_dfl=0
> i: is_dfl=0
> e: is_dfl=0
> c: is_dfl=0

Just so I'm certain I understand what you are saying, if I specify

L2_LD:MESI:M=0

would that be an error (because M=0 conflicts with MESI) ?

I would assume it would be, and we'd have to come up with some way of detecting 
these sorts of errors.  If it would be legal to specify one group and then alter 
it with an individual attribute, would the semantics differ from specifying them 
in the opposite order?

L2_LD:M=0:MESI

In this case I'm saying, I want M=0 but MESI otherwise...

Assuming this mixing groups and individual attributes is just not allowed, would 
the following be an error?
L2_LD:M=0

... where you only specify one of the individual attributes and not the 
others... do the others default to something?  They have is_dfl set to zero, but 
can they still have default values?  Or do you start with the default group, and 
then allow modification of individual attributes (i.e. L2_LD:M=0 would be sort 
of an implicit L2_LD:MESI:M=0)

Also, there definitely needs to be error checking against specifying two
groups:

L2_LD:ANY:CORE_BOTH:CORE_SELF

> 
> Now how do we go about implementing this?
> I have avoided passing complex data structures to libpfm thus far.
> The main reason is extensibility and simplicity. The downside
> is you have lots of simple calls. We could continue down that
> path and add a call just to return the default setting information.
> Alternatively, we could go with what I proposed in an earlier
> message, basically two calls, one for events, one for attributes
> which cover all existing functionalities + the default settings.
> 
> If we go with a dedicated call, then we either have to pass
> a struct and a pointer to a boolean (is_default) and a void *
> to get the value out.
> 
> I have been toying with the structure approach using the following:
> typedef struct {
>         const char *name;
>         const char *desc;
>         pfm_pmu_t pmu;
>         int idx;
>         int nattrs;
>         int size;
>         uint64_t code;
>         uint64_t reserved[9];
> } pfm_event_info_t;
> 
> typedef struct {
>         const char *name;
>         const char *desc;
>         pfm_attr_t type;
>         struct {
>                 int is_dfl:1; /* is default */
>                 int reserved:31;
>         };
>         int idx;
>         int size;
>         uint64_t code;
>         union {
>                 uint64_t dfl_val64;
>                 const char *dfl_str;
>                 int dfl_bool;
>                 int dfl_int;
>         };
>         uint64_t reserved1[6];
> } pfm_event_attr_info_t;
> 
> int pfm_get_event_info(int idx, pfm_event_info_t *info, size_t sz);
> int pfm_get_event_attr_info(int idx, int attr_idx,
> pfm_event_attr_info_t *info, size_t sz);
> 
> Advantage is that this is clearly more compact, a couple of calls and you get
> everything you need. The more I think about it, the more I think this could be
> a workable solution. The type of values is already well covered. There are
> reserved field for future extensions. The size parameter is to enable extensions
> the way they do it with perf_events.
> 
> What do you think?

If we can resolve the rules for combining default groups with individual 
attributes, I think this is a good solution, and would provide a tool with lots 
of useful information to display and options to offer to the user.

One downside is that it might be somewhat difficult to describe in the 
documentation.

--

-- 
Regards,

- Corey

Corey Ashford
Software Engineer
IBM Linux Technology Center, Linux Toolchain
Beaverton, OR
503-578-3507
cjashfor <at> us.ibm.com

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Vince Weaver | 5 Dec 2009 00:28
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[patch] a few more MIPS fixes

Hello

here are a few more MIPS issues.  Sorry it is not broken out properly, but 
I defend my PhD next week so I am a bit busy.  Wantd to send this out 
before I forgot about it.

On MIPS R12000 the event mask is 5 bits, not 4.  In theory this is 
backwards compatible, at least to R10000.  The way things currently are, 
the top bit is lost and thus the top 16 events alias to the bottom ones.  
This took me a while to track down, bitfields can be annoying.  I vaguely 
feel like this issue might have come up before in the past, but my search 
of the archives wasn't turning it up.

The other issue is one where the debug message was printing wrong values 
when compiled on a 32-bit host.  Not sure if it's the right fix.

MIPS support for perfmon2 indeed still works, although in sampled mode it 
gets stuck on floating point programs, haven't had time to find out why.

I also was using prefmon2 on an older itanium machine with only the stock 
perfmon support.  That mostly works too, though there are a few unused 
variable warnings that turn to errors due to -Werror being on.

Vince

diff -u -r libpfm-3.9/include/perfmon/pfmlib_gen_mips64.h libpfm-3.9-vmw/include/perfmon/pfmlib_gen_mips64.h
--- libpfm-3.9/include/perfmon/pfmlib_gen_mips64.h	2008-05-30 07:23:03.000000000 -0400
+++ libpfm-3.9-vmw/include/perfmon/pfmlib_gen_mips64.h	2009-12-04 17:02:35.000000000 -0500
 <at>  <at>  -61,8 +61,8  <at>  <at> 
 		unsigned long sel_sup:1;		/* supervisor level */
 		unsigned long sel_usr:1;		/* user level */
 	        unsigned long sel_int:1;		/* enable intr */
-	  	unsigned long sel_event_mask:4;		/* event mask */
-		unsigned long sel_res1:23;		/* reserved */
+	  	unsigned long sel_event_mask:5;		/* event mask */
+		unsigned long sel_res1:22;		/* reserved */
 		unsigned long sel_res2:32;		/* reserved */
 	} perfsel;
 } pfm_gen_mips64_sel_reg_t;
 <at>  <at>  -73,8 +73,8  <at>  <at> 
 	uint64_t	val;				/* complete register value */
 	struct {
 		unsigned long sel_res2:32;		/* reserved */
-		unsigned long sel_res1:23;		/* reserved */
-	  	unsigned long sel_event_mask:4;		/* event mask */
+		unsigned long sel_res1:22;		/* reserved */
+	  	unsigned long sel_event_mask:5;		/* event mask */
 	        unsigned long sel_int:1;		/* enable intr */
 		unsigned long sel_usr:1;		/* user level */
 		unsigned long sel_sup:1;		/* supervisor level */
diff -u -r libpfm-3.9/lib/pfmlib_gen_mips64.c libpfm-3.9-vmw/lib/pfmlib_gen_mips64.c
--- libpfm-3.9/lib/pfmlib_gen_mips64.c	2008-08-07 14:57:32.000000000 -0400
+++ libpfm-3.9-vmw/lib/pfmlib_gen_mips64.c	2009-12-04 17:05:49.000000000 -0500
 <at>  <at>  -209,9 +209,9  <at>  <at> 
 	reg.sel_event_mask = (gen_mips64_pe[e[j].event].pme_code >> (cntr*8)) & 0xff;
 	pc[j].reg_value   = reg.val;
 	pc[j].reg_addr    = cntr*2;
-  pc[j].reg_num     = cntr;
+        pc[j].reg_num     = cntr;

-	__pfm_vbprintf("[CP0_25_%u(pmc%u)=0x%"PRIx64" event_mask=0x%x usr=%d os=%d sup=%d exl=%d
int=1] %s\n",
+	__pfm_vbprintf("[CP0_25_%"PRIx64"(pmc%u)=0x%"PRIx64" event_mask=0x%x usr=%d os=%d sup=%d
exl=%d int=1] %s\n",
 			pc[j].reg_addr,
 			pc[j].reg_num,
 			pc[j].reg_value,

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stephane eranian | 7 Dec 2009 14:22

Re: [patch] a few more MIPS fixes

Vince,

Patches applied (separately).

On Sat, Dec 5, 2009 at 12:28 AM, Vince Weaver <vince <at> csl.cornell.edu> wrote:
> Hello
>
> here are a few more MIPS issues.  Sorry it is not broken out properly, but
> I defend my PhD next week so I am a bit busy.  Wantd to send this out
> before I forgot about it.
>
I assume your PhD is about performance analysis. I would certainly be
interested in reading about it. Good luck with your defense this week!

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