Question regarding privilege mode

I'm trying to change to privilege mode by twiddling the supervisor bit in the VHDL model.  When I run a test program in TSIM I see the bit change but then I hit a trap saying that when I try to run xgetpsr() I am trying to run a privilege mode command in user mode.  Aside from updating the bit in the VHDL is there anything else I need to do so that TSIM recognizes the mode change?


Posted by: aelbirt-/E1597aS9LQAvxtiuMwx3w@public.gmane.org


Booting Linux on the LEON3 - Console Port

I am currently booting linux on the LEON3 on the VC707 (single processor) using
the serial console port and the ethernet as my grmon interface.

Here is my console output....

PROMLIB: Sun Boot Prom Version 0 Revision 0
Linux versio� 3.10.58-00014-g82979ae (lophi <at> lophi-ws8) (gcc version 4.4.2 (sparc-linux-ct-leon_multilib_basic-0.0.7) ) #12 Tue Dec 16 14:41:37 EST 2014
bootconsole [earlyprom0] enabled
TYPE: Leon3 OF stdout device is: /a::a
PROM: Built device tree with 16992 bytes of memory.
Booting Linux...
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 259729
Kernel command line: console=ttyS0,38400 init=/sbin/init
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
�����-����e ���� ���le e������: 512
SC�� ����yst�� �nit�������
�sbco��: �������re� new inte����� ����er ���
�������: �egister�d ��� ������ ������ ���
��-�����: ������
����������: ������
N��: ���ist���� �������� fa�i�� 2
��� bind hash ���l� entrie�: 2048 (�����: 1, 8192 �����)
���: Regis����� ���tocol �����y 1
RPC: Registered named UNIX socket transport module.
RPC: Registe��� ��� �ranspor� �o��le.
RP�: Registered tcp trans���� ����le.
RP�: ���i������ ��� ����4.1 �������n�el tran����� �odule.
bounce pool si��: 64 pages
FS-�ac�e: ��t�s '���' ����stered for ca����g
N��: ���i��e���� th� ����eso���r k�y ����
����� ��� (�) 2007 ��� ���, �n�.
i� ������le� noop registered
io schedule� �������e registered
���0�7b8: ttyS0 �� ���� 0x80000100 (irq = 3) �� a G�LIB/A������
�rli�-��buart �t 0�80000100, irq 3
brd: module l�����
eh������: ��� 2.0 '��������' ���� ���������� (�H��) ������
����-pci: ���� ��I platf��� ������
��������: �S� Univ����� ���� ��ntr�ller Inte����� �riv��
�������: ���������� ��� ��t��fa�� dri��� u���������gen���c
usbs�����: ��� ������ �����rt ���������� ��� �������
�������: �egi���r�� new int������ ������ ftdi_���
����e����: ��� ����a� ��ppor� �������r�� ��� ��DI U�� �er��� ��v�ce
���c���: �������re� �e� �nter���e driv�� u�bh��
���: ����� �egi������
��� ���� ������������ ����������
������ng ���work...

I am assuming I have a baudrate mismatch once the kernel takes over, but what is the correct baud rate (my terminal is set to 38400).  I am curious if the kernel merely ignores the requested baudrate and defaults to something else....

Advice most welcome,

Posted by: brendon.chetwynd <at> ll.mit.edu




I'm trying to test my application on TSIM.

I start TSIM in GDB mode with the following command:
# 8 MB RAM in 4 banks
tsim-leon -freq 80 -ram 8000 -banks 4 -sdram 0 $1

Now I would like to change the IO values in 0x800000A0.
First I set a bit as output in 0x800000A4 and then try to write it to 1.

However I noticed that when I read these registers I read 0x0.
If I use the memory spy of Eclipse I can see that these two addresses have very different value from 0.

How can I properly use the IOs in TSIM?

Léonard Bise
Software Design Engineer
Direct Line +41 (0)32 338 9902

Neuenburgstrasse 7
CH-3238 Gals (Switzerland)
Desk Line +41 (0)32 338 9800

Posted by: Leonard Bise <leonard.bise-QJjcPyuumotyDzI6CaY1VQ@public.gmane.org>


[GRMON] AMBA plug&play not found !



I use Quartus 11.0 SP1 and grmon 2.0.60 eval version to make design for Cyclon II. When I use "grmon -altjtag" I get this error message : 


"AMBA plug&play not found !

Failed to initialize target!

Exiting GRMON".


Before that I used grmon 2.0.52 on an othet PC ant my designe worked fine.


Do you think grmon 2.0.60 is not compatible with Quartus 11 ?






Posted by: thierry.public1-/E1597aS9LQAvxtiuMwx3w@public.gmane.org


Trying to modify the PSR

So I have updated the iu3.vhd file to modify the status of the supervisor bit (r.w.s.s) which should percolate up to the PSR.  When I run a ModelSim simulation I see the r.w.s.s bit update but I can't find the top level instantiation of the PSR to check that the update made it all the way back.  Can someone point me to where that would be?  I tried to run the design in TSIM and it doesn't look like the PSR is being updated even though I am running the same instruction code that I ran when simulating the VHDL implementation with the testbench.



Posted by: aelbirt-/E1597aS9LQAvxtiuMwx3w@public.gmane.org


LEON3 Ethernet Debug on the VC707


I am attempting to perform debug on my LEON3 over Ethernet on my VC707.

I have read some of the articles regarding the GMII/MII issue and have applied the patch accordingly.

I am also able to connect to the debug control unit via the UART

I will note that the greth0 component is listed with the edcl IP listed as

I cannot connect and I am sure I have forced my link to 10/100 via a physical switch.

Thoughts would be most welcome,

Posted by: brendon.chetwynd-OVIABD91gjs3uPMLIKxrzw@public.gmane.org


Leon3-AltiumNanoboard Port Description


May I ask for the port description of the leon3-altium nanoboard design or if there already is a documentation of that design, may I ask for it as well? please?


Posted by: borces.mgmendiola-/E1597aS9LToLY4ysWL1ZA@public.gmane.org


modify Zedboard design to use Digilent Pmod

I have a Zedboard and I would like to build an SMP system based on 4 Leon3 processor, that will run a Linux distribution.
Since I am not able to use a USB-UART interface placed on the board (it is reserved for ARM processor), I am studying the mode to connect APBUART signals Rx and Tx to a Digilent PMOD connector.

The following steps have been performed:
1) change the leon3mp.vhd entity section:

entity leon3mp is
  generic (
    fabtech : integer := CFG_FABTECH;
    memtech : integer := CFG_MEMTECH;
    padtech : integer := CFG_PADTECH;
    clktech : integer := CFG_CLKTECH;
    disas   : integer := CFG_DISAS;   -- Enable disassembly to console
    dbguart : integer := CFG_DUART;   -- Print UART on console
    pclow   : integer := CFG_PCLOW;
    testahb : boolean := false
  port (
    processing_system7_0_MIO          : inout std_logic_vector(53 downto 0);
    processing_system7_0_PS_SRSTB     : inout std_logic;
    processing_system7_0_PS_CLK       : inout std_logic;
    processing_system7_0_PS_PORB      : inout std_logic;
    processing_system7_0_DDR_Clk      : inout std_logic;
    processing_system7_0_DDR_Clk_n    : inout std_logic;
    processing_system7_0_DDR_CKE      : inout std_logic;
    processing_system7_0_DDR_CS_n     : inout std_logic;
    processing_system7_0_DDR_RAS_n    : inout std_logic;
    processing_system7_0_DDR_CAS_n    : inout std_logic;
    processing_system7_0_DDR_WEB_pin  : inout std_logic;
    processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
    processing_system7_0_DDR_Addr     : inout std_logic_vector(14 downto 0);
    processing_system7_0_DDR_ODT      : inout std_logic;
    processing_system7_0_DDR_DRSTB    : inout std_logic;
    processing_system7_0_DDR_DQ       : inout std_logic_vector(31 downto 0);
    processing_system7_0_DDR_DM       : inout std_logic_vector(3 downto 0);
    processing_system7_0_DDR_DQS      : inout std_logic_vector(3 downto 0);
    processing_system7_0_DDR_DQS_n    : inout std_logic_vector(3 downto 0);
    processing_system7_0_DDR_VRN      : inout std_logic;
    processing_system7_0_DDR_VRP      : inout std_logic;
    button  : in    std_logic_vector(3 downto 0);
    switch  : inout std_logic_vector(7 downto 0);
    led     : out   std_logic_vector(7 downto 0);
    uart_tx: out std_logic; -- port for serial transmission purpose via PMOD
    uart_rx: in std_logic -- port for serial reception purpose via PMOD


2) change the leon3mp.vhd architecture section:

  ua1 : if CFG_UART1_ENABLE /= 0 generate
    uart1 : apbuart                     -- UART 1
      generic map (pindex   => 1, paddr => 1, pirq => 2, console => dbguart,
         fifosize => CFG_UART1_FIFO)
      port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
    u1i.rxd    <= rxd1; --ciò che viene ricevuto dalla uart andrà in rxd1
    u1i.ctsn   <= '0';
    u1i.extclk <= '0';
    txd1       <= u1o.txd;
    uart_tx <= u1o.txd; --assigned the output of apbuart to uart_tx (uart_tx will be connected to PMOD)
    rxd1 <=uart_rx ; --assigned the input for apbuart from uart_rx (uart_rx will be connected to PMOD)

  end generate;

3) change the leon3mp.xdc file:

################## interesting port of PMOD ###################################
set_property PACKAGE_PIN AA11 [get_ports {uart_tx}]
#NET JA2           LOC = AA11 | IOSTANDARD=LVCMOS33;  # "JA2"

set_property PACKAGE_PIN Y10 [get_ports {uart_rx}]
#NET JA3           LOC = Y10  | IOSTANDARD=LVCMOS33;  # "JA3"

4) change the digilent-zedboard-xc7z020.ucf file adding 2 constraints:

NET uart_rx        LOC = Y10  | IOSTANDARD=LVCMOS33;
NET uart_tx        LOC = AA11 | IOSTANDARD=LVCMOS33;

5) When I run "make vivado" script, I will obtain the following error:

Finished Running Vector-less Activity Propagation

report_power: Time (s): cpu = 00:00:35 ; elapsed = 00:00:35 . Memory (MB): peak = 1130.078 ; gain = 0.000

INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max, Constraints type: SDC.

Writing XDEF routing.

Writing XDEF routing logical nets.

Writing XDEF routing special nets.

Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1130.082 ; gain = 0.000

Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'

INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'

Running DRC as a precondition to command write_bitstream

ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 2 out of 152 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: uart_tx, uart_rx.

ERROR: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 2 out of 152 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: uart_tx, uart_rx.

INFO: [Vivado 12-3199] DRC finished with 2 Errors, 139 Warnings, 5 Advisories

INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.

ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.

INFO: [Common 17-83] Releasing license: Implementation

ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.

    while executing

"write_bitstream -force leon3mp.bit -mask_file"

Therefore I have two questions:
1) In your opinion, are the performed steps right?
2) in the file located in:

I have the following information (read from the column): IO Standard for Bank 13, where are connected the signals uart_rx and uart_tx, is LVCMOS18*. But from hardware user guide of the Zedboard, the right IO standard for Bank 13 should be LVCMOS33. This can be the problem?

Thank you very much,

Posted by: giacomo87v <at> yahoo.it


digilent plugin for grmon


I'm trying to use xilinx VC707 development board with grlib and grmon2. The installation of Digilent libraries seems to be OK (at least I'm able to program the dev. board using xilinx impact and digilent.adept.runtime-2.16.1:amd64).

I've unpacked the contents of digilent.adept.runtime_2.16.1_i386.deb to grmon-eval-2.0.59/linux/lib directory, added it to LD_LIBRARY_PATH, started grmon and got the following message

 $ LANG=C ./grmon -digilent

  GRMON2 LEON debug monitor v2.0.59 eval version
  Copyright (C) 2014 Aeroflex Gaisler - All rights reserved.
  For latest updates, go to http://www.gaisl er.com/
  Comments or bug-reports to support-FkzTOoA/JUlBDgjK7y7TUQ@public.gmane.org
  This eval version will expire on 14/05/2015

No cables found!
Exiting GRMON
*** Error in `./grmon': double free or corruption (out): 0xf5100468 ***

Please help me with this issue.


Posted by: dmitrodem-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org


GRMON wmem not working

Hello everyone,
It seems I'm not able to use the wmem command on grmon. I try writing to 
an address, and when I read it using the mem command, it hasn't changed.
I'm using grmon with -altjtag -u -nb options.

Thanks in advance.

Eduardo Ferreira Barbosa
Engenharia de Computação - Unicamp

Posted by: Eduardo <eduardo.f120@...>


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Building leon3-altium-nano3000 using Xilinx 13.2 in CentOS


I cloned https://github.com/jirgais/grlib-gpl/tree/nano3000 and followed the comands for the spartan 6 and got the following problems: 

[Marianne <at> localhost leon3-altium-nano3000-xilinx]$ make mig
make: *** No rule to make target `mig'.  Stop.
[Marianne <at> localhost leon3-altium-nano3000-xilinx]$ make
sparc-elf-gcc -I../../software/leon3  -ffast-math -O3 -c  ../../software/leon3/fpu.c
make: sparc-elf-gcc: Command not found
make: *** [fpu.o] Error 127


[ Marianne <at> localhost leon3-altium-nano3000-xilinx]$ ngdbuild -uc leon3mp
Release 13.2 - ngdbuild O.61xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
ERROR:Portability:90 - Command line error: Argument <design_name> must be

is there a user manual for altium nanoboard 3000?
Perhaps anyone have an idea?


Posted by: borces.mgmendiola-/E1597aS9LToLY4ysWL1ZA@public.gmane.org