please help Post Synthesis Simulation of Leon3


I'm trying for a long time to do gate-level simulation for Leon3 (sythesized using design compiler), but I
couldn't get proper result or simulation does not stop.

I need to know whether Leon has been verified for gate level
simulation? if yes , which tools and steps have been used for synthesis and simulation

I would really appreciate it if you give me info about this, cause I 'm
stuck in my work now.

Sorry if the question is repeated, but i could not find the solution.



Posted by: sajjadhussaintahiri-/E1597aS9LQAvxtiuMwx3w@public.gmane.org


APB Bus limited to 16 slaves?

I tried to connect more than 16 slaves to the APB bus and I noticed that apbctrl.vhd is hardcoding 16 as maximum number of slaves. In particular, the signal bnslave is encoded considering psel can only have 16 valid entries. Plug&Play info are also read for the first 16 devices only.

I changed that code and I was able to connect more devices. The memory area 0x800ff000 shows all pconfig entries and bare metal programs can address all devices.

When it comes to Linux, however, the openpromfs only shows devices with pindex < 16. Is that hardcoded in Linux too? I tried to find it, but I think I need a little help here.

I've already tried editing t he following macros with no success:

LEON3_APB_SLAVES 16 changed to 32 (macro is actually never used in the kernel)

PROMREG_MAX 16 changed to 32

PROMVADDR_MAX 16 changed to 32

OF_MAX_ADDR_CELLS 4 changed to 5

promlib_buf[128]  changed to promlib_buf[256]

I don't know if this information is useful, but I'm using kernel version 3.8

Thank you!

Posted by: paul8mnt-/E1597aS9LQAvxtiuMwx3w@public.gmane.org


power consumption of benchmark applications

Hi all,

does anyone know how to calculate power consumption of running benchmark applications on Leon3. Actually we are working on a research project and we aim to dynamically reconfigure hardware in terms of system frequency and cache lines, we are able to accomplish this but now we aim to analyze the implications of such reconfiguration on power consumption and execution time.

Most benchmarks report the execution time at the end of execution but what about power consumption. I found a standard formula relating frequency with power consumption b ut it requires other factors as well such as clock switching activity, load capacitance and supply voltage and I don't have this information. Moreover I also referred Xpower Analyzer but it gives me almost constant on-chip power consumption regardless of frequency and cache values.


Posted by: zohaibnajam-ur4TIblo6goN+BqQ9rBEUg@public.gmane.org


erc32 eCos compiler


I'm beginner developer about Sparc board. 

I want to compile erc32/eCos on LEON4, but I can't find this compiler.

In sparc-elf-gcc there's no compile option about erc32. So I try to find erc32 eCos compiler, but I failed.

So, I want to know how to get that compiler or way to use sparc-elf-gcc if exist...

Best regards.


Posted by: inputsh-/E1597aS9LQAvxtiuMwx3w@public.gmane.org


LEON3/FPGA on space

Hi all,

Are there LEON(2/3/4) as soft-core on FPGA in use on any space application (or planned to)?

I'm looking for references for my research and I could not find such information.

The only one I know is the EMFISIS:


Posted by: Paulo Villa <prcvilla-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>


Passing Data between LEON3 and Host FPGA


Apologies if this topic has previously been addressed. I couldn't find any discussion. 

I am looking to pass data between the host FPGA and the LEON3 processor resident on the same FPGA. Could anyone give me pointers on how I may go about doing so? Is there something along the lines of passing data between the PowerPC and Virtex4/5. Or the ARM processor and FPGA on the Zynq platforms. Any examples or demos would be much helpful. 


Posted by: rsraman-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org


Passing command line argument to a testbench on leon3


I am trying to run a testbench compress.c on leon3. It uses a command line argument "compress.txt". "compress.txt" is a file which stores the input to the program.
But I am not able to figure out how to pass compress.txt file when chip will run the executable. Please help

PS :
I have copied this testbench in systest.c and by using "make soft" which gives sram.srec.
Now for compilation I used
fuse -intstyle ise -incremental -o project/designs/leon3mp/testbench_isim_beh.exe -prj project/designs/leon3mp/testbench_beh.prj "work.testbench"
 ./testbench_isim_beh.exe -intstyle ise -tclbatch isim.cmd


Posted by: Neetu Jindal <jindalneetu28-/E1597aS9LQAvxtiuMwx3w@public.gmane.org>


Power Estimation using DC and PT PX

Hi everybody,

I m new to Leon2. I want detailed power estimation of Leon3. I am using leon3mp project. For simulation i have QuestaSim64 10.2.


1.synthesis using dc_shell

2.gate level simulation using Questa Sim and generation of VCD and then SAIF files

3.power estimation using PT PX

When I try this procedure with smaller designs, the results are OK. but with leon3mp I could not get

1. Gate Level Simulation propoerly

2. with Prime Time, the error message like Long Instance Name occurs and results in 0% annotation.

Please if anybody can help with gate level simulation in QuestaSim and what environmental settings is to be used in dc_shell while synthesizing.

best regards

Posted by: sajjadhussaintahiri-/E1597aS9LQAvxtiuMwx3w@public.gmane.org


Changing SDRAM Size

Hell all,

I am using Virtex6 ML 605 board. Is there a way to change the SDRAM size in "make xconfig"?
I should change it directly from the vhd file or there is no way at all?


Posted by: razi_seyyedi-/E1597aS9LQAvxtiuMwx3w@public.gmane.org


running mibench on leon2 with modelsim

please help me
I want to run rijndael, Susan, bitcnts programs on Leon2 with modelsim  (my platform is Ubuntu), then inject faults in to I Cache.
but this programs  read/write from/on file . that modelsim can not support them
if you have or  know person who has information about this work , can you introduce to me?
thanks for your attention

Posted by: ali anvari <alianvarissh-/E1597aS9LQAvxtiuMwx3w@public.gmane.org>


using chipscope

I would like to insert a chipscope in the leon3 design. When I use the inserter it looks for leon3mp netlist. I am currently using "make planahead" command as per the readme.txt to generate the bit file.

To add chipscope inserter in the project, what is the procedure. I cudnt find the netlist to add the signals.

Also once the signals are selected in the chiscope inserter, what are the changes needs to be done to include chipscope for the final build.

Posted by: anuyarlagadda-/E1597aS9LQxFYw1CcD5bw@public.gmane.org