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ZC702 grmon connection problem [1 Attachment]



Hello, I'm Taekyung Heo.

I have a problem with establishing a connection to Leon3.

If there is anyone who has a solution, please help me.


Problem

I can't establish a connection to Leon3 using grmon.


Experiment Environment

1) OS: Ubuntu 64bit 14.04.2 Desktop

2) FPGA Board: ZedBoard (ZC702)

3) Cables:

    I have two cables. (Please see the attached file)

    - One is the original one from ZedBoard (ZedBoard cable)

    - The other is from Virtex5. (Virtex5 JTAG cable)

4) Other Conditions

  - If I boot up the device with the default sdcard which has a linux image,  span>I can see messages.

  - I can see /dev/ttyACM0


Error Messages

1) Using ZedBoard Cable


$sudo ./grmon -xilusb


  GRMON2 LEON debug monitor v2.0.65 32-bit eval version

  

  Copyright (C) 2015 Cobham Gaisler - All rights reserved.

  For latest updates, go to http://www.gaisler.com/

  Comments or bug-reports to support-FkzTOoA/JUlBDgjK7y7TUQ@public.gmane.org

  

  This eval version will expire on 10/12/2015


No cables found!

Exiting GRMON


$sudo ./grmon -xilusb -uart /dev/ttyACM0


  GRMON2 LEON debug monitor v 2.0.65 32-bit eval version

  

  Copyright (C) 2015 Cobham Gaisler - All rights reserved.

  For latest updates, go to http://www.gaisler.com/

  Comments or bug-reports to support-FkzTOoA/JUlBDgjK7y7TUQ@public.gmane.org

  

  This eval version will expire on 10/12/2015


  using port /dev/ttyACM0 <at> 115200 baud

..........

UART failed to connect

Exiting GRMON


$sudo ./grmon -digilent


  GRMON2 LEON debug monitor v2.0.65 32-bit eval version

  

  Copyright (C) 2015 Cobham Gaisler - All rights reserved.

  For latest updates, go to http://www.gaisler.com/

  Comments or bug-reports to support-FkzTOoA/JUlBDgjK7y7TUQ@public.gmane.org

 &nbsp ;

  This eval version will expire on 10/12/2015


No cables found!

Exiting GRMON


$sudo ./grmon -digilent -uart /dev/ttyACM0


  GRMON2 LEON debug monitor v2.0.65 32-bit eval version

  

  Copyright (C) 2015 Cobham Gaisler - All rights reserved.

  For latest updates, go to http://www.gaisler.com/

  Comments or bug-reports to support-FkzTOoA/JUlBDgjK7y7TUQ@public.gmane.org

  

  This eval version will expire on 10/12/2015


  using port /dev/ttyACM0 <at> 115200 baud

..........

UART failed to connect

Exiting GRMON



2) Using Virtex5 Cable

$sudo ./grmon -xilusb   


  GRMON2 LEON debug monitor v2.0.65 32-bit eval version

  

  Copyright (C) 2015 Cobham Gaisler - All rights reserved.

  For latest updates, go to http://www.gaisler.com/

  Comments or bug-reports to support-FkzTOoA/JUlBDgjK7y7TUQ@public.gmane.org

  

  This eval version will expire on 10/12/2015


Xilusb: Cable type/rev : 0x3 

JTAG Instruction register length detection failed

Exiting GRMON


$sudo ./grmon -digilent


  GRMON2 LEON debug monitor v2.0.65 32-bit eval version

  

  Copyright (C) 2015 Cobham Gaisler - All rights reserved.

  For latest updates, go to http://www.gaisler.com/

  Comments or bug-reports to support-FkzTOoA/JUlBDgjK7y7TUQ@public.gmane.org

  

  This eval version will expire on 10/12/2015


No cables found!

Exiting GRMON



If you have any solution, please help me.


Thank you.

Taekyung Heo



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Posted by: gumdaeng-/E1597aS9LQAvxtiuMwx3w@public.gmane.org



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GRMON2 compatibility with GR-PCI-XC5V board




​Hello everybody, i am trying to connect a board GR-PCI-XC5V with grmon2 (eval version) downloaded from the aeroflex site. In the past I used the old version of grmon(currently it is not available the eval version)
​I have tried to connect the board with the option -eth and -jtag, in both cases with the ethernet and jtag cables correctly connected.​

​$>grmon -eth 192.168.2.15
The application returns a Segmentation fault ​

$>grmon -jtag
No cables found!
Exiting GRMON​

​Te first question is. Anyone knows if the board GR-PCI-XC5V is compatible with grmon2?


​Regards and thanks in advance,
Pedro.​



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Posted by: "pedro.palomo" <pedro.palomo <at> deimos-space.com>



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passing key strokes via grmon to snapgear



Hi all,

I loaded a snapgear os into leon3 4-core processor onto a altera cycloneiv-based terasic de2-115 board.
Cross-compiled programs run well on leon3 without any problem.
The only thing annoys me is that how the key strokes can be pass into snapgear via grmon. For example, how can I exit a running program on leon3? Ctrl-c can only let me jump out of the snapgear OS and go back to "grmon2>". The keystrokes are not able to be passed into the snapgear OS whenever it is not waiting for command line input.
Do I need to reconfigure the snapgear or leon3? Or do I need a usb/ps keyboard that is directly connected to the fpga board?


regards,

ys



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Posted by: sunyujia-ur4TIblo6goN+BqQ9rBEUg@public.gmane.org



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FPU implementation prob in Xilinx

Dear All, 
I am trying to implement LEON3 core with an FPU in virtex4lx60 board (example design) by modifying the config.vhd.
However in Xilinx ise 13.2 i get following error.....

NgdBuild:604 - logical block 
'leon3gen.cpu[0].nosh.u0/leon3x0/nofpshare.grfpw1gen.fpu0/x1.grfpw0/uni.grfpw 
0' with type 'grfpw_0_unisim' could not be resolved. A pin name misspelling 
can cause this, a missing edif or ngc file, case mismatch between the block 
name and the edif or ngc file name, or the misspelling of a type name. Symbol 
'grfpw_0_unisim' is not supported in target 'virtex4'.

i tried to loacte 'grfpw_0_unisim' source in lib directory , but no success. \
Please suggest the cause and some redmedy for this..

Thanks in Advance...

Pramod

------------------------------------
Posted by: Pramod Mishra <pramod.mishra2210@...>
------------------------------------

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Supervisor mode while running linux




I need to go into supervisor mode while running linux in order to run ASI load/store instructions. However I got same "illegal instruction" error when tried to write to the S bit of PSR register (Note: I am trying writing 0xf4, 0xe4 (8 LSBs) in order to modify 7th bit of PSR, could not try writing all 32 bit bcz it give relocation overflow error). I am doing Something like this: 
asm("wr %g1, 0xe4, %psr;"); asm("nop"); asm(" nop"); asm("nop");
It give me same error when tried to read PSR like this:
__asm__ __volatile__("rd %%psr,%0\n\t":"=r" (ps) : );

I am using latest grlib version (1.4.1) with ml509. Am I doing something wrong or reading/writing to psr is also not allowed in linux?
Please provide me some hint about how i can get into supervisor mode while running linux to run privileged i nstructions?




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Posted by: darnajam72-/E1597aS9LQAvxtiuMwx3w@public.gmane.org



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16bits SDRAM controller

Hi,

I'm working on porting the leon3 on the low cost miniSpartan6+ from
Scarab Hardware on which they use a 16 bits SDRAM AS4C16M16S. from what
I found on the net and the GRIP documentation there is no 16bits SDRAM
memory controller, the only one isn't available.

So my question is, does anyone have one to share :)?

Best regards,
-- 

Alexis Jeandet, 
Plasma Physics Laboratory

------------------------------------
Posted by: jeandet alexis <alexis.jeandet@...>
------------------------------------

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<*> Your email settings:
    Individual Email | Traditional

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    http://groups.yahoo.com/group/LEON_SPARC/join
    (Yahoo! ID required)

<*> To change settings via email:
    LEON_SPARC-digest@... 
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grmon: "Failed to open hub" error



Hi everyone,

I have successfully programmed the Leon3 4-core processor into Altera Cyclone IV EP4CE115F29 on a terasic de2-115 FPGA board via usb-blaster cable. However, after I typed in grmon command:

grmon -u -nb -altjtag -jtagdevice 1

it showed a error message like this

==========

GRMON2 LEON debug monitor v2.0.65 32-bit eval version
 
  Copyright (C) 2015 Cobham Gaisler - All rights reserved.
  For latest updates, go to http://www.gaisler.com/
  Comments or bug-reports to support-FkzTOoA/JUlBDgjK7y7TUQ@public.gmane.org
 
  This eval version will expire on 10/12/2015

 JTAG chain (1): EP3C120/EP4CE115
Failed to open hub (8): cable USB-Blaster [2-2.2], device <at> 1: EP3C120/EP4CE115 (0x020F70DD)
Exiting GRMON

==========

I searched "Failed to open hub", and no one seems to have encountered the same problem as I do. Since Leon3 has been successfully programmed in the FPGA, the usb-blaster should be working. I wonder how I can solve this.
Thanks a lot.




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Posted by: sunyujia-ur4TIblo6goN+BqQ9rBEUg@public.gmane.org



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Understand the difference about the -qnoambapp flag



Hello,
I am opening this thread because I would understand better the difference between the use of -qambapp flag and -qnoambapp flag.
There was a change during various releases of BCC. Now I am using BCC 1.0.45.
My question is: if I have a custom peripheral connected to AMBA APB bus, instantiating it on the address area from 0x80000D00 to 0x80000E00, and I want to simulate it, why the simulation has the following behaviour:
        - if I build the standalone source file test.c where I am testing the custom peripheral:
                sparc-elf-gcc -O 0 test.c -qnoambapp -o test.exe
        writes and reads on APB bus connected to my peripheral work good.
        -If I build the same application with:
               
sparc-elf-gcc -O0 test.c -o test.exe
      
writes and reads on APB bus connected to my peripheral don't work good.
Reporting the Changelog of BCC:
--------- BCC 1.0.45 ----------- 2014-03-10 FPStore errata workaround implemented, enabled by default using the mtune=ut699 flag or -mfpstore-errata. 2014-03-03 -mtune=socc3 removed (same at ut699) --------- BCC 1.0.44 ----------- 2013-09-12 -mtune=[ut699,socc3] improve nop insertion after [ld,st] sequence, backport 4.9 data-nullify errata fix. Add switch -fnullify-allnop to reactivate old fix with nop insertion at every [ld,st] sequence --------- BCC 1.0.43 ----------- 2013-06-11 add trap handler install routine traptable_genjmp() 2013-06-3 -mtune=[ut699,socc3] fix for nop insertion after [ld,st] sequence (data-nullify errata) --------- BCC 1.0.42 ----------- 2012-11-27 Declare jiffies volatile --------- BCC 1.0.41 ----------- 2012-08-13 Change -qambapp to -qnoambapp to enables scanning across AHB2AHB bridges by default

It explains that, from BCC 1.0.41, with -qnoambapp I am enabling the scan across AHB2AHB bridges. Is this the solution of the problem? Does it mean that, if I don't use -qnoambapp flag, scanning among AHB2AHB is disabled? If yes, in my case I have an AHB2APB bridge: this should not be a problem.

Thank you for any help.
Giacomo





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Posted by: giacomo87v-whZMOeQn8C0@public.gmane.org



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Error while running gtl-vsim-launch



Hi,

I am trying to simulate a synthesized netlist of the leon3 asic design using ModelSim. As described in the Makefile, I executed the command make gtl-vsim-launch and got the following error message: t>

** Error: (vcom-11) Could not find unisim.ramb16_s36_s36.
###### ../../lib/techmap/unisim/memory_unisim.vhd(36): use unisim.RAMB16_S36_S36;

I thought  the Makefile uses the files and directories defined in the text file vhdlsim.txt.  But in the unisim directory this files doesn't contain the definition for memory_unisim.vhd

Could you please help me?

Thanks & Kind Regards,
Patrick


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Posted by: Patrick Schmale <patrick.schmale-/E1597aS9LQAvxtiuMwx3w@public.gmane.org>



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Cant access uart data registers directly?



hi!
I have tried to write a simple application for accessing uart referring to the bcc src codes available and run it on TSIM, it had executed without any errors but when I am looking into uart data register i.e. 0x80000900 its not showing anything. Is this method of accessing the uart registers directly is not correct?
#include <st dio.h>
#include <stdlib.h>

//#define     EVEN        0
//#define        ODD        1

/*UART CONTROL BITS*/
#define     TX_EN        0x00000001
#define     RX_EN        0x00000002
#define     RX_INT_EN    2
#define     TX_INT_EN    3
#define     PARITY_SL    4
#define     PARITY_EN    5
#define     LO OP_BK        0x00000080
#define     FLOW_CTRL_EN    6
#define     TX_FIFO        9
#define     RX_FIFO        10

/*UART STATUS BITS*/
#define     DATA_RD        0x00000001
//#define     TX_SF        1
#define     TX_FIFO_EMPTY    0x00000004
/*#define     BRK_RX        3
#define     OV_LOST        4
#defi ne     PARITY_ER    5
#define     FR_ER        6
#define     TX_HALF        7
#define     RX_HALF        8
#define     TX_FIFO_FULL    9
#define     RX_FIFO_FULL    10*/
#define     UART1_ERR    0x00000078   

void uart1_send_data(char data);
char uart1_recev_data(void);

struct uart_regs
{
 volatile int data;
volatile int status;
volatile int ctrl;
volatile int scaler;
};
struct uart_regs *uart = (struct uart_regs*)0x80000900;

int main()
{
    char buff;   
    uart->ctrl=0;
    uart->status=0;
    uart->scaler=0;
    uart->ctrl|= (TX_EN | RX_EN | LOOP_BK);
    uart->scaler=86;
    printf("\nUART1initialized");// in loop back mode to test...");
    uart1_send_data('S');
    buff=uart1_recev_data();
    printf("\nRd",buff);
    r eturn(1);
}   
void uart1_send_data(char user_data)
{
   
    uart->data=(unsigned int)user_data;
    while((uart->status &  TX_FIFO_EMPTY) == 0);
    printf("\nDS\n");   
}         
char uart1_recev_data(void)
{
    if(uart->status & UART1_ERR)
        uart->status= ~UART1_ERR;
    if((uart->status & DATA_RD)!=0)
    return(unsigned int)uart->data;     &nbsp ; 

}   
 
---Sameer Huddar



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Posted by: Sameer Huddar <sam_huddar-/E1597aS9LQxFYw1CcD5bw@public.gmane.org>



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Regarding desgning peripheral libraries



hi

I am trying get to design peripheral library referring to GRIP document for sparcv8 leon3 core processor. The tool chain being used is sparc-elf-gcc executing over TSIM (professional version). Till now, I have tried to develop program for accessing APBUART register addresses through memory mapping but could not get it to work properly. Could anyone please assist me on the same regarding what should be my approach to design my own peripheral library?

Thanks and regards,

-Sameer






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Posted by: Sameer Huddar <sam_huddar-/E1597aS9LQxFYw1CcD5bw@public.gmane.org>



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