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[GRMON - MODELSIM] unrecognized option '-qnoambapp'




Hello,

 

I can't compil a new soft for Modelsim.

 

I set the environement variable LDFLAGS=-qnoambaapp

and I use 'make soft' commant.

 

I get the error : sparc-elf-gcc error : unrecognized option '-qnoambaapp'

 

I use sparc-elf-4.6.0.

 

What is my pb ?

best regards

Thierry

 



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Posted by: thierry.public1-/E1597aS9LQAvxtiuMwx3w@public.gmane.org



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SPI on Kintex-7



Hi guys, 

i would like to add a pinout for SPI to Kintex-7 (i saw that its definitions are missing in xilinx-kc705-xc7k325t.xdc file). 


My question is: can i copy those pinouts from the xilinx-vc707-xc7vx485t.xdc which is roughly the same board (the section under the "SPI" comment). 



Thank you, 

Alex. 



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Posted by: ziksable-/E1597aS9LQAvxtiuMwx3w@public.gmane.org



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Adding additional UART to the Leon3 design on Kintex 7



Hi guys, 

I would like to get help on how to add additional UART to the Leon3 design. 


I understand that in order to do it i need to modify two files, the: leon3mp.vhd and the xilinx-kc705-xc7k325t.xdc file. 


in the  leon3mp.vhd i need to add to the block starting with: 

ua1 : if CFG_UART1_ENABLE /= 0 generate

    uart1 : apbuart                     -- UART 1


another instance of uart. 


and in the xilinx-kc705-xc7k325t.xdc i need to add the pin-out mapping. 


Am i right ? 

Could you advise on how to update those files ? i have tried to copy the block again, but i have trouble with the signal assign, addressees and etc.. 


Thanks, 

Alex. 

    

 



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Posted by: ziksable-/E1597aS9LQAvxtiuMwx3w@public.gmane.org



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UCF file is missing from design VC707



Hello


I could not find the leon3mp.ucf file for vc707 design. I checked the other designs this file was present there but was missing from vc707 desgin


This problem is found in GRLIB version 1.3.7 and 1.2.2


Anyone???



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Posted by: zohaibnajam-ur4TIblo6goN+BqQ9rBEUg@public.gmane.org



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[MODELSIM] AHB slave index error after add e new core




Hi,

 

I try to add a new personal core on global designe but I have a problem.
I did next operations :

 

1] I add new vendor on devices.vhd :
 constant VENDOR_THIERRY1   : amba_vendor_type := 16#EB#;

 

2] I add new core name on devices.vhd :
 constant THIERRY_LEDCTRL       : amba_device_type := 16#098#;

 

3] I specify directory names of my lib on libs.txt, dirs.txt and vhdlsyn.txt


4] I creat my slave IP to plug on AHB bus like this :

 

* lib :

 

 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all, ieee.std_logic_unsigned.all;
 library grlib;
 use grlib.amba.all;
 use grlib.devices.all;
 use grlib.stdlib.all;

 

*entity :

 

 entity ahb_led is
   generic (
      hindex1  : integer := 0;
      paddr : integer := 0;
      hmask : integer := 16#fff# );
   port (
      ahbledRst   : in  std_ulogic;
     ahbledClk  : in  std_ulogic;
      ahbledBus_V15Out:out  std_logic_vector (15 downto 0);
      ahbledTest_V15Out:out std_logic_vector (15 downto 0);
      ahbledAhb_In    : in  ahb_slv_in_type;
      ahbledAh_ Out    : out ahb_slv_out_type );
 end;


*Plug and play config :

 

 architecture rtl of ahb_led is

 

constant HCONFIG: ahb_config_type := (
0=>ahb_device_reg (VENDOR_THIERRY1, THIERRY_LEDCTRL,0,0,0),
4 => ahb_membar(paddr, '0', '0', hmask),
others => X"00000000"); -- plug and play config


5] after add my personal .vhd file on project I make an instance of my IP on leon3mp.vhd like this :

 

*declaration :


 component ahb_led is
  generic (
      hindex1  : integer ;
      paddr : integer ;
      hmask : integer );
   port (
      ahbledRst    : in  std_ulogic;
      ahbledClk     : in  std_ulogic;
      ahbledBus_V15Out:out  std_logic_vector (15 downto 0);
      ahbledTest_V15Out:out std_logic_vector (15 downto 0);
      ahbledAhb_In    : in  ahb_slv_in_type;
      ahbledAh _Out    : out ahb_slv_out_type );
 end component;


* add nbslave :

 

 ------------------------------------------------
 ---  AHB CONTROLLER ------------------------------
 -----------------------------------------------------

ahb0 : ahbctrl   -- AHB arbiter/multiplexer


generic map (defmast => CFG_DEFMST, split => CFG_SPLIT, 
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, ioen => IOAEN,
nahbm => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
devid => ALTERA_DE2, nahbs => 9) -- <=== origin : nahbs => 8

 

port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);


* instance :

 

 led0 : ahb_led
 generic map (
   hindex1  => 8,
   paddr   => 16#A00#,
   hmask    => 16#FFF#)
 port map (
   ahbledRst     => rstn,
   ahbledClk      => clkm,
   ahbledBus_V15Out    => compteurLED1xDO,
   ahbledTest_V15Out => compteurTestVector1xDO,
   ahbledAhb_In    => ahbsi,
   ahbledAh_Out    => ahbso(8) );

 

 

6] The compilation with quartus and modelsim are good.

 

But when I launch the simu with 'make vsim-launch' I have this echo on modelsim terminal (my IP is slv8) :


run -a
# ** Note: Cyclone II PLL is enabled
#    Time: 0 ps  Iteration: 2  Instance: /testbench/d3/clkgen0/sden/altpll0/CYCLONEII_ALTPLL/M3
# LEON3 Altera DE2-EP2C35 Demonstration design
# GRLIB Version 1.3.4, build 4140
# Target technology: altera    , memory library: inferred 
# ahbctrl: AHB arbiter/multiplexer rev 1
# ahbctrl: Common I/O area at 0xfff00000, 1 Mbyte
# ahbctrl: AHB masters: 4, AHB slaves: 9
# ahbctrl: Configuration area at 0xfffff000, 4 kbyte
# ahbctrl: mst0: Aeroflex Gaisler        LEON3 SPARC V8 Processor      
# ahbctrl: mst1: Aeroflex Gaisler        AHB Debug UART   &nb sp;            
# ahbctrl: mst2: Aeroflex Gaisler        JTAG Debug Link               
# ahbctrl: mst3: Aeroflex Gaisler        SVGA frame buffer             
# ahbctrl: slv0: European Space Agency   LEON2 Memory Controller       
# ahbctrl:       memory at 0x00000000, size 512 Mbyte, cacheable, prefetch
# ahbctrl: slv1: Aeroflex Gaisler        AHB/APB Bridge      & nbsp;         
# ahbctrl:       memory at 0x80000000, size 1 Mbyte
# ahbctrl: slv2: Aeroflex Gaisler        LEON3 Debug Support Unit      
# ahbctrl:       memory at 0x90000000, size 256 Mbyte
# ahbctrl: slv3: Aeroflex Gaisler        PC133 SDRAM Controller        
# ahbctrl:       memory at 0x40000000, size 8 Mbyte, cacheable, prefetch
# ahbctrl:       I/O port at 0xfff00100, size 256 byte
# ahbctrl: slv7: Aeroflex Gaisler        Test report module            
# ahbctrl:       memory at 0x20000000, size 1 Mbyte
# ahbctrl: slv8: Unknown vendor          Unknown Device                
# ahbctrl:       memory at 0xa0000000, size 1 Mbyte
# ** Failure: AHB slave index error on slave 8. Detected index value 0
#    Time: 2 ns  Iteration: 0  Process: /testbench/d3/ahb0/diag File: ../../lib/grlib/amba/ahbctrl.vhd
# Break in ForLoop loop at ../../lib/grlib/amba/ahbctrl.vhd line 960


This error corresponding to the next line on ahbctrl.vhd :

 

assert (slvo(i).hindex = i) or (icheck = 0)
        report "AHB slave index error on slave " & tost(i) &
L960=>          ". Detected index value " & tost(slvo(i).hindex) severity failure;
        if mcheck /= 0 then
          for j in 0 to i loop
            for k in memmap(i)'range loop
              if memmap(i)(k).stop /= zero32(memmap(i)(k).stop'range) then
                 for l in memmap(j)'range loop
                  assert ((memmap(i)(k).start >= memmap(j)(l).stop) or
                          (memmap(i)(k).stop <= memmap(j)(l).start) or
                          (mcheck /= 2 and (memmap(i)(k).io xor memmap(j)(l).io) = '1') or
                       & nbsp;  (i = j and k = l))
                    report "AHB slave " & tost(i) & " bank " & tost(k) &
                    " intersects with AHB slave " & tost(j) & " bank " & tost(l)
                    severity failure;
                end loop;
              end if;
  &nbs p;         end loop;
          end loop;

 

My questions :

 

Where can I modify leon3mp.vhd to add correctly my IP ?

 

Why have I an Unknown vendor  and Unknown Device on my IP (slv8) ?

 

Best regards
Thierry

 

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Posted by: thierry.public1-/E1597aS9LQAvxtiuMwx3w@public.gmane.org



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Data Cache Write



Hi,


For data cache write, do we have a tag access read before each write?

Based on the cache controller's state machine, there is a data tag read state. But when I run a benchmark and check the signals, this happens rarely and doesn't happen for data cache writes!

Is there a special write mode that has a sequential access to tag and data in consecutive cycles?


Thanks,

Abbas



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Posted by: abbasb58-/E1597aS9LQAvxtiuMwx3w@public.gmane.org



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GRMON2 LEON eval version "Unknown JTAG device id" problem



Hi guys, 

I'm trying to connect to Leon3 through FTDI JTAG using the grmon2 evaluation version (on win7 32bit). And i get the unknown jtag device error. Is it something related to the "eval-version" ? I have all the divers installed.   


C:\grmon-eval-2.0.55r2\win32\bin>grmon.exe -d2xx


GRMON2 LEON debug monitor v2.0.55r2 eval version


  Copyright (C) 2014 Aeroflex Gaisler - All rights reserved.

  For latest updates, go to http://www.gaisler.com/

  Comments or bug-reports to support-FkzTOoA/JUlBDgjK7y7TUQ@public.gmane.org


  This eval version will expire on 28/01/2015


 Unknown JTAG device id = 00712649

 JTAG chain (1):

 JTAG De bug Interface not found.

Exiting GRMON


Thank you, 

Alex



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Posted by: ziksable-/E1597aS9LQAvxtiuMwx3w@public.gmane.org



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Change data cache controller



Hi,

I‌ want to change the data cache controller to modify the write operation. I‌ want to do a read-before-write for each write to data cache. Is it possible to add this extra read before each write to data cache?


Any help would be appreciated.

Thanks,

Abbas 



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Posted by: abbasb58 <at> yahoo.com



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TSIM for Leon3ft



can any one provide me the link for downloading the free version of TSIM simulator for leon 3ft??




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Posted by: khanaqsa915-/E1597aS9LQAvxtiuMwx3w@public.gmane.org



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TSIM simulator



can any one provide me the link for downloading the free version of TSIM simulator for leon 3ft??




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Posted by: khanaqsa915-/E1597aS9LQAvxtiuMwx3w@public.gmane.org



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Σχετ: Linux on a ML605 board



Hi Rechard,

Have you tried to use Snapgear Linux 2.6 for Leon ?
You can find it here: Snapgear Linux

There is a guide online that shows you the steps in order to prepare the distribution according to your needs in this blog: Snapgear Preparation - www.rte.se blog

I have followed the same steps and it worked fine for me on an ml505 board.

I hope I helped you.


Στις 11:04 π.μ. Δευτέρα, 18 Αυγούστου 2014, ο/η "richard.bruchthal-/E1597aS9LQAvxtiuMwx3w@public.gmane.org [LEON_SPARC]" <LEON_SPARC-hHKSG33TihhbjbujkaE4pw@public.gmane.org> έγραψε:


 
Hello,I want to run a Leon3-SoC with Linux on a Xilinx ML605 board. To be sure that I don't mess up the settings I downloaded the ML605 bit file (in "FPGA bit files for GRLIB template designs") from the following link: http://www.gaisler.com/index.php/downloads/leongrlib?task=view&id=156You can see the “info sys” in the attachments.
Afterwards I set up the lunixbuild toolchain as decribed in linuxbuild-1.0.7.pdf. Then I started the configuration GUI and built a ram image with the default settings.
After loading the bit file with Xilinx Impact and the ram image with GRMON the Linux started to boot. Unfortunately the booting always gets stuck. You can see the status messages in the attachments as well.I assume the problem is the unknown signal state of CPU2. This status pops up at different locations/CPUs at different runs. Any idea where my mistake is? As mentioned earlier I'm only using the provided bit file from Gaisler and the default settings to build the Linux ram image. Is there another way to get a bit file and a ram image to just get the system just run for the start?
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