timothy.canham | 21 Apr 21:47 2014
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UT699 Memory Controller



Studying the UT699 Leon 3FT/SPARC Functional Manual, dated February 2014. 

In 3.10, when using 8-bit mode, the manual states "If the memory is configured in 8-bit mode, the EDAC checkbit bus (CB[7:0]) is not used, but it is still possible to use EDAC protection. This is done by allocating the top 20% of the memory bank to the EDAC checksums."

We plan on using a 8MB ROM, and we need an exact number for the starting address of the EDAC checksums. I just used 8MB*0.8, but that gives me a fractional remainder, so I don't know if there are any rounding adjustments or anything. Can you tell me the EDAC address f or an 8MB ROM?


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mehmed.murat | 21 Apr 16:47 2014
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sending and receiving a small .bmp file on grmon



hi,
I'm using atlys board and ethernet cable to debug. I am trying to send a small bmp file to leon, then after some basic changes on the image i wanna receive the file back. I dont know how can i do that.
Could you please help me out.

Best regards,
Murat.


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pd.aneesh | 20 Apr 21:51 2014
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HOW to pass context number information to cache through sparc v8 processor



I have got a small query related to implementation of cache with sparc v8 processor..  Iam implementing VIVT cache with processor model.. Previously I thought sparc processor have some register to keep process ID information, which will be passed to caches, along with virtual address, for extended cache tags. But I didnt find any material which proves my concept. Also no such register is mentioned in sparc v8 manual.

Can you please hint me the standard method of keeping/propagating context information by sparc v8 processor?

Regards
Aneesh

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alhawaj | 18 Apr 19:58 2014
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Changing LEON3's frequency on VC707



Hi everyone,

I am trying to change the frequency of the LEON3 core on the VC707 board. However, I cannot seem to do so. Whenever I change the multiplier and divider, the period of 10ns won't change. MIG is enabled, so clock is generated by the MIG; it seems that CFG_CLKMUL and CFG_CLKDIV are not to be found when initializing and defining MIG.

Is it possible to change the clock period for my design to meet the timing constraints?

Thanks,
Khalid


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timothy.canham | 17 Apr 23:28 2014
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UT699/Sparc V8 CRC instruction?



I have to compute a 7-bit CRC value from a 32-bit word. Does the Sparc V8 have an instruction to do that?

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Jan Andersson | 16 Apr 17:12 2014

grlib-gpl-1.3.7-b4144 released

Hello,

GRLIB GPL 1.3.7-b4144 is now available from:

http://www.gaisler.com/products/grlib/grlib-gpl-1.3.7-b4144.tar.gz

Changelog is here:

http://www.gaisler.com/products/grlib/Changelog.txt

These files and the bitfiles and netlist packages can be downloaded via:

http://www.gaisler.com/index.php/downloads/leongrlib

Changelog since last GPL release is included below at [1]. Please note
that you may need to upgrade your BCC toolchain in case your current one
does not support the -qnoambapp flag. This flag is not added by default
for "make soft".

Best regards,
  Jan

[1]:

----------------------- Release 1.3.7-b4144 ----------------------------

2014-04-16	Change default assignment of GRLIB_SIMULATOR to ModelSim

2014-04-15	DDR3RAM sim model: Improve memory usage

2014-04-11	RGMII: First revision of documentation for the RGMII IP

2014-04-11	SAED32-TECHMAP: Fixed Bidir mapping and corrected erroneous
		instantiation of technology memory.

2014-04-11	LEON3-ASIC: Fixed simulation for SAED32 technology library
		and modified design to work with base_test and greth_test
		in systest

2014-04-10	Xilinx techmap: Assign SIM_COLLISION_CHECK generic in techmap
		layer instead of patching UNSIM sources.

2014-04-10	Disable install-unisim and install-secureip targets when
		GRLIB_SIMULATOR is set to Xilinx.

2014-04-10	Updated PlanAhead script generation to allow ISim simulation

2014-04-08	Updated the leon3-digilent-xc7z020 design to working condition

2014-04-04	10/100Mbit mode fix for RGMII and SGMII on Xilinx designs
		- Fixed 10/100Mbit mode in RGMII for ref designs KC705,
		  AC701 and GR-XC6
		- Fixed 10/100Mbit mode in SGMII for ref designs VC707

2013-04-04	PlanAhead flow updated to improve overall timing

2013-04-04	GRETH/GRETH_GBIT updated to support unchanged clock speed for
		lower bit rates

2013-03-25	Remove lib/openchip

2013-03-25	Add template design for Xilinx AC701 board (leon3-xilinx-ac701)

2013-03-21	Set Unisim pad delays to zero to match ISE simulation model
		behavior.

2013-03-18	GPTIMER/GRTIMER: Merge GRTIMER functionality into GPTIMER.

2014-03-06	DSU3: Add dsu3_mb to allow AHB trace of second AHB bus

2014-03-05	LEON3v3: Rearranged and updated IP core documentation.

2014-03-05	LEON3v3: Removed fast snooping option from xconfig menus,
		default to always on.

2014-03-05	LEON3v3: Added safeguard to generate error in simulation if FT
		features are accidentally enabled on non-FT version of LEON3.

2014-03-01	LEON3v3: Improve performance for d-cache in frozen state by
		only fetching missing data instead of full d-cache line.

2014-02-17	GPTIMER: Add WDOGDIS and WDOGNMI fields, see GRIP for details.

2014-02-16	systest: Add -qnoambapp option if LDFLAGS variable is
		undefined. If -qnoambapp leads to errors then these can be
		fixed by defining LDFLAGS or installing a recent BCC version.

2014-02-09	MUL32/DIV32: Add support for grlib_async_reset_enable.

2014-01-18	Update documentation to warn for use of -use_new_parser yes
		with Xilinx XST.

2014-01-13	Remove planAhead make target, use only planahead.

2014-01-03	Added generic DDR1, DDR2, DDR3 SDRAM simulation models
		under lib/gaisler/sim.vhd. Updated most template designs
		to use new models.

------------------------------------

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leonard.bise | 10 Apr 16:40 2014
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Simple hello world not printfing anything in tsim-leon



Hello,
I'm running on Ubuntu 12.04 LTS.
I have a very simple hello world program:
#include <stdio.h>

int main(void)
{
  printf("Hello world!\n");
  return 0;
}

I compile this code with sparc-elf-gcc -g hello.c -o hello.exe
sparc-elf-gcc is latest from the website :
sparc-elf-gcc (BCC 4.4.2 release 1.0.44) 4.4.2
Copyright (C) 2009 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

An d I'm trying to run it in tsim like so:
tsim-leon
then I get no print when executing it:
bisel <at> serv-its:~/network/home/mkprom_leo$ ~/tsim-leon-2.0.26/tsim/linux/tsim-leon

 TSIM/LEON SPARC simulator, version 2.0.26 (professional version)

 Copyright (C) 2013, Aeroflex Gaisler - all rights reserved.
 For latest updates, go to http://www.gaisler.com/
 Comments or bug-reports to support-FkzTOoA/JUlBDgjK7y7TUQ@public.gmane.org

serial port A on stdin/stdout
allocated 4096 K RAM memory, in 1 bank(s)
allocated 32 M SDRAM memory, in 1 bank
allocated 2048 K ROM memory
icache: 1 * 4 kbytes, 16 bytes/line (4 kbytes total)
dcach e: 1 * 4 kbytes, 16 bytes/line (4 kbytes total)
tsim> load hello.exe
section: .text, addr: 0x40000000, size 24608 bytes
section: .data, addr: 0x40006020, size 2912 bytes
read 285 symbols
tsim> ru
starting at 0x40000000


Program exited normally.
tsim>

What is going on? Where is my printf going? :/




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alhawaj | 9 Apr 08:04 2014
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Micron DDR3 Model



Hello Everyone,

I was trying to simulate ML605 using vsim on the latest package grlib-gpl-1.3.4-b4140. I ended up with errors that the ports on DDR3 model in verilog mismatch the ports defined in the testbench in VHDL. After a bit of investigation, I figured out that the problem comes from here:

    inout   dm_tdqs;                        < THIS LINE
    input   [BA_BITS-1:0]   ba;
    input   [ADDR_BITS-1:0] addr;
    inout   [DQ_BITS-1:0]   dq;
    inout   dqs;                            < THIS LINE
    inout   dqs_n;                          < THIS LINE

These ports should be defined as an array. Therefore, I changed their definition to:

    inout   [DM_BITS-1:0]   dm_tdqs;
    input   [BA_BITS-1:0]   ba;
    input   [ADDR_BITS-1:0] addr;
    inout   [DQ_BITS-1:0]   dq;
    inout   [DQS_BITS-1:0]  dqs;
    inout   [DQS_BITS-1:0]  dqs_n;

I didn't have the chance to simulate the design as I am still fixing some modifications I made unrelated to this, but my modification made the vsim-compile of the design to go smoothly. However, did I modify the files correctly and is my assumption correct in this situation?

-Khalid



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Jack Morrison | 9 Apr 07:43 2014

Getting started/RAM simulation error

Hello. I'm trying to get up to speed on building a LEON3 system. I've 
run into a number of minor issues that I've been able to work around, 
but I'm getting stuck while running a behavioral simulation.

My setup is:
- Windows 7 64-bit, Cygwin (I suspect things would have gone easier 
under Linux)
- grlib-gpl-1.3.4-b4140
- Xilinx ISE 14.7 WebPack (note that Vivado tools don't support Spartan6)
- BCC 1.0.44

I'm starting from the leon3-gr-xc6s sample design. The only change I 
made was to disable gigabit ethernet since that's not supported in the 
GPL version. I ran "make mig39" and "make install-secureip" okay.

I got the dreaded Cygwin fork failures running "make planAhead". To work 
around this, I broke it into steps:
	make -n planAhead/leon3mp_planAhead.tcl >! foo
	bash foo
	make planAhead

That runs and eventually builds a bit file (the actual board hasn't 
arrived yet so I don't know if the bit file will work). There are over 
3000 warnings though, and I worry that some of them shouldn't be ignored.

I was also able to "make soft" and build prom.srec and ram.srec.

The real fun begins with simulation. I loaded the leon3mp.xise into ISE 
Navigator, selected Simulation view and testbench.vhd as top-level file, 
and ISim simulator process. Unlike the planAhead tool, this seems to 
have a lot of trouble loading the VHDL files, giving bogus complaints 
about circular references and components missing from the libraries. I 
got it to work eventually by renaming work.config to work.bconfig (so it 
wouldn't confuse it with grlib.config), and toggling from manual to auto 
compile order and back, and then rearranging the order on some files.

The simulator starts up, and I get messages showing components being 
initialized (copied below). And I can see the main clock running, and 
reset go inactive. But then I run into trouble:

at 3176001 ps(2), Instance /testbench/ddr2mem/\ddr2mem0(0)\/u1/ : 
Warning: WARNING : (STATE_MACHINE) : Illegal Command Issued. Command 
Ignored.
[this repeats every 4 ns]

I tried to trace this down, it looks like the memory instance is 
decoding an "error" command because RAS and CAS (among other signals) 
are Undefined (they start out as "Z" but change to "U" after reset 
finishes and the ddrclk starts toggling).

Probably some of these earlier warnings are relevant, but I don't know 
how to fix them:

[from fuse.log]
Starting static elaboration
WARNING:HDLCompiler:89 - 
"...mig39/mig_39/user_design/rtl/mcb_raw_wrapper.vhd" Line 4093: <mcb> 
remains a black-box since it has no binding entity.
WARNING:HDLCompiler:220 - 
"...grlib-gpl-1.3.4-b4140/lib/gaisler/sim/sram.vhd" Line 93: Assignment 
ignored
Completed static elaboration
WARNING:Simulator:648 - 
"...mig39/mig_39/user_design/rtl/mcb_raw_wrapper.vhd" Line 4093. 
Instance mcb is unbound

[from isim.log]
Simulator is doing circuit initialization process.
at 0 ps, Instance

/testbench/cpu/mig_gen/ddrc/MCB_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib/mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/ 
: Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the 
result will be 'X'(es).
at 0 ps: Note: The 200 us wait period required before CKE goes active 
has been skipped in Simulation 
(/testbench/cpu/mig_gen/ddrc/MCB_inst/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib/mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/).
Finished circuit initialization process.
LEON3 GR-XC6S-LX75 Demonstration design
GRLIB Version 1.3.4, build 4140
Target technology: spartan6  , memory library: spartan6
ahbctrl: AHB arbiter/multiplexer rev 1
ahbctrl: Common I/O area disabled
ahbctrl: AHB masters: 4, AHB slaves: 16
ahbctrl: Configuration area at 0xfffff000, 4 kbyte
ahbctrl: mst0: Aeroflex Gaisler        LEON3 SPARC V8 Processor
ahbctrl: mst1: Aeroflex Gaisler        AHB Debug UART
ahbctrl: mst2: Aeroflex Gaisler        JTAG Debug Link
ahbctrl: mst3: Aeroflex Gaisler        GR Ethernet MAC
ahbctrl: slv0: European Space Agency   LEON2 Memory Controller
ahbctrl:       memory at 0x00000000, size 512 Mbyte, cacheable, prefetch
ahbctrl: slv1: Aeroflex Gaisler        AHB/APB Bridge
ahbctrl:       memory at 0x80000000, size 1 Mbyte
ahbctrl: slv2: Aeroflex Gaisler        LEON3 Debug Support Unit
ahbctrl:       memory at 0x90000000, size 256 Mbyte
ahbctrl: slv4: Aeroflex Gaisler        Xilinx MIG DDR2 Controller
ahbctrl:       memory at 0x40000000, size 128 Mbyte, cacheable, prefetch
ahbctrl: slv6: Aeroflex Gaisler        Test report module
ahbctrl:       memory at 0x20000000, size 1 Mbyte
ahbctrl: slv13: Aeroflex Gaisler        AHB/APB Bridge
ahbctrl:       memory at 0x80100000, size 1 Mbyte
apbctrl: APB Bridge at 0x80000000 r
apbctrl: slv0: European Space Agency   LEON2 Memory Controller
apbctrl:       I/O ports at 0x80000000, size 256 byte
apbctrl: slv1: Aeroflex Gaisler        Generic UART
apbctrl:       I/O ports at 0x80000100, size 256 byte
apbctrl: slv2: Aeroflex Gaisler        Multi-processor Interrupt Ctrl.
apbctrl:       I/O ports at 0x80000200, size 256 byte
apbctrl: slv3: Aeroflex Gaisler        Modular Timer Unit
apbctrl:       I/O ports at 0x80000300, size 256 byte
apbctrl: slv4: Aeroflex Gaisler        PS2 interface
apbctrl:       I/O ports at 0x80000400, size 256 byte
apbctrl: slv5: Aeroflex Gaisler        PS2 interface
apbctrl:       I/O ports at 0x80000500, size 256 byte
apbctrl: slv6: Aeroflex Gaisler        SVGA frame buffer
apbctrl:       I/O ports at 0x80000600, size 256 byte
apbctrl: slv7: Aeroflex Gaisler        AHB Debug UART
apbctrl:       I/O ports at 0x80000700, size 256 byte
apbctrl: slv9: Aeroflex Gaisler        AMBA Wrapper for OC I2C-master
apbctrl:       I/O ports at 0x80000900, size 256 byte
apbctrl: slv10: Aeroflex Gaisler        General Purpose I/O port
apbctrl:       I/O ports at 0x80000a00, size 256 byte
apbctrl: slv11: Aeroflex Gaisler        General Purpose I/O port
apbctrl:       I/O ports at 0x80000b00, size 256 byte
apbctrl: slv12: Aeroflex Gaisler        General Purpose I/O port
apbctrl:       I/O ports at 0x80000c00, size 256 byte
apbctrl: slv13: Aeroflex Gaisler        AHB Status Register
apbctrl:       I/O ports at 0x80000d00, size 256 byte
apbctrl: slv14: Aeroflex Gaisler        GR Ethernet MAC
apbctrl:       I/O ports at 0x80000e00, size 256 byte
apbctrl: slv15: Aeroflex Gaisler        Gaisler RGMII Interface
apbctrl:       I/O ports at 0x80001000, size 4 kbyte
apbctrl: APB Bridge at 0x80100000 r
apbctrl: slv0: Aeroflex Gaisler        Xilinx MIG DDR2 Controller
apbctrl:       I/O ports at 0x80100000, size 256 byte
leon3_0: LEON3 SPARC V8 processor rev 3
leon3_0: icache 2*8 kbyte, dcache 2*4 kbyte
dsu3_2: LEON3 Debug support unit + AHB Trace Buffer, 4 kbytes
ahbuart7: AHB Debug UART rev 0
ahbjtag AHB Debug JTAG rev 2
testmod6: Test report module
apbuart1: Generic UART rev 1, fifo 4, irq 2, scaler bits 12
irqmp: Multi-processor Interrupt Controller rev 3, #cpu 1, eirq 0
gptimer3: GR Timer Unit rev 0, 8-bit scaler, 2 32-bit timers, irq 8
apbps2_4: APB PS2 interface rev 2, irq 4
apbps2_5: APB PS2 interface rev 2, irq 5
svgactrl6: SVGA controller rev 0, FIFO length: 384, FIFO part length: 
128, FIFO address bits: 9, AHB access size: 32 bits
i2cmst9: AMBA Wrapper for OC I2C-master rev 3, irq 3
grgpio10: 16-bit GPIO Unit rev 2
grgpio11: 32-bit GPIO Unit rev 2
grgpio12: 28-bit GPIO Unit rev 2
ahbstat13: AHB status unit rev 0, irq 1
greth3: 10/100 Mbit Ethernet MAC rev 03, EDCL 1, buffer 16 kbyte 256 
txfifo, irq 6
at 4 ns(3), Instance /testbench/cpu/rgmii0/ : Warning: NUMERIC_STD."=": 
metavalue detected, returning FALSE
[last one repeats 5 more times]

So... is it apparent what I'm doing wrong, or at least what I need to do 
next to make it work? I'm expecting it to run the "GRLIB system test" 
code as described in the library user's manual.

Many thanks for any suggestions.

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paul8mnt | 9 Apr 02:32 2014
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Amba AHB grant unexpected behavior



Hi everybody,

I have designed a peripheral for Leon3 SoC which has an APB slave interface to read/write registers and an AHB master interface that reads data from DRAM, does some computation, then stores the data back to memory. The processor is not involved in the memory transaction, except for the allocation of the region in memory.

The sequence of operations is the following:

1- User app mmaps a buffer in memory and initializes it
2- User app invokes a driver that flushes the cache and pins the pages where the buffer is located
3- The driver writes the registers of the peripheral to start it
4- The driver puts the thread to sleep waiting for the interrupt
5- When the peripheral i s done, the IRQ wakes the thread
6- The driver checks the status and returns to user space
7- Finally the user app checks the result.

grlib version: grlib-gpl-1.3.4-b4140
Linux verion: 3.8.0
Board: vc707 and xupv5

Most of the times everything works fine, however, sometimes I noticed using chipscope that the AHB grant does not return to the processor when my peripheral releases the request.
Is this an expected behavior? RTL simulation and bare metal (with chipscope) show that the grant should return to the processor as soon as the peripheral releases the request (as long as nobody else has priority).
Do you have any suggestions on where I should look inside the code of the bus controller (which so far I have not touched)?


I also have a second unrelated issue: the Ethernet is not working on vc707. I saw a patch on the group and I tried it, but it didn't work. Do I need to set some specific parameters with xconfig to make it work?

Thank you in advance.
Paolo




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bhavishya.goel | 7 Apr 15:07 2014
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Frequency for Nexys 4 board



Hi,

Has the Nexys 4 board tested with main clock (clkm) frequency other than 50 MHz? I tried changing the clkm frequency from 50 MHz to 25 MHz and ran into timing errors. Apparently, this is because of data path from 25 MHz main clock domain to 50 MHz RMII clock (eth_clk90) domain. Here is an example of the output from timing report:

Timing constraint: TS_eth_clk90_nobuf = PERIOD TIMEGRP "eth_clk90_nobuf"
TS_sys_clk_pin * 0.5         PHASE 5 ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 11316 paths analyzed, 1590 endpoints analyzed, 1 failing endpoint
 1 timing error detected. (1 setup error, 0 ho ld errors, 0 component switching limit errors)
 Minimum period is  21.044ns.
--------------------------------------------------------------------------------
Slack:                  -0.261ns (requirement - (data path - clock path skew + uncertainty))
  Source:               eth0.e1/m100.u0/ethc0/r_txlength_2 (FF)
  Destination:          eth0.e1/m100.u0/ethc0/tx_rmii1.tx0/r_tx_en (FF)
  Requirement:          5.000ns
  Data Path Delay:      4.547ns (Levels of Logic = 3)
  Clock Path Skew:      -0.394ns (3.883 - 4.277) div>
  Source Clock:         clkm rising at 0.000ns
  Destination Clock:    eth_clk90 rising at 5.000ns
  Clock Uncertainty:    0.320ns

  Clock Uncertainty:          0.320ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Discrete Jitter (DJ):       0.330ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: eth0.e1/m100.u0/ethc0/r_txlength_2 to eth0.e1/m100.u0/ethc0/tx_rmii1.tx0/r_tx_en
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X23Y159.BQ     Tcko                  0.379   eth0.e1/m100.u0/ethc0/r_txlength(2)
                                                       eth0.e1/m100.u0/ethc0/r _txlength_2
    SLICE_X24Y158.D3     net (fanout=13)       0.688   eth0.e1/m100.u0/ethc0/r_txlength(2)
    SLICE_X24Y158.CMUX   Topdc                 0.449   eth0.e1/m100.u0/ethc0/tx_rmii1.tx0/r_tx_en_PWR_131_o_MUX_7089_o11
                                                       eth0.e1/m100.u0/ethc0/tx_rmii1.tx0/r_tx_en_PWR_131_o_MUX_7089_o111_F
                                                &n bsp;      eth0.e1/m100.u0/ethc0/tx_rmii1.tx0/r_tx_en_PWR_131_o_MUX_7089_o111
    SLICE_X25Y162.D6     net (fanout=5)        0.523   eth0.e1/m100.u0/ethc0/tx_rmii1.tx0/r_tx_en_PWR_131_o_MUX_7089_o11
    SLICE_X25Y162.D      Tilo                  0.105   eth0.e1/m100.u0/ethc0/tx_rmii1.tx0/r_tx_en_PWR_131_o_MUX_7089_o
                                                       eth0.e1/m100.u0/ethc0/tx_rmii1.tx0/r_tx_en_PWR_131_o_MUX_7089_o116
    SLICE_X0Y175.A6      net (fanout=5)        1.161   eth0.e1/m100.u0/ethc0/tx_rmii1.tx0/r_tx_en_PWR_131_o_MUX_7089_o
    SLICE_X0Y175.A       Tilo                  0.105   eth0.e1/m100.u0/ethc0/tx_rmii1.tx0/r_main_state[3]_X_108_o_Mux_117_o
                                                       eth0.e1/m100.u0/ethc0/tx_rmii1.tx0/Mmux_r_main_state[3]_X_108_o_Mux_117_o11
    OLOGIC_X0Y177.D1     net (fanout=2)        0.430   eth0.e1/m100.u0/ethc0/tx_rmii1.tx0/r_main_state[3]_X_108_o_Mux_117_o
    OLOGIC_X0Y177.CLK    Todck                 0.707   eth0.e1/m100.u0/ethc0/tx_rmii1.tx0/r_tx_en
                                                       eth0.e1/m100.u0/ethc0/tx_rmii1.tx0/r_tx_en
    -------------------------------------------------  ---------------------------
    Total                                      4.547ns (1.745ns logic, 2.802ns route)
                                                       (38.4% logic, 61.6% route)



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Gmane