Good evening everyone,
I'm currently writting a component in order to watch what is going with the memory controller:
I'm working in the memory controller of the leon3 available on gaisler/aeroflex website (the main purpose of this group).
Long story, short:
I want to make a component which I can use to monitor a range of adress (I have check the component alone with a testbench, not with simulation of the whole projet because hconfig doesn't do the job, and the component don't work on the board of course).
I already declare the new ahb_menbar in the hconfig of the mctrl.vhd but I can't reach the component (as manual said in the Plug and Play section for AHB).
So I check the address which contains configuration for slaves/ma
I found all previous corresponding configuration (aka IO/RAM/ROM, as manual said and so the vhdl is coherent with it). I can't see anything at 0xFFFFF840 in GRMON with a fouth ahb_menbar in the BAR register, it's just zeros.
I use xilinx ISE, and the component is not trimed (on the rtl), the test signal are also connected, but not used in the component.
So here's my QUESTIONS:
Is(/are) there any another thing(s) other than hconfig to set an address to a component ?
Do I need to add Scan Support (as mentionned in the grlib page 57) ?
Or is it only for the sake of info sys (in grmon) or/and the simulation ?
I tried to use ChipScope Pro but it just s***w my projet (clkm signal is missing in the leon3mp.vhd is really the vhdl) and had to start over from another backup projet but from now on, I don't that's going to help me anyway.
All things I already did:
Declared my vhd in the package memoryctrl: works (ise and make scripts where automatically updated)
entity mctrl is
mymaddr: integer := 16#A00#;
mymmask: integer := 16#FFF#;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_
membar(ioaddr, '0', '0', iomask),
6 => ahb_membar(ramaddr, '1', '1', rammask),
7 => ahb_menbar(mymaddr, 0, '0', mymmask),
others => zero32);
constant mycomp: integer := 3;
type reg_type is record
area : std_logic_vector(0 to 3);-- previously 0 downto 2
signal ahbso_bidon : ahb_slv_out_type;
acomp : mycompname
hindex => 7,
hirq => 0,
mymaddr => 16#A00#,
mymmask => 16#FFF#
rstn => rst,
clk => clk,
ahbsi => ahbsi,
ahbso => ahbso_dummy
area := ahbsi.hmbsel(0 to 3);-- previously 0 to 2
if area(mycomp)= '1' then
ahbso.hrdata <= ahbso_dummy.hrdata;
if r.area(mycomp) = '1' then
Am I doing it wrong ?
Posted by: jerome.vaessen-/E1597aS9LQAvxtiuMwx3w@public.gmane.org