Issue with ECDL via GRMON2 on Terasic DE2-115 board

Hi All,

I have a bit of issue with connecting the LEON3 systems on Terasic DE2-115 board via GRMON2 ECDL.
I am using "GRMON2 LEON debug monitor v2.0.68 32-bit pro version".

Basically, I am using the template design provided in the GRLIB. I am able to connect the DSU through the JTAG interface.

I have done the following setup:

The host is Windows 7 64-bit. I have CentOS 6.5 64-bit Linux running as guest on VMWare Player.
The network setting between the host and guest is NAT. The static IP address is set to in Windows.
I used a 5-port 10/100 Belkin switch in between the Terasic DE2-115 and the PC.

I am not able to establish the ECDL via GRMON2 from both Windows and Linux.
I got this message:

Ethernet startup...
Ethernet initialization failure, retrying

On the Terasic DE2-115 board, I used Ethernet Port 0 and the jumper JP1 is set to short pin 2-3.

I am able to ping another development kit with Linux running on ARM Cortex connected to
one of the po rts of the switch with IP address

To me, my setup does not seem to have any issue.

Is this due to GRMON2 or something else?

Yan Lin Aung

Posted by: Yan Lin Aung <yan_lin_aung-/E1597aS9LQAvxtiuMwx3w@public.gmane.org>


GHDL compilation error > "object subtype is not locally static"

I am trying to compile latest GRLIB with GHDL (0.31 for Ubuntu14.04). I see that compilation fails with following error
"object subtype is not locally static" .

Any suggestions if there any fix for this issue?

Best Regards,


Posted by: hariprasad.palli-/E1597aS9LQAvxtiuMwx3w@public.gmane.org


random replacemet counter


I need some suggestion if someone has a good idea how can I change the random replacement counter that it effect the execution time of a code (C -code)

I try to generate a random number and give it to counter but it didn't effect the timing on each run the execution time remain the same

if you see this code i have change the r.rndcnt+1 with r.rndcnt+random_sig which is my random number , it should effect the timimg as timer value changed but unfortunately NOT. Does anyone has any idea.

-- random replacement counter
    if ISETS > 1 then
      --if conv_integer(r.rndcnt) = (ISETS - 1) then v.rndcnt := (others => '0');
    if conv_integer(r.rndcnt) = (ISETS - 1 00) then v.rndcnt := (others => '0');
      -- else v.rndcnt := r.rndcnt + 1; end if;
    else v.rndcnt := r.rndcnt + random_sig; end if;
    end if;

Posted by: hassananwarpoly-/E1597aS9LQAvxtiuMwx3w@public.gmane.org


[L3STAT] How many events occur simultaneously?


It is possible that more than one event occurs in a single clock cycle?




Posted by: almeidajr-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org


new debugger tool

Came across an alternative to GRMON, new debugger tool evaluation available from http://ocetechnology.com/ 

Posted by: Jon Murphy <jonnyjmurphy-/E1597aS9LQAvxtiuMwx3w@public.gmane.org>


microzed ?

I'm a studying Verilog and working with a microZed board. In looking at the documentation, it seems the ZedBoard is supported but I was unsure if the microZed board was.

I would be grateful if someone could point me to some documentation and/or a web page where it walks one through the process for a microzed.

Thanks for any help you can provide.

Brad Walker

Posted by: Brad Walker <bwalker-WlSugiYO8JFBDgjK7y7TUQ@public.gmane.org>


please help : either I am wrong or found a bug

Dear all;

I am simulating some C codes on a leon-3. These C-codes are working fine on grmon terminal and on tsim, but when run these code on modelsim these codes didn't work. The problem is with the prom.srec or either with ram.srec.

After reading people comments and searching on the web I have develop that prom.srec contains application data and ram.srec contains processor booting configurations. but after working on it i think i misunderstood it . As prom.srec file never change its contents but ram.srec though change every time when you change your C code.

For example, when I run  ram.srec file which is drived by helloworld .c on a tsim it give me "hello world" ouptput.

But in modelsim simulator I dnt know what the problem s it always runs o nly prom.srec file .....one  flush and clr statements only.

Please tell me how can I do see all instruction of my c codes on modelsim simulator. or there is some bug there which halt the simulation on modelsim.

Posted by: hassananwarpoly-/E1597aS9LQAvxtiuMwx3w@public.gmane.org




to verify my grmon (it did not work with a atlys board), I tried to
leon3 and a sockit board. To eliminate a possible error cause.

I use altera 15.0 and edited qsf_append.qsf and the Makefile and I get
the following error Message:

Error (11802): Can't fit design in device
Error: Quartus II 64-Bit Fitter was unsuccessful. 1449 errors, 6 warnings
    Error: Peak virtual memory: 1233 megabytes
    Error: Processing ended: Fri Sep 25 20:30:58 2015
    Error: Elapsed time: 00:00:55
    Error: Total CPU time (on all processors): 00:00:53

I extracted a fresh grlib tar gz and edited the two files and run

    make qwiz
    make quartus

any ideas ?


kind regards

Posted by: Markus Kreidl <markus.kreidl@...>


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save tsim output in text file

I am running my code on tsim


load systest.exe
hist 1000
inst 1000

I want to save the inst output to the text file is their any way because I tried

inst 1000 > *.txt

but > is shell syntax didnt work any other way around

Posted by: hassananwarpoly-/E1597aS9LQAvxtiuMwx3w@public.gmane.org


stop flushing the cache

I want to run some C codes continuously e.g. 1000 times. But every time when code starts from the beginning it flushes the cache,is their any way that after first run it didn't flush the cache.

Posted by: hassananwarpoly-/E1597aS9LQAvxtiuMwx3w@public.gmane.org


random seed signal

Is their anyone who know how to change the random seed input value if  I am using random replacement policy.

where is this signal ????

Posted by: hassananwarpoly-/E1597aS9LQAvxtiuMwx3w@public.gmane.org