are ther some MPI implementation for the LEON3 out there?

Posted by: fabikem-LWAfsSFWpa4@public.gmane.org


multicore compiler problem with snapgear linux 2.6

Hi everybody, Hi Jiri,

I worked with the support SMP kernel for leon3:  Snapgear 2.6.21. I have implemented the Leon3mp architecture with four Leon3 processors on virtex ML507 board.
I have created 4 threads in my c application, and I am trying to set thread 1 to run on CPU1, thread2 on CPU 2, etc.
However, an>the compiler sparc-linux-gcc does not recognize these functions:

CPU_SET (int cpu, cpu_set_t * set);
CPU_ZERO (cpu_set_t * set);

and this type: cpu_set_t
It always gives me these errors:

implicit declaration of funtion 'CPU_ZERO'
implicit declaration of funtion 'CPU_SET'
'cpu_set_t' undeclared (first use in this function)

Here is my code to bind active thread to processor 0:
cpu_set_t mask;
CPU_ZERO (& mask);
CPU_SET (0, & mask) // bind processor 0
sched_setaffinity (0, sizeof(mask), & mask);

I have included and defined at the top :

#define _GNU_SOURCE
#include <sched.h>

But I always get the same errors.v>

can you help me please.

I would really appreciate any help.
Thanks in advance

Posted by: jerbi78-/E1597aS9LQAvxtiuMwx3w@public.gmane.org


Leon3 custom APB peripheral raise interrupt and catch it on RTEMS

Hello all,

I am developing a peripheral to read data from an ADC. I am using RTEMS.

I already have the APB peripheral working fine and I can read the data from it (although I am still using fake data just to test the APB connection).

However, I need to raise an interrupt when the ADC has data ready.

If I trigger the interrupt by calling LEON_Force_interrupt, it enters the isr handler, so the listeners should be well initialized.

I am using a physical button to raise the interrupt, and the led shows the button is pressed to give me HW feedbac k.

However, the RTEMS doesn't detect the interrupt that should be generated.

I will show how I did, and I hope it can be useful to someone in the future.

Is this a problem on the VHDL or in the RTEMS?

Any idea is welcome, since I am running out of them, and I guess I am missing some important part here...

Thank you,


VHDL periphera l:

bus_requests_handler : process(rstn, clk)


    if (rstn = '0') then

        rdata <= (others => '0');  

    elsif rising_edge(clk) then  

 rdata <= (others => '0');    -- init

 if (apbi.psel(pindex) = '1') then  

            &n bsp;rdata <= std_logic_vector(to_unsigned(count_value, rdata'length)); 

 end if; 

 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then

             in_data <= signed(apbi.pwdata(31 downto 0)); -- a:=pwdata

          end if;  

 -- Rais e IRQ   

 if button = '1' then --  test with led first 

     led <= '1'; 

     vpirq(pirq) <= '1';


     led <= '0';  

     vpirq(pirq) <= '0';

 end if; 

     end if;

  end process bus_requests_handler; 

  apbo.prdata <= rdata;

  apbo.pindex <= pindex;   

  apbo.pirq <= vpirq; -- This is where I set the pass to the bus data

  apbo.pconfig <= pconfig;


VHDL topmodule:

   adc : entity work.apb_example                    

     generic map (pindex  => 10, paddr => 10, pirq => 12, pmask => 16#FFF#) --

    &n bsp;port map (

       rstn => rstn, 

       clk => clkm, 

       apbi => apbi, 

       apbo => apbo(10), 

       adc_CLK_5Mhz => clk_adc_5_mhz, 

       adc_enable => '1', 

       adc_raw_input => X"ABCD",  


       button => right_button, 

       led => led(7)


And then on RTEMS :

main function:

        int VHDL_PIRQ = 12;//The value in the vhdl pirq

status = rtems_interrupt_catch (irqhandler, VHDL_PIRQ + 16, &old_handle); //Notice the +16




printf ("CLEAR & UNMASK\n");




irq_executed_flag = 0;

while(1) {

if(irq_executed_flag) {

printf ("\n\t --> Caught synchronous trap with vector %d\n", irq_executed_flag);

irq_executed_flag = 0;


else {

volatile unsigned int *padc = (unsigned *) 0x80000A00;

volatile unsigned int adc_val = 0;

printf (".");

adc_val = padc[0];




ISR handler:

       rtems_isr irqhandler( rtems_vector_number vector ) {

      irq_executed_flag = SPARC_REAL_TRAP_NUMBER(vector);


Posted by: nunobrito84-/E1597aS9LQAvxtiuMwx3w@public.gmane.org


Problem in Simulation for ML605

Simulation for ML605 Design  is not working.... compilation is fine as all files compile successfully without any warning but simulation gives fatal error in ddr3ram.vhd line 285

I don't know how to fix it......I am kind of stuck here!

Posted by: zohaibnajam-ur4TIblo6goN+BqQ9rBEUg@public.gmane.org


Trouble creating Debian Image Linuxbuild

Hello all!

I'm trying to create an image of Debian, using the linuxbuild 1.0.5 but I'm getting 404 whenever I try to setup Debian. I guess the ftp got some directories changed.
I also tried with the linuxbuild 1.0.7 but onle allows to select buildroot.
Any ideas? Someone can save me and send me those images?


Posted by: rafael.adorna-/E1597aS9LQAvxtiuMwx3w@public.gmane.org


ML605 Board ddr3_addr port mismatch of 13 and 14


USing REv- E Board 

after make planahead command 

and doing changes from README.txt 

I get following error in planAhead environment

[HDLCompiler 717] Port ddr3_addr of width 13 cannot connect to 14 bit actual ["D:/grlib-gpl-1.3.7-b4144/designs/leon3-xilinx-ml605/leon3mp.vhd":438]

Any help will be highly appreciated 


Posted by: ghazalifahad-/E1597aS9LQAvxtiuMwx3w@public.gmane.org


ML507 egtx_clk error


I'm trying to add a second uart to my grlib system. To do this, i have replicated the block of uart1 to add another uart, as below : 

ua1 : if CFG_UART1_ENABLE /= 0 generate
    uart1 : apbuart -- UART 1
    generic map (pindex => 1, paddr => 1,  pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
    port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
    u1i.rxd <= rxd1; u1i.ctsn <= '0'; u1i.extclk <= '0'; txd1 <= u1o.txd;
  end generate;
  noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
  ua2 : if CFG_UART2_ENABLE /= 0 generate
    uart2 : apbuart -- UART 2
    generic map (pindex => 9, paddr => 9,  pirq => 3, fifosize => CFG_UART2_FIFO)
    port map (rstn, clkm, apbi, apbo(9), u2i, u2o);
    u2i.rxd <= rxd2; u2i.ctsn <= '0'; u2i.extclk <= '0'; txd2 <= u2o.txd;
  end generate;

 After that, I re-synthesize the leon3 design using ISE 13.4, but I received the following error after "make ise-map" completes:

ERROR:Xst:1370 - Line 10: Signal name egtx_clk not found in design.
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:Xst:1341 - XCF parsing failed

can you help me please.
Thanks in advance.

Posted by: Mariem Makni <mariam.makni-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>


The problem running LEON3 in VC709

root <at> sizhao-VirtualBox:/opt/grmon-eval-2.0.54/linux/bin# ./grmon -digilent -nb

  GRMON2 LEON debug monitor v2.0.54 eval version


  Copyright (C) 2014 Aeroflex Gaisler - All rights reserved.

  For latest updates, go to http://www.gaisler.com/

  Comments or bug-reports to support-FkzTOoA/JUlBDgjK7y7TUQ@public.gmane.org


  This eval version will expire on 28/12/2014

 JTAG chain (1): xc7vx690t 

  GRLIB build version: 4140

  Detected frequency:  100 MHz


  Component                            Vendor

  LEON3 SPARC V8 Processor         &nbs p;   Aeroflex Gaisler

  AHB Debug UART                       Aeroflex Gaisler

  JTAG Debug Link                      Aeroflex Gaisler

  LEON2 Memory Controller              European Space Agency

  AHB/APB Bridge                       Aeroflex Gaisler

  LEON3 Debug Support Unit             Aeroflex Gaisler

  Single-port AHB SRAM module          Aeroflex Gaisler

  Xilinx MIG DDR3 Controller           Aeroflex Gaisler

  Sing le-port AHB SRAM module          Aeroflex Gaisler

  Generic UART                         Aeroflex Gaisler

  Multi-processor Interrupt Ctrl.      Aeroflex Gaisler

  Modular Timer Unit                   Aeroflex Gaisler

  AMBA Wrapper for OC I2C-master       Aeroflex Gaisler

  General Purpose I/O port             Aeroflex Gaisler


  Use command 'info sys' to print a detailed report of attached cores

grmon2> info sys

  cpu0      Aeroflex Gaisler  LEON3 SPARC V8 Pr ocessor    

            AHB Master 0

  ahbuart0  Aeroflex Gaisler  AHB Debug UART    

            AHB Master 1

            APB: 80000700 - 80000800

            Baudrate 115200, AHB frequency 100.00 MHz

  ahbjtag0  Aeroflex Gaisler  JTAG Debug Link    

            AHB Master 2

  mctrl0    European Space Agency  LEON2 Memory Controller    

            AHB: 00000000 - 20000000

            APB: 80000000 - 80000100

    &nbs p;       16-bit prom <at> 0x00000000

  apbmst0   Aeroflex Gaisler  AHB/APB Bridge    

            AHB: 80000000 - 80100000

  dsu0      Aeroflex Gaisler  LEON3 Debug Support Unit    

            AHB: 90000000 - A0000000

            AHB trace: 256 lines, 32-bit bus

            CPU0:  win 8, hwbp 2, itrace 256, V8 mul/div, srmmu, lddel 1

                   stack pointer 0x7ffffff0

                   icache 4 * 4 kB, 32 B/line dir

    &n bsp;              dcache 4 * 4 kB, 32 B/line dir

  ahbram0   Aeroflex Gaisler  Single-port AHB SRAM module    

            AHB: 20000000 - 20100000

            32-bit static ram: 4 kB <at> 0x20000000

  mig0      Aeroflex Gaisler  Xilinx MIG DDR3 Controller    

            AHB: 40000000 - 80000000

            APB: 80000400 - 80000500

            SDRAM: 1024 Mbyte

  ahbram1   Aeroflex Gaisler  Single-port AHB SRAM module    

            AHB: A00 00000 - A0100000

            32-bit static ram: 4 kB <at> 0xa0000000

  uart0     Aeroflex Gaisler  Generic UART    

            APB: 80000100 - 80000200

            IRQ: 2

            Baudrate 38343

  irqmp0    Aeroflex Gaisler  Multi-processor Interrupt Ctrl.    

            APB: 80000200 - 80000300

  gptimer0  Aeroflex Gaisler  Modular Timer Unit    

            APB: 80000300 - 80000400

            IRQ: 8

        & nbsp;   8-bit scalar, 2 * 32-bit timers, divisor 100

  i2cmst0   Aeroflex Gaisler  AMBA Wrapper for OC I2C-master    

            APB: 80000900 - 80000A00

            IRQ: 11

  gpio0     Aeroflex Gaisler  General Purpose I/O port    

            APB: 80000A00 - 80000B00


grmon2> load hello 

  40000000 .text                        0B              [>    40000000 .text                      8.0kB /  39.0kB & nbsp; [===  40000000 .text                     16.0kB /  39.0kB   [===  40000000 .text                     24.0kB /  39.0kB   [===  40000000 .text                     32.0kB /  39.0kB   [===  40000000 .text                     39.0kB /  39.0kB   [===============>] 100%

  40009C20 .data                        0B              [>    40009C20 .data                      2.9kB /   2.9kB   [===============>] 100%

  Total size: 41.90kB (258.48kbit/s)

  Entry point 0x40000000

  Image /opt/grmon-eval-2.0.54/linux/bin/hello loaded


grmon2> run

  Unknown signal

  0x40000040: a1480000  mov  %psr, %l0

The hello file is only print "hello world".

I think the leon3 doesn't work. And what reason can lead to this result?

Who can run the leon3 in VC709?  What files can be modified?

Thank you very much!

Posted by: mercket-/E1597aS9LRv1O+Z8WTAqQ@public.gmane.org


g++ produces errors in vhdl simulation

Dear all,

I am trying to run c and c++ code on a leon3 design (leonmp). When compiling c code with gcc it works fine, but as soon as I invoke the g++ compiler (either directly or via gcc by changing the file extension to .cc), my vhdl simulation in modelsim crashes. The code is still the same c code.

The error in modelsim is:
# leon3_0: LEON3 SPARC V8 processor rev 3
# leon3_0: icache 1*4 kbyte, dcache 1*4 kbyte
# ** Fatal: (vsim-3734) Index value 512 is out of range 511 downto 0.
#    Time: 30 ns  Iteration: 5  Process: /testbench/sd0/u0/state_register File: ../../lib/micron/sdram/mt48lc16m16a2.vhd
# Fatal error in ForLoop loop at ../../lib/micron/sdram/mt48lc16m16a2.vhd line 1234
# HDL call sequence:
# Stop ped at ../../lib/micron/sdram/mt48lc16m16a2.vhd 1234 ForLoop loop


- I'm using the latest version of grlib, bcc etc
- I'm using modelsim 10.1d
- I've a very simple file test.c

I've modified leonmp/Makefile to include:

##################  project specific targets ##########################
test.exe: test.c
    sparc-elf-g++ -O2 -Wall -msoft-float -g
test.c -o test.exe

    sparc-elf-objcopy -O srec --gap-fill 0
test.exe ram.srec

Thus my ram.srec overwrites the systest srec. No further changes to the toolchain besides enabling vhdl debugging using xconfig. Placing my srec in the prom gives the same results.

When running the g++ compiled test.exe in tsim it works fine. The same file compile with normal x86 g++ also works.

Am I making a major mistake by assuming c and c++ code will run on the same system without further change? What could be the problem here?


best regards,


Posted by: erikvermij-/E1597aS9LQAvxtiuMwx3w@public.gmane.org


Leon3 Buildroot No Output (DVI) to Monitor


I'm using the buildroot function on Ubuntu, and running "make xconfig". I tried selecting the predefined configurations "lb_config_leon-linux3.10_ngmp.tar.bz2", "lb_config_leon-linux3.10_smp_fpu.tar.bz2", and "lb_config_leon-linux3.10_up_soft.tar.bz2", and when I try running all three versions, I never get output to the monitor I hooked up to the DVI port on the FPGA.

I tried configuring I2C and a few other options, but it still doesn& #39;t work.

I typically run the command "i2c 0 dvi init_ml50x_vga" on GRMON before loading the image.ram file.

Does anyone know how to fix this?




Posted by: meijannis-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org


unknown watchpoint hit


Whenever I try to set the directions of GPIO I get unknown watchpoint hit error. I followed a post on this forum but could not get any rectification.


 I get results on modlesim but on hardware I keep getting unknown watchpoint hit error.



Posted by: m.shehzad.ah-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org