GRLIB GPL 1.4.0-b4154 released

GRLIB GPL 1.4.0-b4154 is now available for download from:


Bitfile and netlist packages are available via:


The changelog is here:


and is also reproduced below.

Some of the highlights are:
* Added template design for Nexys4-DDR
* Added template design for TerASIC SoCKit (experimental)
* Expand netlist package with netlists for 7-series, V6 and Statix IV/V
* Update to support ISE 14.7 and Vivado 2014.4.1 for most Xilinx designs
* Remove GRPCI1 core, add GRPCI2 core
* Add L3STAT IP core (performance counters)
* Several IP core updates with fixes, new features and timing optimisations

Please note that simulation for 7-series AC701/KC705/VC707 does not work
with ModelSim/Questa/Riviera at the moment. There will be a new release
in the near future trying to address this.

If there have been problems reported in this group that have not been
addressed in this release we would appreciate a heads up on those so
(Continue reading)


0MHz detection


I am using Leon3 core on a custom board. I am using GRMON to connect to the Target board using Xilinx Platform USB cable. I see the following, when I enter grmon -xilusb. I made sure a active low signal is the reset and using a 50MHz clock which is generated from a clock generator. I drive some other logic with the same clock and reset signal that controls other peripherals on the board which seem to work fine. Can you please suggest the reason for 0 MHz detection.

Posted by: anuyarlagadda-/E1597aS9LQxFYw1CcD5bw@public.gmane.org


iu3 and data cache interface


I am a bit confused regarding the interface between CPU (iu3) and data cache (dc). The interface contains two address ports (dci.eaddress, dci.maddress). In a store command (double cycle command) during the first clock cycle in the execute stage dci.eaddress and during the second clock cycle dci.maddress are passed (sequentially). In every memory access both addresses are always equal.

I played a bit with the two addresses/ports in order to understand what they are used for by corrupting them. At the beginning it seemed as if only the address passed at dci.maddress is considered during the store command. I came to that conclusion because a corruption of dci.eaddress didn't result in an error.

However I found one case (at there only for one particular address) w here either corruption (dci.eaddress, dci.maddress) results in a faulty write (nothing is written).

Does someone know what exactly the ports are used for?

I couldn't find the information in the provided documents. 

Posted by: richard.bruchthal-/E1597aS9LQAvxtiuMwx3w@public.gmane.org


Performance Counters for LEON3 (v1.3.7-b4144) [2 Attachments]

Hello, LEON Community,

During my work on LEON3, I needed some performance counters to test and verify results. Therefore, I implemented single-cycle accurate performance counters. I attached the performance counter patch to this message as well as an example to how to use them. The header file in the example should be easily included in any code-base and the macros that read the performance counters are straightforward.

The implementation of the performance counters is a bit heavy; therefore, it might restrain how big your design can be. For me, on a VC707, the design went down from 8 cores to 4 cores. The reason behind this drop is that I implement banks for the performance counters. These banks can store a "snapshot" of ALL the performance counters. Then, one can read the values one by one. The counters are 64-bits. Therefore, it is pretty hard to overflow these counters.

Supported counters are as follows:
  1. Time Stamp (TS)
  2. Instruction Cache Total Misses
  3. Instruction Cache Total Accesses
  4. Data Cache Total Misses
  5. Data Cache Total Accesses
  6. Branchprediction Total Miss-predicts
  7. Branchprediction Total Predicts

I have left out one important counter, which is Total Instructions Committed. However, I am planning to add this in the future.

The default setting is that the design has TWO banks. Both Macros, the one that start the performance counters and the one that stop them, actually record a snapshot of the performance counters into one bank OR the other; these snapshots-recording are each one instruction that takes one cycle. Subsequently, the program starts to fetch the performance counters one by one and perform a subtraction to find the measurements for the code.

The ISA was modified to include special instructions for the performance counter; HOWEVER, no modification is needed for the compiler. If you have the time and you look through the header file, you will see a simple trick that I came-up with to include custom instructions in the compiled code.

If anyone has any idea/question, please feel free to ask it here so people can contribute/assist.


__._,_.___ View attachments on the web
Posted by: alhawaj <alhawaj-fWAZDB8bsKe+fmr0zi+kZQ@public.gmane.org>

Attachment (performance_counters_example.tar.bz2): application/octet-stream, 2943 bytes
Attachment (perfcounters.patch): application/octet-stream, 40 KiB

Adding Xilinx IP cores to a LEON3 using "make planahead"

Hi all,

I want to do the same thing discussed in this link but on a Virtex6 ML605 board. The problem is that, with the "make planahead" command for Virtex 6 in ISE 14.x, it seems like it doesn’t look into any "Cores Search Directories" as it was the procedure with "make ise" (like ../../netlists/xilinx/VirtexXX).
Any suggestion how I can add IP core to the LEON3 processor?



Posted by: razi_seyyedi <at> yahoo.com


AHB clk and Processor clk


GRLIB release: 1.2.2

Target Board: ML509


I am working on clock gating and processor frequency scaling, now I need to know that can I have separate clocks for AHB and Processor as I should have when implementing clock gating. secondly I have  implemented dynamic frequency scaling and it works fine on bare-metal but with O.S when I change the frequency, UART start printing unknown and garbage values, Is it because I have changed the frequency of the source clock (clkm) to UART module


Posted by: zohaibnajam-ur4TIblo6goN+BqQ9rBEUg@public.gmane.org


Composing a 32Kb AHBRAM with a single RAMB36E1 instance

Is it feasible to compose a 32Kb AHBRAM with a single RAMB36E1 instance?
Created by: andrewmarkkeller
  1. Yes
  2. No

I spent the morning looking at the memory layout of a 32kb AHBRAM.  The GRLIB AHBRAM core breaks the memory into 4 SYNCRAMs each with 4 RAMB18E1 instances associate with them (a total of 16 Block RAM instances).

After studying the AHB bus, in theory it should be possible to provide a 32Kb AHBRAM using a single RAMB36E1 instance without suffering a performance loss (at least on a kintex-7 <at> 100MHz)

There is approximately 2MBits of BRAM available on the chip I am using (k7 325t). I want to take the most advantage of these resources that I can.

What are your general thoughts on the feasibility of this undertaking?

Posted by: andrewmarkkeller-/E1597aS9LQAvxtiuMwx3w@public.gmane.org


Building leon3 in spartan 6


Could someone help me on this one?
After make xconfig in grlib-gpl/designs/leon3-xilinx-sp605,
All i did was to enable FPU and change it from GRFPU to GRFPU-LITE.
$ make mig
$ make install-secureip
$ make ise

Unfortunately it prompted an error:
Checking expanded design ...
ERROR:NgdBuild:604 - logical block 'nosh.cpu[0].l3s.u0/leon3x0/p0/iu/dis2.x0'
   with type 'cpu_disasx' could not be resolved. A pin name misspelling can
   cause this, a missing edif or ngc file, case mismatch between the block name
   and the edif or ngc file name, or the misspelling of a type name. Symbol
   'cpu_disasx' is not supported in target 'spartan6'.
WARNING:NgdBuild:452 - lo gical net 'N2893' has no driver
WARNING:NgdBuild:452 - logical net 'N2894' has no driver
WARNING:NgdBuild:470 - bidirect pad net 'spi_sel_n' has no legal driver

I am using ububtu and xilinx 13.2. Does anyone know how to resolve this?

Thank you.

Marianne Borces

Posted by: borces.mgmendiola-/E1597aS9LToLY4ysWL1ZA@public.gmane.org


writing to asr19 from linux


I know that write access to ASRs are privileged and can be done from supervisor mode but again this requires writing to 'S' bit of 'PSR' which can be easily done on bare metal (without O.S underneath) but I want to know how can I write to ASR19 from linux 3.1

Actually I am working on clock gating and in order to force the processor to power-down mode I need to perform the following instruction

__asm__ __volatile__("wr %g0,%asr19\n\t");


Note that currently writing to ASRs from O.S generates a trap i.e illegal instruction


Posted by: zohaibnajam-ur4TIblo6goN+BqQ9rBEUg@public.gmane.org


Weird AHBCTRL behavior


In my lab we found a weird behavior with the AHBCTRL, when an ABH slave
located at index 0 holds its Hready signal to '0' it blocks the whole
AHB bus. If you move this slave to a higher index the bus will work
correctly. Normally a busy slave shouldn't block the bus specially if
you don't try to talk with him?
Is it due to the default selected slave in the controller, if yes
shouldn't it let the arbiter work?

Best regards,

libmpfr.so.1 missing for sparc-rtems toolchain

When I try to compile under Ubuntu 14.04 (64-bit) I'm getting the following error:

/opt/rtems-4.10/libexec/gcc/sparc-rtems/4.4.6/cc1: error while loading shared libraries: libmpfr.so.1: cannot open shared object file: No such file or directory

I googled a lot, but no suggestion solved the problem.

Any help is appreciated.

Regards, Rolf

Posted by: rolf.schroedter-jFBKDsIvBNU@public.gmane.org