1 Jan 01:59
Re: [EE] Current Production Digital Clock Chips
Jinx <joecolquitt <at> clear.net.nz>
2009-01-01 00:59:24 GMT
2009-01-01 00:59:24 GMT
> The first thing you need is one line that goes high and low once > a second That is so easy. With hindsight !! There are common ways to do it (1) use a single crystal for clock and core (2) separate crystals (3) count mains cycles An example of (1) would be to have, for example, a 19.6608MHz on the OSC pins and use one of the PICs timers (or, more accurately, hardware counters) to divide this frequency down So, the PIC's Fosc will be 19,660,800/4 = 4,915,200Hz If you use the 16-bit TMR1 as the divider, it's first loaded with 0x4000, which equates to d49152 counts below the rollover of 0x0000. Therefore, it takes 49152 transitions of Fosc for TMR1 to count up to 0x0000, and TMR1IF to be set (which can be polled or used as an interrupt). As Fosc is 4,915,200Hz, then this will happen 100 times/sec. That can be further divided down with a RAM register to get 1Hz Note that power consumption rises per MHz TMR1 can also have its own crystal, independent of the core. Generally this would be a 32768Hz "watch" crystal. Again, you pre-load TMR1 with a value to get the division you want. If you used TMR1 in 16-bit free-run mode, it takes 65536 counts for a cycle, or 0.5Hz ( = 32768/(Continue reading)
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