Re: [Discussion/Prec] The record speed up plan (Make speed like without prec)
Hui Zhu <teawater <at> gmail.com>
2010-05-04 02:46:35 GMT
On Sat, May 1, 2010 at 11:12, paawan oza <paawan1982 <at> yahoo.com> wrote:
> please find my analysis below.
>>> the first thing is, how can we rely on recording volatile memory locations. infact is is even problem
with curent prec, as the moment w are going to record next insn and volatile locations are changed then ?
>>> another point as Eli suggested, share memory, shared semaphores in short memory which we do not have
control over at a particular time.
>>> we dont know how big is the process, and we try to record everything from the beginning, and we use memory
(are we going to come up with file concept for prec info !! ), then we exhaust virtuall address space may be,
and use may not need that much of prec also.
>>> currently we have not talkd to kernel guys to provide kernel support for reversible debigging, which
should essentially support reversible debugging of signals, I/O and many more primitive things, I am not
sure how this model will fit over there because there may be many asynchronous events we might want to play
I still didn't find some thing need kernel do.
I need inferior stop on special insn like rdtsc, but looks x86 cpu
doesn't support it.