1 Apr 2009 01:37
Re: help for arm avr bfin cris frv h8300 m68k mcore mmix pdp11 rs6000 sh vax
Alexandre Oliva <aoliva <at> redhat.com>
2009-03-31 23:37:15 GMT
2009-03-31 23:37:15 GMT
On Mar 13, 2009, Paolo Bonzini <bonzini <at> gnu.org> wrote: > For 4.5 I would like to improve our RTL canonicalization so that no > out-of-range shifts are ever in the RTL representation. FR-V non-vector shifts truncate a register shift count to 5 bits; it's from the ISA specs, it doesn't appear that the same truncation is applied to 10- or 12-bit immediate shift operands. Vector shifts truncate the 6-bit immediate shift count to 4 bits. -- -- Alexandre Oliva, freedom fighter http://FSFLA.org/~lxoliva/ You must be the change you wish to see in the world. -- Gandhi Be Free! -- http://FSFLA.org/ FSF Latin America board member Free Software Evangelist Red Hat Brazil Compiler Engineer
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