Re: Regarding bug 22480, vectorisation of shifts
Paolo Bonzini <paolo.bonzini <at> lu.unisi.ch>
2005-09-01 07:24:26 GMT
Uros Bizjak wrote (privately, but I forwarded to GCC in order to get help):
>Hello Paolo!
>
>I was looking at PR middle-end/22480 if there is something to fix at the i386
>backend. However, there is no documentation at all regarding vec_shl_≤mode> and
>vec_shr_≤mode> builtins.
>
>
Heh, I'm quite at a loss regarding PR22480. I don't know exactly what
to do because i386 does not support, e.g. { 2, 4 } << { 1, 2 } (which
would give {4, 16} as a result). There is indeed a back-end problem,
because ashl<mode>3 is supposed to have two operands of the same mode,
not one vector and one SI!
On the other hand, I'm not keen on using vec_shl_≤mode> because these
shift the *whole* register, not each byte/word/dword. i.e. { 0x40000000,
0x80000000 } << 2 = { 2, 0 } which is not really what is expected.
One simple way to fix the PR could be *not* to define ashl<mode>3 insns
for i386. These however would lose vectorization of a shift by
constant.
Another way could be to
1) in the vectorizer, check in the optab if the predicate for each
operand of an insn accepts a register. If not, refuse vectorization if
the corresponding gimple operand is not constant.
2) and add a new predicate to i386 that only accepts CONST_VECTORs whose
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