headers
Aurelien Jarno | 1 Apr 2007 02:14

[PATCH][SPARC] RDASR and WRASR instructions on SPARCv8

Hi all,

The SPARCv8 RDASR and WRASR instructions currently generate an
illegal_instruction trap for rs1 != 0, whereas the SPARCv8 
manual explicitely says that an rs1 value of 1...14 in an RDASR
instruction produces undefined results, but does not cause an 
illegal_instruction trap. The same applies for WRASR.

The patch below fixes the current implementation by doing the
same thing as the microSPARC II CPU, ie reading the y register
in all cases for the RDASR instruction, and doing a NOP when
rs1 != 0 for the WRASR instruction.

Bye,
Aurelien

Index: target-sparc/translate.c
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/translate.c,v
retrieving revision 1.38
diff -u -d -p -r1.38 translate.c
--- target-sparc/translate.c	25 Mar 2007 07:55:52 -0000	1.38
+++ target-sparc/translate.c	31 Mar 2007 23:52:18 -0000
 <at>  <at>  -1130,11 +1130,14  <at>  <at>  static void disas_sparc_insn(DisasContex
                 rs1 = GET_FIELD(insn, 13, 17);
                 switch(rs1) {
                 case 0: /* rdy */
+#ifndef TARGET_SPARC64
+                case 0x01 ... 0x0e: /* undefined in the SPARCv8 manual, rdy on the microSPARC II */
+                case 0x0f:          /* stbar in the SPARCv8 manual, rdy on the microSPARC II */
(Continue reading)

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headers
Stuart Anderson | 1 Apr 2007 03:18
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Re: [PATCH] semaphore syscalls - refresh

On Sat, 31 Mar 2007, Thiemo Seufer wrote:

>> +    switch( cmd ) {
>> +	case GETALL:
>> +	case SETALL:
>> +	case IPC_STAT:
>> +	case IPC_SET:
>> +           lock_user_struct(target_su, target_addr, 1);
>> +	   target_to_host_semid_ds(ds,target_su->buf);
>> +	   host_su->buf = ds;
>> +           unlock_user_struct(target_su, target_addr, 0);
>> +	   break;
>
> I don't see how this can work with target_su being an uninitialized pointer.

#define lock_user_struct(host_ptr, guest_addr, copy) \
     host_ptr = lock_user(guest_addr, sizeof(*host_ptr), copy)

target_su is the left hand side of the assignment. The macro just hides it.

                                 Stuart

Stuart R. Anderson                               anderson <at> netsweng.com
Network & Software Engineering                   http://www.netsweng.com/
1024D/37A79149:                                  0791 D3B8 9A4C 2CDC A31F
                                                  BD03 0A62 E534 37A7 9149
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headers
Stuart Anderson | 1 Apr 2007 03:52
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Re: [PATCH] clone syscall fix

On Sat, 31 Mar 2007, Thiemo Seufer wrote:

> Stuart Anderson wrote:
>>
>> Even though clone() and fork() are related, they don't seem to be close
>> enough to allow a single routine to be used to implement both. With this
>> patch, the LTP tests for clone now pass.
>
> But it still does the same, assuming VM_CLONE is set, except for passing
> additional arguments to the host call.

I'm not so sure that the VM_CLONE flag should control wether the new
stack is set up or not. There are tests for newsp == NULL inside that
block anyway. The LTP certainly tests combination for which the
do_fork() code doesn't work.

> Passing untranslated regs looks
> like a bug to me, I'm unsure about the tls_val.

Hmm, could be, but that's the way it is in the current code. I think
more testing on additional combination sof target &host will be needed.

>> It may be possible to fold this back into do_fork(), but this just seemed to
>> be a little bit more straightforward.
>
> Since Linux's fork() is just a specialcase of clone() this should be
> done eventually.

I'll try just dropping do_fork completely, and see if this new do_clone()
works for the fork case also. If so, then that effectively folds the
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headers
Blue Swirl | 1 Apr 2007 11:32
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RE: [PATCH][SPARC] Fix the shift instructions for theSPARC target

>The shift instructions on the SPARC target currently take into account
>the whole register as the shift count. According to the SPARC v8 and v9
>manuals, only the lower 5 bits should be taken into account for 32-bit
>instructions (SLL, SRL, SRA), and only the lower 6 bits for 64-bit
>instructions (SLLX, SRLX, SRAX).
>
>The patch below fixes that. Note that SLL and SLLX are now different, as
>they don't take into account the same number of bits. Please apply.

Can you check what happens in real hardware, especially in the case when the 
shift amount is in a register, not immediate, and the value is either >32 or 
==32?

The 64-bit mask should be 0x3f, not 0x2f.

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headers
Thiemo Seufer | 1 Apr 2007 13:16
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qemu .cvsignore Makefile Makefile.target config...

CVSROOT:	/sources/qemu
Module name:	qemu
Changes by:	Thiemo Seufer <ths>	07/04/01 11:16:48

Modified files:
	.              : .cvsignore Makefile Makefile.target configure 
	target-mips    : op_helper.c 

Log message:
	MIPS64 configurations.

CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/.cvsignore?cvsroot=qemu&r1=1.16&r2=1.17
http://cvs.savannah.gnu.org/viewcvs/qemu/Makefile?cvsroot=qemu&r1=1.114&r2=1.115
http://cvs.savannah.gnu.org/viewcvs/qemu/Makefile.target?cvsroot=qemu&r1=1.152&r2=1.153
http://cvs.savannah.gnu.org/viewcvs/qemu/configure?cvsroot=qemu&r1=1.134&r2=1.135
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper.c?cvsroot=qemu&r1=1.33&r2=1.34
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headers
Aurelien Jarno | 1 Apr 2007 13:39

Re: [PATCH][SPARC] Fix the shift instructions for theSPARC target

On Sun, Apr 01, 2007 at 11:32:06AM +0200, Blue Swirl wrote:
> >The shift instructions on the SPARC target currently take into account
> >the whole register as the shift count. According to the SPARC v8 and v9
> >manuals, only the lower 5 bits should be taken into account for 32-bit
> >instructions (SLL, SRL, SRA), and only the lower 6 bits for 64-bit
> >instructions (SLLX, SRLX, SRAX).
> >
> >The patch below fixes that. Note that SLL and SLLX are now different, as
> >they don't take into account the same number of bits. Please apply.
> 
> Can you check what happens in real hardware, especially in the case when 
> the shift amount is in a register, not immediate, and the value is either 
> >32 or ==32?

I have just made the test on real hardware. Specifying a value of 32 leave
the register unchanged. Specifying a value > 32 only takes the lower 5
bits of the value. So exactly as specified in the manual.

> The 64-bit mask should be 0x3f, not 0x2f.

Oops you are right, please find an updated patch below.

Index: target-sparc/op.c
===================================================================
RCS file: /sources/qemu/qemu/target-sparc/op.c,v
retrieving revision 1.26
diff -u -d -p -r1.26 op.c
--- target-sparc/op.c	23 Mar 2007 20:01:20 -0000	1.26
+++ target-sparc/op.c	25 Mar 2007 13:50:45 -0000
 <at>  <at>  -965,38 +965,43  <at>  <at>  void OPPROTO op_logic_T0_cc(void)
(Continue reading)

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headers
Christian MICHON | 1 Apr 2007 14:11
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Gravatar

Re: Bugs

On 3/31/07, James Jacobs <jrj76 <at> optusnet.com.au> wrote:
>
> > Using the start.bat file included with the QEMU package (except changing
> > cd-rom and hard disk image filenames as appropriate).
> > I haven't adjusted any audio settings, I'm using whatever the defaults
> are.
>
> which package ?

you mentionned a package. not me.
did you download the zip containing win32 executables ?

> >I find strange even knoppix does not work with raw images. Have you
> tried "fdisk" inside the guest ? and what "dmesg | grep hda" gives you ?
>
> It doesn't even get that far. I get this kind of error: "qemu: could not
> open hard disk image 'c:\e2\linux\debian.img'" and QEMU then quits. FILEMON
> is showing that the file is being opened read-only for some reason, and the
> resultcode is shown as SHARING.

I'll be offline for a week: send the start.bat to the list, hopefully someone
will look into it.

--
Christian
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headers
Thiemo Seufer | 1 Apr 2007 14:36
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qemu hw/mips_malta.c hw/mips_r4k.c target-mips/...

CVSROOT:	/sources/qemu
Module name:	qemu
Changes by:	Thiemo Seufer <ths>	07/04/01 12:36:18

Modified files:
	hw             : mips_malta.c mips_r4k.c 
	target-mips    : exec.h mips-defs.h op.c op_helper.c 
	                 op_helper_mem.c op_mem.c translate.c 
	                 translate_init.c 

Log message:
	Actually enable 64bit configuration.

CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_malta.c?cvsroot=qemu&r1=1.18&r2=1.19
http://cvs.savannah.gnu.org/viewcvs/qemu/hw/mips_r4k.c?cvsroot=qemu&r1=1.39&r2=1.40
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/exec.h?cvsroot=qemu&r1=1.21&r2=1.22
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/mips-defs.h?cvsroot=qemu&r1=1.9&r2=1.10
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op.c?cvsroot=qemu&r1=1.29&r2=1.30
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper.c?cvsroot=qemu&r1=1.34&r2=1.35
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_helper_mem.c?cvsroot=qemu&r1=1.6&r2=1.7
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/op_mem.c?cvsroot=qemu&r1=1.6&r2=1.7
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/translate.c?cvsroot=qemu&r1=1.42&r2=1.43
http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/translate_init.c?cvsroot=qemu&r1=1.3&r2=1.4
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headers
Blue Swirl | 1 Apr 2007 17:19
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qemu/target-sparc cpu.h translate.c

CVSROOT:	/cvsroot/qemu
Module name:	qemu
Changes by:	Blue Swirl <blueswir1>	07/04/01 15:08:21

Modified files:
	target-sparc   : cpu.h translate.c

Log message:
	Fix Sparc co-processor ops (Aurelien Jarno)

CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/cpu.h?cvsroot=qemu&r1=1.30&r2=1.31
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/translate.c?cvsroot=qemu&r1=1.39&r2=1.40

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Blue Swirl | 1 Apr 2007 17:18
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qemu/target-sparc translate.c

CVSROOT:	/cvsroot/qemu
Module name:	qemu
Changes by:	Blue Swirl <blueswir1>	07/04/01 15:05:09

Modified files:
	target-sparc   : translate.c

Log message:
	Fix Sparc ASR handling (Aurelien Jarno)

CVSWeb URLs:
http://cvs.savannah.gnu.org/viewcvs/qemu/target-sparc/translate.c?cvsroot=qemu&r1=1.38&r2=1.39

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