Kumail Ahmed | 28 Mar 14:48 2015
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Interrupts in GEM5

Hello Everyone, 

Can someone please guide me how can I use the interrupts in SE or FS mode in GEM5?

Best regards,
Kumail Ahmed
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Bigel Hadi | 27 Mar 22:32 2015
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How to create sconscript for McPAT?

Dear all users
I want to integrated McPAT and GEM5.
So, I need a sconscript for McPAT building.
Can anybody help me?
Best regards
hadi


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ESPERANCE ASNGAR | 27 Mar 13:58 2015
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Configuraton of a new system

My Greetings
It is my first time using gem5. I want to simulate a system consisting of a processor with a single core and executes a program.i am working on it for one months and yet i aint able to make it !
i just want to know from which files i should start!
I already run the hello program in both execution mode (syscall & full system ).
Please could someone give me a boost!

--
Cordialement
**********************************************
 ASNGAR DJELAR ESPERANCE 
Master 2 Génie Electrique Informatique Industrielle
56100 Lorient 
Tel:0664117963

************************************************
 
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Matthias Jung | 26 Mar 13:41 2015
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SystemC Co-Simulation

Hi,

I just want to try the SystemC coupling example provided in: gem5/util/systemc
I followed the instructions of the README file.

During this step:

> scons —with-cxx-config —without-python build/ARM/libgem5_opt.so

I get the following error message:

> build/ARM/cxx_config/InstPBTrace.cc: In member function 'virtual SimObject* InstPBTraceCxxConfigParams::simObjectCreate()':
> build/ARM/cxx_config/InstPBTrace.cc:91:25: error: 'SimObject' is an inaccessible base of 'Trace::InstPBTrace'
>      return this->create();
>                          ^
> build/ARM/cxx_config/InstPBTrace.cc:92:1: error: control reaches end of non-void function [-Werror=return-type]
>  }
>  ^
> cc1plus: all warnings being treated as errors
> scons: *** [build/ARM/cxx_config/InstPBTrace.os] Error 1
> scons: building terminated because of errors.

Maybe somebody knows what I’m doing wrong?

Furthermore: is there somewhere a tutorial, which describes how to attache a SystemC-TLM component
(AT/nb_transport) to gem5?

Best Regards
Matthias

—

Dipl.-Ing. Matthias Jung

Member
Advanced Silicon Technologies & Design Methodologies

University of Kaiserslautern
Microelectronic Systems Design Research Group
Erwin-Schrödinger-Straße 12/228
67663 Kaiserslautern, Germany

Phone: +49 631 205 3579
Fax: +49 631 205 4437
jungma <at> eit.uni-kl.de
http://ems.eit.uni-kl.de

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Matheus Alcântara Souza | 26 Mar 00:26 2015
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Miss rate douby

Hi all,

Consider two gem5 simulation enviroments, one with an l2 cache of size 2048kB, and the other with the same parameters, but a smaller l2 cache of 256kB.

I used X86 with fs.py, with Classic Memory System (no Ruby). The results showed an increase in l2 overall miss rate, if the cache is smaller. But the sim_seconds remains the same.

Is it normal? Anyone have suggestions about what to check? 

Best,
Matheus Alcântara Souza
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George Michelogiannakis | 24 Mar 22:59 2015
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Page size and superpages

Hi all,

The page size is set to 8KB for ALPHA in isa_traits.hh

Is this practically feasible to change in FS? Are there more steps than recompiling Gem5 and then the FS kernel?

Also, is there any support for multi-level TLBs or super pages?

Thank you!
  George M
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Nimish Girdhar | 24 Mar 04:31 2015
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Counting cache misses runtime

Hello all,

I am working with ARM full system mode with classic memory model and I want to count the icache, dcache, L2 misses at runtime. I am not able to find where in the source code are these counters resident. I tried tracing back from the regstats in the src/mem/base.cc file but in vain.

Has anybody done it before?  

Thanks,

--
Warm regards
Nimish Girdhar
Department of Electrical and Computer Engineering
Texas A&M University
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Jianghao | 23 Mar 21:24 2015
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Full system simulation and Ruby

Is there anybody who has successful experience to run ALPHA full system 
and Ruby?
I try many different configurations and just cannot boot up the system.
Is this doable or it's the wrong way? I am stuck here for several days 
and thanks for any advice.
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Rodrigo Reynolds Ramírez | 23 Mar 19:07 2015
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Add new structures between caches

Hello everyone,

I am working with cache strategies, I am working with Ruby, specifically with the MOESI_CMP_DIRECTORY policy. I need to add a "buffer" between L1 and L2 (LLC). This buffer will decide is a block goes into L2 or not. I am really lost trying to add this buffer. Could somebody advice me about a good point to start?

Thanks a lot,

Rodrigo
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Renju Boben | 23 Mar 16:43 2015
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Number of active threads

Hi,
   I am working on switching algorithm in big.little architecture.
   For this I need to find the number of active threads. From where can I find this information?

What I want to do is

if (#threads > n)
    use little cores
else
    use big cores

I believe that this code segement has to be added to simulation.py (Please correct me if I am wrong)

Regards,
Renju Boben
renjuboben <at> gmail.com

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yuhang liu | 22 Mar 07:06 2015

Why Memory Bus Utilization is Too Low

Hi All,

I found the memory bus utilization is about 2%. 
This value is too low and is in contradiction with bandwidth wall problem. 
Could someone explain this for me?

system.membus.reqLayer0.utilization               2.3                       # Layer utilization (%)
system.membus.respLayer1.occupancy           54082750                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              2.8                       # Layer utilization (%)

Best regards.
Yuhang




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Gmane