Remapping address in SE mode

Hi,
            I want to remap address using the page table available in se mode of gem5. I went through the page table code and mremapFunc of sys_emul.hh. But could not figure out from where the call to mremapFunc function call is made.
Is there are true virtual memory support. I mean suppose I want to perform page-out and page-in, is it possible to do so with gem5 se mode. All I mean to say is "Suppose, I want to increase physical memory of one process and decrease for other in runtime, is it possible with gem5 se mode paging system.". If it is possible to do so, please give me a pointer to it.

Thanks,
Debiprasanna Sahoo

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Meng Wang via gem5-users | 21 Oct 21:29 2014

arm64 full system simulation cannot find block devices when starts up

Hello,
I tried to run full system simulation for arm64 architecture. I used the latest gem5 simulator and downloaded prebuilt full system image from gem5 website. The command line I used  is:

$ ../gem5/build/ARM/gem5.opt ../gem5/configs/example/fs.py --machine-type=VExpress_EMM64 --kernel=vmlinux-3.14-aarch64-vexpress-emm64 --disk-image=linaro-minimal-armv8.img --dtb-filename=rtsm_ve-aemv8a.dtb

...
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /home/wmeng/workspace/livesp/m5_images/binaries/vmlinux-3.14-aarch64-vexpress-emm64
warn: Highest ARM exception-level set to AArch32 but bootloader is for AArch64. Assuming you wanted these to match.
Listening for system connection on port 5900
Listening for system connection on port 3456
      0: system.cpu.isa: ISA system set to: 0x4a0e540 0x4a0e540
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7001
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80080040
info: Loading DTB file: /home/wmeng/workspace/livesp/m5_images/binaries/rtsm_ve-aemv8a.dtb at address 0x88000000
**** REAL SIMULATION ****
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue <at> 0.  Starting simulation...
warn: SCReg: Writing 0 to dcc0:site0:pos0:fn7:dev0
4101426500: system.terminal: attach terminal 0
warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist
10133760032500: system.cpu.break_event: break event panic triggered
10133760033000: system.cpu.break_event: break event panic triggered
10133760033500: system.cpu.break_event: break event panic triggered
10133760034000: system.cpu.break_event: break event panic triggered

I set up the M5_PATH environment variable, and put the kernel and dtb files in <m5_path>/binaries/,  put rootfs image file in <m5_path>/disks/. Thus I only specify file name instead of full path in command line. 

m5term shows the following error:
...
[    0.047510] TCP: cubic registered
[    0.047511] NET: Registered protocol family 17
[    0.642521] input: AT Raw Set 2 keyboard as /devices/smb.2/motherboard.3/iofpga.7/1c060000.kmi/serio0/input/input0
[    2.542532] input: PS/2 Generic Mouse as /devices/smb.2/motherboard.3/iofpga.7/1c070000.kmi/serio1/input/input2
[    2.542570] VFS: Cannot open root device "sda1" or unknown-block(0,0): error -6
[    2.542571] Please append a correct "root=" boot option; here are the available partitions:
[    2.542572] Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0)
[    2.542573] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.14.0-rc2+ #1
[    2.542574] Call trace:
[    2.542575] [<ffffffc000087d5c>] dump_backtrace+0x0/0x12c
[    2.542576] [<ffffffc000087e9c>] show_stack+0x14/0x1c
[    2.542577] [<ffffffc0004943a0>] dump_stack+0x78/0xc4
[    2.542578] [<ffffffc0004912dc>] panic+0xe8/0x208
[    2.542579] [<ffffffc000645d68>] mount_block_root+0x1d8/0x278
[    2.542580] [<ffffffc000645f20>] mount_root+0x118/0x134
[    2.542582] [<ffffffc00064607c>] prepare_namespace+0x140/0x188
[    2.542583] [<ffffffc0006459bc>] kernel_init_freeable+0x1b8/0x1d8
[    2.542584] [<ffffffc00048f5b4>] kernel_init+0x10/0xd4

Kernel panics on VFS mounting. 

When I changed dtb file to either rtsm_ve-aemv8a-2core.dtb or rtsm_ve-aemv8a-4core.dtb, the kernel hangs after outputing following:

...
[    0.000000] Virtual kernel memory layout:
[    0.000000]     vmalloc : 0xffffff8000000000 - 0xffffffbbffff0000   (245759 MB)
[    0.000000]     vmemmap : 0xffffffbc01c00000 - 0xffffffbc02300000   (     7 MB)
[    0.000000]     modules : 0xffffffbffc000000 - 0xffffffc000000000   (    64 MB)
[    0.000000]     memory  : 0xffffffc000000000 - 0xffffffc020000000   (   512 MB)
[    0.000000]       .init : 0xffffffc000645000 - 0xffffffc000687f40   (   268 kB)
[    0.000000]       .text : 0xffffffc000080000 - 0xffffffc000644104   (  5905 kB)
[    0.000000]       .data : 0xffffffc000688000 - 0xffffffc0006e3618   (   366 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000]  RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=2.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[    0.000000] NR_IRQS:64 nr_irqs:64 0
[    0.000000] Architected cp15 timer(s) running at 100.00MHz (phys).
[    0.007706] sched_clock: 56 bits at 100MHz, resolution 10ns, wraps every 2748779069440ns
[    0.000012] Console: colour dummy device 80x25
[    0.000013] Calibrating delay loop (skipped) preset value.. 3997.69 BogoMIPS (lpj=19988480)
[    0.000014] pid_max: default: 32768 minimum: 301
[    0.000026] Mount-cache hash table entries: 256
[    0.000086] hw perfevents: no hardware support available

Could anyone help me?

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[Slicc Code generation] peek keyword

Dear All, 

I added one  simple public variable to the RubyRequest class in RubyRequest.hh file; and I was trying to access that variable as a part of cache coherence protocol (MOESI_hammer-cache.sm). 

I know after using 'peek keyword (like this: (mandatoryQueue_in, RubyRequest, block_on="LineAddress") {' ; variable 'in_msg' which is of the same type as specified in the input port's declaration declared ( in my case it should be from RubyRequest type). So, I was expecting to access to the variable which I defined  in the body of the RubyRequest Class, like this 'in_msg.variable' . However, it turned out that I can not do that. So, what is the problem. Did I do any thing wrong ?! I wonder maybe 'in_msg' is limited to certain variables! if so, how can I include my own variable to the in_msg variable list.  

Thanks for your help!

Regards,
Reza
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Running Multithreaded Dijkstra on ARM Cortex A7

Hi all,

I need to run the multithreaded (pthread) version of Dijkstra benchmark on
a systemc consisting of multi-cores (say 2) of Cortex A7.

Please note that, I compiled the source code of dijkstra bench mark with
number of processors fixed to 2. I compiled it statically with m5thread
i.e linking thread.o to the object/binary file of bench mark.

First I run the benchmark on se.py. As I mentioned that benchmark has
number of processors fixed to 2. When I use following command

build/ARM/gem5.opt configs/example/se.py -n 2 -c
dijkstra_parallel_squeue_obj --options="2"

It generates the following output with error
--------------------------------------------------------------
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Oct  1 2014 19:17:30
gem5 started Oct 21 2014 16:01:32
gem5 executing on naveed-desktop
command line: build/ARM/gem5.opt configs/example/se.py -n 2 -c
dijkstra_parallel_squeue_obj --options=2
Global frequency set at 1000000000000 ticks per second
      0: system.cpu0.isa: ISA system set to: 0 0xc41ce00
      0: system.cpu1.isa: ISA system set to: 0 0xc41ce00
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
**** REAL SIMULATION ****
info: Entering event queue  <at>  0.  Starting simulation...
info: Increasing stack size by one page.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
fatal: Called sys_clone, but no unallocated thread contexts found!
  <at>  tick 114892000
[cloneFunc:build/ARM/sim/syscall_emul.cc, line 859]
Memory Usage: 588688 KBytes
Program aborted at tick 114892000
Aborted (core dumped)

-------------------------------------------------------------
HOWEVER, if I change number of processors on commandline option to 3,
there is no error as shown below. Can someone explains me why no error
this time?

--------------------------------------------------------
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Oct  1 2014 19:17:30
gem5 started Oct 21 2014 16:06:49
gem5 executing on naveed-desktop
command line: build/ARM/gem5.opt configs/example/se.py -n 3 -c
dijkstra_parallel_squeue_obj --options=3
Global frequency set at 1000000000000 ticks per second
      0: system.cpu0.isa: ISA system set to: 0 0xa9f6e00
      0: system.cpu1.isa: ISA system set to: 0 0xa9f6e00
      0: system.cpu2.isa: ISA system set to: 0 0xa9f6e00
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
0: system.remote_gdb.listener: listening for remote gdb #2 on port 7002
**** REAL SIMULATION ****
info: Entering event queue  <at>  0.  Starting simulation...
info: Increasing stack size by one page.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
Shortest path is 24 in cost. Path is: 0 2 1 6 7 8 10 12 15
Exiting  <at>  tick 129116000 because target called exit()
-----------------------------------------------------------------

SECOND part of my question is that I use the following script (modified
version of se.py) to run the same dijkestra benchmark on Cortex A7. But it
gives error. I first Post here the script and then error

-------------------------------Script---------------------------
import optparse
import sys
import os

import m5
from m5.defines import buildEnv
from m5.objects import *
from m5.util import addToPath, fatal

addToPath('../common')
addToPath('../ruby')

import Options
import Ruby
import Simulation
import CacheConfig
import MemConfig
from Caches import *
from cpu2000 import *
from O3_ARM_v7a import *

def get_processes(options):
    """Interprets provided options and returns a list of processes"""

    multiprocesses = []
    inputs = []
    outputs = []
    errouts = []
    pargs = []

    workloads = options.cmd.split(';')
    if options.input != "":
        inputs = options.input.split(';')
    if options.output != "":
        outputs = options.output.split(';')
    if options.errout != "":
        errouts = options.errout.split(';')
    if options.options != "":
        pargs = options.options.split(';')

    idx = 0
    for wrkld in workloads:
        process = LiveProcess()
        process.executable = wrkld
        process.cwd = os.getcwd()

        if len(pargs) > idx:
            process.cmd = [wrkld] + pargs[idx].split()
        else:
            process.cmd = [wrkld]

        if len(inputs) > idx:
            process.input = inputs[idx]
        if len(outputs) > idx:
            process.output = outputs[idx]
        if len(errouts) > idx:
            process.errout = errouts[idx]

        multiprocesses.append(process)
        idx += 1

    if options.smt:
        assert(options.cpu_type == "detailed" or options.cpu_type ==
"inorder")
        return multiprocesses, idx
    else:
        return multiprocesses, 1

parser = optparse.OptionParser()
Options.addCommonOptions(parser)
Options.addSEOptions(parser)
parser.add_option("--I_Cache",type="string")
parser.add_option("--D_Cache",type="string")

parser.add_option("--TLB_Size",type="string")
parser.add_option("--Volts",type="string")
parser.add_option("--Clocks",type="string")

if '--ruby' in sys.argv:
    Ruby.define_options(parser)

(options, args) = parser.parse_args()

if args:
    print "Error: script doesn't take any positional arguments"
    sys.exit(1)

multiprocesses = []
numThreads = 1

if options.bench:
    apps = options.bench.split("-")
    if len(apps) != options.num_cpus:
        print "number of benchmarks not equal to set num_cpus!"
        sys.exit(1)

    for app in apps:
        try:
            if buildEnv['TARGET_ISA'] == 'alpha':
                exec("workload = %s('alpha', 'tru64', '%s')" % (
                        app, options.spec_input))
            elif buildEnv['TARGET_ISA'] == 'arm':
                exec("workload = %s('arm_%s', 'linux', '%s')" % (
                        app, options.arm_iset, options.spec_input))
            else:
                exec("workload = %s(buildEnv['TARGET_ISA', 'linux', '%s')"
% (
                        app, options.spec_input))
            multiprocesses.append(workload.makeLiveProcess())
        except:
            print >>sys.stderr, "Unable to find workload for %s: %s" % (
                    buildEnv['TARGET_ISA'], app)
            sys.exit(1)
elif options.cmd:
    multiprocesses, numThreads = get_processes(options)
else:
    print >> sys.stderr, "No workload specified. Exiting!\n"
    sys.exit(1)

# Check -- do not allow SMT with multiple CPUs
if options.smt and options.num_cpus > 1:
    fatal("You cannot use SMT with multiple CPUs!")

np = options.num_cpus#reading number of processors input by user
#read Voltage domains
Volts= []
if options.Volts!= "":
       Volts = options.Volts.split(',')
#read clock domains
Clocks=[]
if options.Clocks!= "":
	Clocks= options.Clocks.split(',')
#read I Cache sizes
I_Cache=[]
if options.I_Cache!= "":
	I_Cache= options.I_Cache.split(',')
#read D Cache sizes
D_Cache=[]
if options.D_Cache!= "":
	D_Cache= options.D_Cache.split(',')
#read TLB sizes
TLB_Size=[]
if options.TLB_Size!= "":
	TLB_Size= options.TLB_Size.split(',')

#define voltage domains based on values entered by user
VoltageDomainList= [VoltageDomain(voltage =Volts[i]) for i in xrange(np)]

#define clock domains based on values entered by user
ClockDomainList=
[SrcClockDomain(clock=Clocks[i],voltage_domain=VoltageDomainList[i]) for i
in xrange(np)]

#define L1 Instruction Cache list
L1ICacheList=[O3_ARM_v7a_ICache(size=I_Cache[i]) for i in xrange(np)]
#define L1 Data Cache list
L1DCacheList=[O3_ARM_v7a_DCache(size=D_Cache[i]) for i in xrange(np)]

#define L2 TLB List
ArmTLBList=[O3_ARM_v7aWalkCache(size=TLB_Size[i]) for i in xrange(np)]

#assign clock domains to cores
mycpu = [O3_ARM_v7a_3(cpu_id=i,clk_domain=ClockDomainList[i])  for i in
xrange(np)]

i=0;
for cpu in mycpu:# adding caches to each core
	cpu.addTwoLevelCacheHierarchy(L1ICacheList[i],L1DCacheList[i],ArmTLBList[i])
	i=i+1
#Craete the system with simple memory
mysystem = System(
	cpu=mycpu,
	mem_ranges = [AddrRange(options.mem_size)],
	cache_line_size = options.cacheline_size,
	physmem = SimpleMemory(),
	membus = CoherentXBar(),
	mem_mode = 'timing'
		)

#connect slave port of membus with system port
mysystem.system_port=mysystem.membus.slave
#connect master port of membus with port of physical memory
mysystem.physmem.port=mysystem.membus.master

# create the interrupt controller
for cpu in mycpu:
	cpu.createInterruptController()
	cpu.connectAllPorts(mysystem.membus)

# Create a top-level voltage domain
mysystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
# Create a source clock for the system and set the clock period
mysystem.clk_domain = SrcClockDomain(clock =
options.sys_clock,voltage_domain = mysystem.voltage_domain)

# Sanity check
if options.fastmem:
    if CPUClass != AtomicSimpleCPU:
        fatal("Fastmem can only be used with atomic CPU!")
    if (options.caches or options.l2cache):
        fatal("You cannot use fastmem in combination with caches!")

if options.simpoint_profile:
    if not options.fastmem:
        # Atomic CPU checked with fastmem option already
        fatal("SimPoint generation should be done with atomic cpu and
fastmem")
    if np > 1:
        fatal("SimPoint generation not supported with more than one CPUs")

for i in xrange(np):
    if options.smt:
        mysystem.cpu[i].workload = multiprocesses
    elif len(multiprocesses) == 1:
        mysystem.cpu[i].workload = multiprocesses[0]
    else:
        mysystem.cpu[i].workload = multiprocesses[i]

    if options.fastmem:
        mysystem.cpu[i].fastmem = True

    if options.simpoint_profile:
        mysystem.cpu[i].addSimPointProbe(options.simpoint_interval)

    if options.checker:
        mysystem.cpu[i].addCheckerCpu()

    mysystem.cpu[i].createThreads()

root = Root(full_system = False, system = mysystem)
# instantiate configuration
m5.instantiate()
exit_event = m5.simulate()
print 'Exiting  <at>  tick', m5.curTick(), 'because', exit_event.getCause()
---------------------------------------------------------------

and following is the COMMAND and the ERROR which I get for this script

gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Oct  1 2014 19:17:30
gem5 started Oct 21 2014 16:21:08
gem5 executing on naveed-desktop
command line: build/ARM/gem5.opt
configs/MyScripts/Stage0_PN_Mthreading_try3.py -n 3 -c
dijkstra_parallel_squeue_obj --options=3 --I_Cache=32MB,32MB,32MB
--D_Cache=32MB,32MB,32MB --TLB_Size=64MB,64MB,64MB --Volts=1mV,1mV,1mV
--Clocks=1GHz,1GHz,1GHz
Global frequency set at 1000000000000 ticks per second
      0: system.cpu0.isa: ISA system set to: 0 0xb5a0200
      0: system.cpu1.isa: ISA system set to: 0 0xb5a0200
      0: system.cpu2.isa: ISA system set to: 0 0xb5a0200
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
0: system.remote_gdb.listener: listening for remote gdb #1 on port 7001
0: system.remote_gdb.listener: listening for remote gdb #2 on port 7002
info: Entering event queue  <at>  0.  Starting simulation...
info: Increasing stack size by one page.
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
warn: User mode does not have SPSR
gem5.opt: build/ARM/cpu/o3/rename_map.hh:120: PhysRegIndex
SimpleRenameMap::lookup(SimpleRenameMap::RegIndex) const: Assertion
`arch_reg < map.size()' failed.
Program aborted at tick 194029000
Aborted (core dumped)

Please guide me guys.....Thanks to you all.

Best Regards
Naveed Ul Mustafa

Enabling --dual for ARM on Gem5

Has anybody got the --dual args working for ARM on gem5? When I try to run
build/ARM/gem5.opt configs/example/fs.py
--disk-image=/home/ram/full_system_images/arm-system-2011-08/disks/arm-ubuntu.img
--kernel=/home/ram/Desktop/linux-2.6.38.1/vmlinux --mem-size=256MB
--script=configs/boot/temp.rcS --dual

I get the error output:
Global frequency set at 1000000000000 ticks per second
Error in unproxying port 'int0' of etherlink
Traceback (most recent call last):
  File "<string>", line 1, in <module>
  File "/home/ram/Downloads/gem5-stable-aaf017eaad7d/src/python/m5/main.py",
line 388, in main
  File "configs/example/fs.py", line 245, in <module>
    Simulation.run(options, root, test_sys, FutureClass)
  File "/home/ram/gem5/configs/common/Simulation.py", line 415, in run
    m5.instantiate(checkpoint_dir)
  File
"/home/ram/Downloads/gem5-stable-aaf017eaad7d/src/python/m5/simulate.py",
line 87, in instantiate
  File
"/home/ram/Downloads/gem5-stable-aaf017eaad7d/src/python/m5/SimObject.py",
line 926, in unproxyParams
  File
"/home/ram/Downloads/gem5-stable-aaf017eaad7d/src/python/m5/params.py", line
1451, in unproxy
  File
"/home/ram/Downloads/gem5-stable-aaf017eaad7d/src/python/m5/proxy.py", line
89, in unproxy
  File
"/home/ram/Downloads/gem5-stable-aaf017eaad7d/src/python/m5/proxy.py", line
164, in find
  File
"/home/ram/Downloads/gem5-stable-aaf017eaad7d/src/python/m5/SimObject.py",
line 734, in __getattr__
AttributeError: object 'RealViewPBX' has no attribute 'ethernet'
  (C++ object is not yet constructed, so wrapped C++ methods are unavailable.)

If I run that exact command without the --dual, it works perfectly. 

My ultimate goal is to get two instances of gem5 to communicate. Can anybody
help?

Regards 

About Page Table fault


Hi guys,

I am desperate need of your help. I am trying to solve this problem for
last 2 days but could not solve it. I have two questions.

1) I sucessfully ran the "hello world" program on my simulation script
(with one processor), then I change the workload to run a queens benchmark
for 12x12, and it was also sucessfull. However, when I try to run the
dijkstra benchmark using exactly  same configuration script, I get the
Page Table fault( as given below.)

--------------------------------------
build/ARM/gem5.opt --stats-file=A7Freq1000MHz
configs/MyScripts/Stage0_PN.py --num_cpus=1 --Volts=1mV --Clocks=1000MHz
--I_Cache=32kB --D_Cache=32kB --TLB_Size=512kB
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Oct  1 2014 19:17:30
gem5 started Oct 20 2014 21:40:03
gem5 executing on naveed-desktop
command line: build/ARM/gem5.opt --stats-file=A7Freq1000MHz
configs/MyScripts/Stage0_PN.py --num_cpus=1 --Volts=1mV --Clocks=1000MHz
--I_Cache=32kB --D_Cache=32kB --TLB_Size=512kB
Global frequency set at 1000000000000 ticks per second
      0: system.cpu.isa: ISA system set to: 0 0xb892200
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
info: Entering event queue  <at>  0.  Starting simulation...
info: Increasing stack size by one page.
Usage: dijkstra <filename>
Only supports matrix size is #define'd.
panic: Page table fault when accessing virtual address 0
  <at>  tick 20109000
[invoke:build/ARM/sim/faults.cc, line 70]
Memory Usage: 199012 KBytes
Program aborted at tick 20109000
Aborted (core dumped)
------------------------------------------------

My second question is that how can I distribute the workload (e.g single
dijkstra exe) on dual core system? Does the following piece of code
distribute the workload (e.g single dijkstra program execution) on 2/more
processors ?

root.workload = LiveProcess(cmd= '-o Mibench/input.dat >
Mibench/output_small.dat', executable ='Mibench/dijkstra_small_obj')

for cpu in mycpu:
	cpu.workload=root.workload

I am pasting here the full content of my script file. Thanks you all in
advance.

------------------------------------------------
import optparse
import sys
import m5
from m5.defines import buildEnv
from m5.objects import *
from m5.util import addToPath, fatal
addToPath('../common')
from FSConfig import *
from SysPaths import *
from Benchmarks import *
import Simulation
import CacheConfig
import MemConfig
from Caches import *
import Options
from O3_ARM_v7a import *

parser = optparse.OptionParser()
parser.add_option("--num_cpus", type="int")#adding a new option for script
parser.add_option("--I_Cache",type="string")
parser.add_option("--D_Cache",type="string")
parser.add_option("--TLB_Size",type="string")
parser.add_option("--Volts",type="string")
parser.add_option("--Clocks",type="string")
Options.addCommonOptions(parser)
Options.addFSOptions(parser)
(options, args) = parser.parse_args()

np = options.num_cpus#reading number of processors input by user
#read Voltage domains
Volts= []
if options.Volts!= "":
       Volts = options.Volts.split(',')
#read clock domains
Clocks=[]
if options.Clocks!= "":
	Clocks= options.Clocks.split(',')
#read I Cache sizes
I_Cache=[]
if options.I_Cache!= "":
	I_Cache= options.I_Cache.split(',')
#read D Cache sizes
D_Cache=[]
if options.D_Cache!= "":
	D_Cache= options.D_Cache.split(',')
#read TLB sizes
TLB_Size=[]
if options.TLB_Size!= "":
	TLB_Size= options.TLB_Size.split(',')

#define voltage domains based on values entered by user
VoltageDomainList= [VoltageDomain(voltage =Volts[i]) for i in xrange(np)]
#define clock domains based on values entered by user
ClockDomainList=
[SrcClockDomain(clock=Clocks[i],voltage_domain=VoltageDomainList[i]) for i
in xrange(np)]

#define L1 Instruction Cache list
L1ICacheList=[O3_ARM_v7a_ICache(size=I_Cache[i]) for i in xrange(np)]
#define L1 Data Cache list
L1DCacheList=[O3_ARM_v7a_DCache(size=D_Cache[i]) for i in xrange(np)]

#define L2 TLB List
ArmTLBList=[O3_ARM_v7aWalkCache(size=TLB_Size[i]) for i in xrange(np)]

#define np number of cores
mycpu = [O3_ARM_v7a_3(cpu_id=i,clk_domain=ClockDomainList[i])  for i in
xrange(np)]

i=0;
for cpu in mycpu:# adding caches to each core
	cpu.addTwoLevelCacheHierarchy(L1ICacheList[i],L1DCacheList[i],ArmTLBList[i])
	i=i+1
#Craete the system with simple memory
mysystem = System(
	cpu=mycpu,
	cache_line_size = options.cacheline_size,
	physmem = SimpleMemory(),
	membus = CoherentXBar(),
	mem_mode = 'timing'
		)

#connect slave port of membus with system port
mysystem.system_port=mysystem.membus.slave
#connect master port of membus with port of physical memory
mysystem.physmem.port=mysystem.membus.master

# create the interrupt controller
for cpu in mycpu:
	cpu.createInterruptController()
	cpu.connectAllPorts(mysystem.membus)

# Create a top-level voltage domain
mysystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
# Create a source clock for the system and set the clock period
mysystem.clk_domain = SrcClockDomain(clock =
options.sys_clock,voltage_domain = mysystem.voltage_domain)

#declare the root
root = Root(full_system=False,system = mysystem)

#assign the work load to the system
#root.workload = LiveProcess(cmd= 'hello', executable
='/home/naveed/Desktop/gem5-dev/tests/test-progs/hello/bin/arm/linux/hello')
#root.workload = LiveProcess(cmd= '', executable
='/home/naveed/Desktop/gem5-dev/queens12_obj')
root.workload = LiveProcess(cmd= '-o Mibench/input.dat >
Mibench/output_small.dat', executable ='Mibench/dijkstra_small_obj')

for cpu in mycpu:
	cpu.workload=root.workload

# instantiate configuration
m5.instantiate()

exit_event = m5.simulate()
print 'Exiting  <at>  tick', m5.curTick(), 'because', exit_event.getCause()
------------------------------------------------

Naveed Ul Mustafa

Full System X86 Dual mode checkpoint-restore problem

Hi all,

I'm running a simple client-server application on FS dual mode. I start server on drive_sys and take a checkpoint. The problem is that if I restore from the checkpoint with detail O3 cpu, client on test_sys cannot connect to server and prints out there is no server running on drive_sys. However if I restore with simple atomic cpu I can establish connection between client and server.

Any idea why I lose my connection if restore with O3 cpu?!

Thank you,
Mohammad
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Nitin Rathi via gem5-users | 19 Oct 00:48 2014

Running TPC-H benchmark on gem5

Hello,

I am a graduate student at University of South Florida. I recently started using gem5 simulator and was able to run various benchmarks like PARSEC. But currently I am facing difficulty to run TPC-H benchmark on gem5. I would like to know that if anyone has worked on it and are willing to help me.

Thanks in Advance.

Nitin Rathi
Department of Computer Science,
University of South Florida, Tampa. 
nitinr <at> mail.usf.edu
(352) 870-9493
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Getting trace statements related to benchmarks only

Hi,

I placed SPLASH benchmarks inside the disk image, and now I'm interested in getting DPRINTF traces related to cache replacement behavior only while running these benchmarks. what would be a good way to proceed with this requirement? 

the most basic way is to run the gem5.debug binary and get the tick right before executing a benchmark and then filtering the trace file, but that takes a very long time with debugging. Is there a better/faster way to do this?

Thank your for your time,
Mohammad
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Patrick L. via gem5-users | 17 Oct 18:11 2014

Turn Off Scientific Notation in Histogram Stats Printing

I am collecting some histogram data that is getting printed out to 
stats.txt. The problem I am having is that the buckets are getting printed 
out in scientific notation. I have been looking around in the code and 
documentation and it isn't immediately obvious to me how to change that. 
Does anyone know how to change this?

Thanks,
Patrick

Heterogeneous system in FS mode

Hi all

I'm trying to create a heterogeneous system with 1 2-way 2 4-way and 1 8-way core in arm-detailed FS mode.

Following is the change I made in fs.py:

cpus = []

for i in xrange(4):
    if(i == 0):
           cpus.append(2-way)
    elif (i == 1):
           cpus.append(4-way)
    elif (i == 2):
           cpus.append(4-way)
    elif (i == 3):
           cpus.append(4-way)

test_sys.cpu = cpus

However when I'm trying to create a check point, I'm getting the following error:
"break event panic triggered"

Is there something I'm missing?

Thanks

V Vanchinathan
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Gmane