Anny via gem5-users | 18 Dec 17:54 2014

Benchmarks on gem5

Hi all,

Can you give me a description of what benchmarks do in gem5.

Regards,

Printing All stats even if they are 0

Hello again :)
I am using Gem5 with the parsec Benchmarks. When I am using a small intervall for dumping, some stats are getting zero and will not be printet in the stat file. 

After some googling I found out, that there is a function named "prereq" which prevent stats from being printed out if some prerequired ones are 0. 
But I dont find the correct line for the l2 stats. So I am not able to enable "full printing" of the system.l2.ReadReq_misses::total key for example.  

Is there a way to print generally all values, even if they are 0 ?

Thanks in anticipation,
Chris
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via gem5-users | 18 Dec 07:56 2014

problems when running gem5 in FS mode with the latest kernels

Hi everyone

I’m trying to run gem5 in FS mode with the latest kernels and images downloaded from the website.I use the kernels and images in ARM Full-System Files.

The command line I use is as follows:

./build/ARM/gem5.opt configs/example/fs.py --kernel=..path../vmlinux.aarch32.ll_20131205.0-gem5 --disk=..path../linux-aarch32-ael.img --mem-size=512MB --machine-type=Vexpress_EMM --script=./configs/boot/queens.rcS

But when I run it,it shows errors,the result is as follows:

Info:Using bootloader at address 0x10

Info:Using kernel entry physical address at 0x80008000

Warn:Kernel supports device tree,but no DTB file specified

****REAL SIMULATION****

Fatal:Unable to find destination for addr 0x1c000060 on bus system.iobus <at> tick 278715500

[findport:build/ARM/mem/bus.cc,line 353]

Memory Usage:727072 Kbytes

Program aborted at tick 278715500

已放弃(核心已转储)

I find the error information in the file mentioned above.But I don’t know how to solve it.I would appreciate any advice how to solve the problem above and run in FS mode with the latest kernels.

Thanks

 

 

Ran Luo

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Milad Milad via gem5-users | 18 Dec 00:55 2014

How to run DVFS on ARM for 16 cores? how to run DVFS on alpha?

Hi to All,

I am working with the released version of DVFS on Gem5, based on ARM architecture
however I have some questions about it. 

1- how can I change the dtb file so that it would be possible to run DVFS on more than 4 cores (based on the guide document released by gem5 people, dtbs are just for 1 and 2 and 4 cores)

2- how can I use the cpufreq governer inside the OS on the simulated machin, because the OS cant recognize this command and needs apt-get install which does not work
(how can I change the frequency based on my desire frequency?)


3- is there any way to run a DVFS on ALPHA arch?

Regards,
Milad
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Full System Simulation with ARM

I'm having problems running a full system simulation with the ARM processor.
I'm  using  the precompiled disk images from the gem5 website.

Firstly, I tried using the 32-bit version. Then I get the following error:

[lecco <at> shredder gem5-stable]$ ./build/ARM/gem5.opt
configs/example/fs.py --cpu-type=timing --caches --mem-size=256MB
--disk-image=/user/lecco/no_save/Downloads/arm_system/disks/aarch32-ubuntu-natty-headless.img
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Dec 16 2014 16:47:21
gem5 started Dec 17 2014 13:47:18
gem5 executing on shredder.net.ida
command line: ./build/ARM/gem5.opt configs/example/fs.py
--cpu-type=timing --caches --mem-size=256MB
--disk-image=/user/lecco/no_save/Downloads/arm_system/disks/aarch32-ubuntu-natty-headless.img
Global frequency set at 1000000000000 ticks per second
info: kernel located at:
/user/lecco/no_save/Downloads/arm_system/binaries/vmlinux.aarch32.ll_20131205.0-gem5
Listening for system connection on port 5900
Listening for system connection on port 3456
      0: system.cpu.isa: ISA system set to: 0x3ca3080 0x3ca3080
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
info: Using bootloader at address 0x80000000
info: Using kernel entry physical address at 0x8000
warn: Kernel supports device tree, but no DTB file specified
**** REAL SIMULATION ****
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue  <at>  0.  Starting simulation...
warn: Not doing anything for miscreg ACTLR
warn: Not doing anything for write of miscreg ACTLR
warn: The clidr register always reports 0 caches.
warn: clidr LoUIS field of 0b001 to match current ARM implementations.
warn: The csselr register isn't implemented.
fatal: Unable to find destination for addr 0x1c090018 on system.iobus
  <at>  tick 1254122000
[findPort:build/ARM/mem/xbar.cc, line 345]
Memory Usage: 610700 KBytes
Program aborted at tick 1254122000
Aborted (core dumped)

Then, I tried the 64-bit version. This time a different problem... but
I still dont know how to fix it:

[lecco <at> shredder gem5-stable]$ ./build/ARM/gem5.opt
configs/example/fs.py --mem-size=256MB
--disk-image=/user/lecco/no_save/Downloads/arm_system/disks/aarch64-ubuntu-trusty-headless.img
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Dec 16 2014 16:47:21
gem5 started Dec 17 2014 13:43:14
gem5 executing on shredder.net.ida
command line: ./build/ARM/gem5.opt configs/example/fs.py
--mem-size=256MB
--disk-image=/user/lecco/no_save/Downloads/arm_system/disks/aarch64-ubuntu-trusty-headless.img
Global frequency set at 1000000000000 ticks per second
info: kernel located at:
/user/lecco/no_save/Downloads/arm_system/binaries/vmlinux.aarch64.20140821
Listening for system connection on port 5900
Listening for system connection on port 3456
      0: system.cpu.isa: ISA system set to: 0x485bab0 0x485bab0
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
info: Using bootloader at address 0x80000000
info: Using kernel entry physical address at 0x80000
warn: Kernel supports device tree, but no DTB file specified
warn: Kernel supports generic PCI host but PCI Config offsets
configured for legacy. Set pci_cfg_gen_offsets to True
warn: Kernel supports generic PCI host but PCI IO base is set to 0.
Set pci_io_base to the start of PCI IO space
**** REAL SIMULATION ****
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue  <at>  0.  Starting simulation...
warn: Device system.membus.badaddr_responder accessed by write to
address 0xffffffff size=1 data=0
gem5.opt: build/ARM/cpu/simple/atomic.cc:453: virtual Fault
AtomicSimpleCPU::writeMem(uint8_t*, unsigned int, Addr, unsigned int,
uint64_t*): Assertion `!pkt.isError()' failed.
Program aborted at tick 6832000
Aborted (core dumped)

According to the website, this setup is supposed to work... Do you
guys know what is wrong?
babak aghaei via gem5-users | 16 Dec 20:22 2014

modifying the components of gem5

Dear Andreas Hansson
I prey this msg find you in complete health and full happiness state.
I have been studying gem5 simulator for last 10 month ago. but now because information starvation i am stopping my research.  if possible plz guide me in following issues:
1. when i want to modify a file in gem5 component, how i can see the result in stats.txt? my mean is what i must be do after modifying this file until see the result.
2. my main studies are on faults and fault injection to network on chip. in continue my studies, i want know about router idle time. I want know weather the router have idle time on not, if yes where i can realize that.
3. I want to modify the router files(which file must be change from .cc .h .py)?
4. if i wanna modify the flit structure what i must be do?
sry if my questions are heterogeneous. i am really confused.
i wait for kindly response..
Best
 
---------------------------------------------------------------
Babak Aghaei
Ph.D candidate
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Anny via gem5-users | 16 Dec 12:04 2014

simObject clocks and global simulation clock

Hi all,

I have a question about clocks on gem5. In gem5, it seems that there is a
global simulation clock and every simObject has a clock domain. The eventq
is sorted in time. When two objects with two different clocks schedule two
events on eventq, how the order is determined since the two objects have
different clocks? Are all objects synchronious? it seems that everything in
the system is based of one clock (global simulation clock)? It is binding.

Best, 
Anny.
Zhenman Fang via gem5-users | 16 Dec 06:09 2014

X86 with large memory and ruby

Dear all,

I tried to run X86 with 4GB memory and ruby and encountered a problem when restoring from the checkpoint. It's OK to do checkpoint (no ruby) though.

The problem is: it had a virtual address "0x13f635080" which could not be translated into the physical address correctly. Actually it translated into the same physical address as "0x13f635080". Then an assertion will fail later when it tries to find the corresponding cache tag. The assertion happened at "build/X86/mem/ruby/structures/DirectoryMemory.cc:121: AbstractEntry* DirectoryMemory::lookup(PhysAddress): Assertion `idx < m_num_entries' failed".

Anyone can help? Thanks a lot.

The changeset for gem5-dev is 10560:dd04eb06ad42.

The command line I use: ./build/X86/gem5.opt --debug-flags=RubyCache configs/example/fs.py --restore-with-cpu=timing -n 1 --mem-size=4GB --ruby --garnet=fixed --topology=Mesh --checkpoint-dir=ckpt-1core -r 1

Detailed trace as below:

warn: Physical memory size specified is 4GB which is greater than 3GB.  Twice the number of memory controllers would be created.
Global frequency set at 1000000000000 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (4096 Mbytes)
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (1024 Mbytes)
info: kernel located at: /space/scratch/zhenman/parade/binaries/x86_64-vmlinux-2.6.22.9.smp
Listening for com_1 connection on port 3458
      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7002
warn: Reading current count from inactive timer.
**** REAL SIMULATION ****
info: Entering event queue <at> 5234045298000.  Starting simulation...
5234045300000: system.ruby.l1_cntrl0.L1Dcache: No tag match for address: [0x13f635080, line 0x13f635080]
5234045300000: system.ruby.l1_cntrl0.L1Icache: No tag match for address: [0x13f635080, line 0x13f635080]
5234045300000: system.ruby.l1_cntrl0.L1Icache: address: [0x13f635080, line 0x13f635080]
5234045300000: system.ruby.l1_cntrl0.L1Icache: Allocate clearing lock for addr: [0x13f635080, line 0x13f635080]
5234045300000: system.ruby.l1_cntrl0.L1Dcache: No tag match for address: [0x13f635080, line 0x13f635080]
5234045305000: system.ruby.l2_cntrl0.L2cache: No tag match for address: [0x13f635080, line 0x13f635080]
5234045305000: system.ruby.l2_cntrl0.L2cache: address: [0x13f635080, line 0x13f635080]
5234045305000: system.ruby.l2_cntrl0.L2cache: Allocate clearing lock for addr: [0x13f635080, line 0x13f635080]
5234045310000: system.ruby.dir_cntrl0.directory: Looking up address: [0x13f635080, line 0x13f635080]
gem5.opt: build/X86/mem/ruby/structures/DirectoryMemory.cc:121: AbstractEntry* DirectoryMemory::lookup(PhysAddress): Assertion `idx < m_num_entries' failed.

Program received signal SIGABRT, Aborted.
0x000000371c832635 in raise () from /lib64/libc.so.6
Missing separate debuginfos, use: debuginfo-install glibc-2.12-1.132.el6_5.4.x86_64 gperftools-libs-2.0-11.el6.3.x86_64 keyutils-libs-1.4-4.el6.x86_64 krb5-libs-1.10.3-15.el6_5.1.x86_64 libcom_err-1.41.12-18.el6_5.1.x86_64 libselinux-2.0.94-5.3.el6_4.1.x86_64 libunwind-1.1-2.el6.x86_64 openssl-1.0.1e-16.el6_5.15.x86_64 python-libs-2.6.6-52.el6.x86_64 zlib-1.2.3-29.el6.x86_64
(gdb) bt
#0  0x000000371c832635 in raise () from /lib64/libc.so.6
#1  0x000000371c833e15 in abort () from /lib64/libc.so.6
#2  0x000000371c82b75e in __assert_fail_base () from /lib64/libc.so.6
#3  0x000000371c82b820 in __assert_fail () from /lib64/libc.so.6
#4  0x00000000005ef76b in DirectoryMemory::lookup(Address) () at build/X86/mem/ruby/structures/DirectoryMemory.cc:121
#5  0x000000000055efe5 in Directory_Controller::getDirectoryEntry(Address const&) () at build/X86/mem/protocol/Directory_Controller.cc:670
#6  0x000000000055f0a3 in Directory_Controller::getState(Directory_TBE*, Address const&) () at build/X86/mem/protocol/Directory_Controller.cc:687
#7  0x0000000000564dab in Directory_Controller::doTransition(Directory_Event, Directory_TBE*, Address) () at build/X86/mem/protocol/Directory_Transitions.cc:27
#8  0x0000000000567b1a in Directory_Controller::wakeup() () at build/X86/mem/protocol/Directory_Wakeup.cc:54
#9  0x000000000080adb1 in EventQueue::serviceOne() () at build/X86/sim/eventq.cc:228
#10 0x0000000000827980 in doSimLoop(EventQueue*) () at build/X86/sim/simulate.cc:195
#11 0x0000000000827f94 in simulate(unsigned long) () at build/X86/sim/simulate.cc:127
#12 0x000000000044366c in _wrap_simulate () at build/X86/python/swig/event_wrap.cc:5499
#13 0x000000371f8d55c6 in PyEval_EvalFrameEx () from /usr/lib64/libpython2.6.so.1.0
#14 0x000000371f8d7657 in PyEval_EvalCodeEx () from /usr/lib64/libpython2.6.so.1.0
#15 0x000000371f8d5aa4 in PyEval_EvalFrameEx () from /usr/lib64/libpython2.6.so.1.0
#16 0x000000371f8d6b8f in PyEval_EvalFrameEx () from /usr/lib64/libpython2.6.so.1.0
#17 0x000000371f8d6b8f in PyEval_EvalFrameEx () from /usr/lib64/libpython2.6.so.1.0
#18 0x000000371f8d7657 in PyEval_EvalCodeEx () from /usr/lib64/libpython2.6.so.1.0
#19 0x000000371f8d7732 in PyEval_EvalCode () from /usr/lib64/libpython2.6.so.1.0
#20 0x000000371f8d5c92 in PyEval_EvalFrameEx () from /usr/lib64/libpython2.6.so.1.0
#21 0x000000371f8d7657 in PyEval_EvalCodeEx () from /usr/lib64/libpython2.6.so.1.0
#22 0x000000371f8d5aa4 in PyEval_EvalFrameEx () from /usr/lib64/libpython2.6.so.1.0
#23 0x000000371f8d7657 in PyEval_EvalCodeEx () from /usr/lib64/libpython2.6.so.1.0
#24 0x000000371f8d7732 in PyEval_EvalCode () from /usr/lib64/libpython2.6.so.1.0
#25 0x000000371f8f1bac in ?? () from /usr/lib64/libpython2.6.so.1.0
#26 0x000000371f8f1dba in PyRun_StringFlags () from /usr/lib64/libpython2.6.so.1.0
#27 0x0000000000811fef in m5Main(int, char**) () at build/X86/sim/init.cc:221
#28 0x000000000041a4b3 in main () at build/X86/sim/main.cc:58

Thanks,
Zhenman Fang
Postdoc, CS, UCLA
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k h via gem5-users | 14 Dec 15:30 2014

compression

hello
I am trying to change the cache structure (L2) .
I want to add a data compressor.
can someone help me?
How can I do it?
thanks
Guru Prasad via gem5-users | 12 Dec 21:13 2014

Debugging Simulated Code - "Remote 'g' packet is too long"

I followed the instructions given here to debug simulated code.
I run into the following issue with gdb-7.8.1.

(gdb) set remote Z-packet on
(gdb) set tdesc filename features/arm-with-neon.xml
(gdb) symbol-file linux-linaro-gem5/vmlinux
Reading symbols from linux-linaro-gem5/vmlinux...done.
(gdb) target remote localhost:7000
Remote debugging using localhost:7000
Remote 'g' packet reply is too long: 7d3cc510e0080000000000884833608000c0648000c064800039698010ef6d806a400080f0c00f410000000000000000f8b60180ec3260807480008010336080d30100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

Does anyone know how to resolve this?

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Implementing a perfect cache

Hi,

I'm trying to use gem5 to simulate a perfect cache, where we always have 
a hit. One way I could go about this is by moving the main memory to the 
level of the L1s and change its access latency, but what I eventually 
would like to do is always hit on a given set of memory locations (to 
get idealised figures for optimising away those specific accesses from 
lower level memory) and have everything else go through the real cache 
hierarchy.

I'm having trouble getting this to work; one way which was suggested to 
me was to hack in a functional access to the address before the true 
timing access, but since functional accesses don't change any state this 
causes nothing to actually happen. Similarly, forwarding the result of 
that access to the timed access function on a miss, instead of doing the 
actual timed access to lower level caches, causes gem5 to go into an 
infinite loop waiting on a real reply.

Has anyone implemented anything like this using gem5, and if so, do you 
have any pointers?

Thanks,
Sam

Gmane