Re: gem5-users Digest, Vol 96, Issue 17

Hello Senni Sophianne,

To configure gem5 according to parameters mentioned in O3_ARM_v7a.py file you need to first type on the command line :

build/ARM/gem5.opt   configs/common/O3_ARM_v7a.py

and then once the executable is configured with the parameters in O3_ARM_v7a.py you give the command line options as you mentioned in the mail.


On Wed, Jul 23, 2014 at 6:00 PM, via gem5-users <gem5-users <at> gem5.org> wrote:
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Today's Topics:

   1. Compile Linux kernel v3 for gem5 FS (saber nabavi via gem5-users)
   2. Re: Compile Linux kernel v3 for gem5 FS
      (Anthony Gutierrez via gem5-users)
   3. Re: Compile Linux kernel v3 for gem5 FS (Zi Yan via gem5-users)
   4. AttributeError when creating own configuration
      (Weber, Fabian via gem5-users)
   5. Cache configuration of arm_detailed
      (senni sophiane via gem5-users)


----------------------------------------------------------------------

Message: 1
Date: Tue, 22 Jul 2014 22:55:49 +0430
From: saber nabavi via gem5-users <gem5-users <at> gem5.org>
To: gem5-users <at> gem5.org
Subject: [gem5-users] Compile Linux kernel v3 for gem5 FS
Message-ID:
        <CAP6Eee-LjrgLBiVmof0+pKG+rgd3H3kTmNZc1rLfGojBzU9gDg <at> mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"

Hi,
I was wondering if I could compile and use linux kernel version 3 or above
with gem5. I mean is it compatible with 2.6.* or will gem5 patches work
with it?

Saber.
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Message: 2
Date: Tue, 22 Jul 2014 14:29:08 -0400
From: Anthony Gutierrez via gem5-users <gem5-users <at> gem5.org>
To: gem5 users mailing list <gem5-users <at> gem5.org>
Subject: Re: [gem5-users] Compile Linux kernel v3 for gem5 FS
Message-ID:
        <CAEQEbpT4qG+OnmAXL+MLeF1rTS1EE16ykFxOZcf_2QJqgrK_Ug <at> mail.gmail.com>
Content-Type: text/plain; charset="utf-8"

For ARM you definitely can. Use the patch and kernel config contained here:

http://www.gem5.org/dist/current/arm/vmlinux-emm-pcie-3.3.tar.bz2

And the kernel source here:

http://www.gem5.org/dist/current/arm/linux-arm-arch.tar.bz2


Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier


On Tue, Jul 22, 2014 at 2:25 PM, saber nabavi via gem5-users <
gem5-users <at> gem5.org> wrote:

> Hi,
> I was wondering if I could compile and use linux kernel version 3 or above
> with gem5. I mean is it compatible with 2.6.* or will gem5 patches work
> with it?
>
> Saber.
>
> _______________________________________________
> gem5-users mailing list
> gem5-users <at> gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
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Message: 3
Date: Tue, 22 Jul 2014 14:58:49 -0400
From: Zi Yan via gem5-users <gem5-users <at> gem5.org>
To: "gem5 users mailing list" <gem5-users <at> gem5.org>
Subject: Re: [gem5-users] Compile Linux kernel v3 for gem5 FS
Message-ID: <A2F0F75A-BDEA-4CC6-9E78-CB4E5F7C3380 <at> gmail.com>

How about DTB(device tree blob) file? Do we need a DTB file for
kernel running on gem5-ARM?

Thanks.

--
Best Regards
Yan Zi

On 22 Jul 2014, at 14:29, Anthony Gutierrez via gem5-users wrote:

> For ARM you definitely can. Use the patch and kernel config contained here:
>
> http://www.gem5.org/dist/current/arm/vmlinux-emm-pcie-3.3.tar.bz2
>
> And the kernel source here:
>
> http://www.gem5.org/dist/current/arm/linux-arm-arch.tar.bz2
>
>
> Anthony Gutierrez
> http://web.eecs.umich.edu/~atgutier
>
>
> On Tue, Jul 22, 2014 at 2:25 PM, saber nabavi via gem5-users <
> gem5-users <at> gem5.org> wrote:
>
>> Hi,
>> I was wondering if I could compile and use linux kernel version 3 or above
>> with gem5. I mean is it compatible with 2.6.* or will gem5 patches work
>> with it?
>>
>> Saber.
>>
>> _______________________________________________
>> gem5-users mailing list
>> gem5-users <at> gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
> _______________________________________________
> gem5-users mailing list
> gem5-users <at> gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


------------------------------

Message: 4
Date: Tue, 22 Jul 2014 21:10:51 +0000
From: "Weber, Fabian via gem5-users" <gem5-users <at> gem5.org>
To: "gem5-users <at> gem5.org" <gem5-users <at> gem5.org>
Subject: [gem5-users] AttributeError when creating own configuration
Message-ID:
        <A837B72F7988834E815986A038ABDD1C11EEEAAC <at> mail4.ad.uni-siegen.de>
Content-Type: text/plain; charset="iso-8859-1"

Hi everyone,

I've a problem creating an own configuration. Starting from the ruby_network_test.py I copied this configuration file and the network_test folder which includes networktest.cc/hh and NetworkTest.py. Then I renamed them to tt_network ... (and also the class and methods in the source file).

It compiles successfully but does not execute:

Traceback (most recent call last):
  File "<string>", line 1, in <module>
  File "/gem5/src/python/m5/main.py", line 388, in main
    exec filecode in scope
  File "configs/example/ruby_tt_network_test.py", line 123, in <module>
    for ruby_port in system.ruby._cpu_ruby_ports:
  File "/gem5/src/python/m5/SimObject.py", line 736, in __getattr__
    raise AttributeError, err_string
AttributeError: object 'RubySystem' has no attribute '_cpu_ruby_ports'
  (C++ object is not yet constructed, so wrapped C++ methods are unavailable.)

Does somebody knows this error and could explain what I forgot/have to do?

Best regards,
Fabian

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Message: 5
Date: Wed, 23 Jul 2014 11:17:41 +0200
From: senni sophiane via gem5-users <gem5-users <at> gem5.org>
To: gem5 users mailing list <gem5-users <at> gem5.org>
Subject: [gem5-users] Cache configuration of arm_detailed
Message-ID: <53CF7DB5.2060405 <at> gmail.com>
Content-Type: text/plain; charset=ISO-8859-1

Hi all,

When I am using the options --cpu_type=arm_detailed --caches --l2cache
in the command line, the cache configuration of the system is not the
one specified in the O3_ARM_v7a.py file. Instead it is the cache
configuration described in Caches.py
This is the command line I used :

build/ARM/gem5.opt configs/example/fs.py --caches --l2cache
--cpu-type=arm_detailed -n4 -b splash2_fmm


Does someone know what could be the reason ? Am I missing something ?

Thanks for your help.

--
Cordialement / Best Regards

SENNI Sophiane
Ph.D. candidate - Microelectronics
LIRMM - www.lirmm.fr



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End of gem5-users Digest, Vol 96, Issue 17
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Cache configuration of arm_detailed

Hi all,

When I am using the options --cpu_type=arm_detailed --caches --l2cache
in the command line, the cache configuration of the system is not the
one specified in the O3_ARM_v7a.py file. Instead it is the cache
configuration described in Caches.py
This is the command line I used :

build/ARM/gem5.opt configs/example/fs.py --caches --l2cache
--cpu-type=arm_detailed -n4 -b splash2_fmm

Does someone know what could be the reason ? Am I missing something ?

Thanks for your help.

--

-- 
Cordialement / Best Regards

SENNI Sophiane
Ph.D. candidate - Microelectronics
LIRMM - www.lirmm.fr

AttributeError when creating own configuration

Hi everyone,

I've a problem creating an own configuration. Starting from the ruby_network_test.py I copied this configuration file and the network_test folder which includes networktest.cc/hh and NetworkTest.py. Then I renamed them to tt_network ... (and also the class and methods in the source file).

It compiles successfully but does not execute:

Traceback (most recent call last):
  File "<string>", line 1, in <module>
  File "/gem5/src/python/m5/main.py", line 388, in main
    exec filecode in scope
  File "configs/example/ruby_tt_network_test.py", line 123, in <module>
    for ruby_port in system.ruby._cpu_ruby_ports:
  File "/gem5/src/python/m5/SimObject.py", line 736, in __getattr__
    raise AttributeError, err_string
AttributeError: object 'RubySystem' has no attribute '_cpu_ruby_ports'
  (C++ object is not yet constructed, so wrapped C++ methods are unavailable.)

Does somebody knows this error and could explain what I forgot/have to do?

Best regards,
Fabian

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saber nabavi via gem5-users | 22 Jul 20:25 2014

Compile Linux kernel v3 for gem5 FS

Hi,
I was wondering if I could compile and use linux kernel version 3 or above with gem5. I mean is it compatible with 2.6.* or will gem5 patches work with it?

Saber.
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Responding multiple packets from the DRAM

Hi,
  I am making changes to the memory system in dram_ctrl.cc . Once a packet reads a data, I am not responding back immediately - but after I collect few more packets. I am storing them in a separate queue (the dram_pkt is also deleted from the respQueue). Once the separate queue becomes full, I am responding back all the packets at once using
port.schedTimingResp(pkt, curTick() + latency);
latency added accordingly to each packet.
simulate() limit is getting reached very early - & I am guessing its because cpu got stalled waiting for a memory request that never got serviced.

Is the port dropping any packets? How do I overcome this problem?
Any pointer will be of great help

--

thanks&regards
BISWABANDAN
http://www.cse.iitm.ac.in/~biswa/

“We might fall down, but we will never lay down. We might not be the best, but we will beat the best! We might not be at the top, but we will rise.”


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Getting Ideal CPI

Hi Everybody,
For calculating CPI in a changed system, I need to get ideal CPI without memory stall. But I can't increase L1 and L2 caches very much in order to decreasing access time to the memory. So, How can I do it via Gem5?
Thanks,
Sobhan Niknam
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Having multi-ported L1 Cache

I would like to know if it is possible to connect the dcache_port of a CPU to separate ports on L1 Cache in classic memory model.

Currently L1 cache has a single cpu_side port. I wanted to know if the functionality will be correct if I change this to a vector instead and connect each of the CPU dcache_port to this.

Thanks
V Vanchinathan
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Wrong decoding of instructions

I'm trying to execute a binary on ARM gem5 O3CPU model. I made some modification to the code.

Now, some instructions wrongly get encoded as four micro-ops. I'm not sure how I should go about for debugging this problem.

Any help is really appreciated.

Thanks a lot!
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Correlate the gem5's cpu model to a specific core

Hi all,

I would like to model a specific core, for instance a cortex-A15, into
gem5. I never did this kind of work. So, could someone tell me from
where I should start ? I mean which files I have to modify if I want to
match the cpu model of gem5 to a cortex-A15 ?

Thanks for your time.

--

-- 
Cordialement / Best Regards

SENNI Sophiane
Ph.D. candidate - Microelectronics
LIRMM - www.lirmm.fr

How to stats.txt is created in gem5, what are the functions to open, write to and close this file ?

Hi all,

Can you explain clearly for me how the stats.txt is created in gem5 ( e.g what are the functions to open, write to and close this file, ... and when these functions are called when I simulate gem5 and execute a binary file ? ) ?

Thanks advance,
Hien.
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Source address of a node in garnet

Hi All,

I want to know where is specified the source address of a message(packet or  Head flit) which is sent from a particular source node in garnet network. How can I access to the source address?

Thanks in advance for your help.
Mohammad Sadegh Sadeghi
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Gmane