Vanchinathan Venkataramani | 27 May 09:37 2015
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Re: Maximum ARM cores in FS mode

I fixed this problem by using the system files provided in the beginning of this thread and recompiling the dtb file to support 8 cores as stated in:

Thanks

On Mon, May 25, 2015 at 6:52 PM, Vanchinathan Venkataramani <dcsvave <at> nus.edu.sg> wrote:
Hi Tony

Is it possible to run 8 cores on 32 bit ARM?

Thanks

On Sat, May 23, 2015 at 2:24 AM, Gutierrez, Anthony <Anthony.Gutierrez <at> amd.com> wrote:

I thought I updated the system files to have support for 8 cores in aarch64. If you use aarch64 and the system files here: http://www.gem5.org/dist/current/arm/aarch-system-2014-10.tar.xz you

may be able to use 8 cores. If not, you need to build an updated dtb file with support for 8 cores. I have one somewhere and I’ll put it up on the wiki, but I won’t be able to get to it today.

 

-Tony

 

From: gem5-users [mailto:gem5-users-bounces <at> gem5.org] On Behalf Of Vanchinathan Venkataramani
Sent: Friday, May 22, 2015 11:06 AM
To: gem5 users mailing list
Subject: [gem5-users] Maximum ARM cores in FS mode

 

Hi all

 

I found that the maximum number of cores in arm fs mode is four. What do I need to do enable 8 cores?

Thanks a lot in advance.


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Davesh Shingari | 26 May 23:50 2015
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Android + 2GB configuration

Hi Andreas

Is it possible to run Android ICS with more than 256MB RAM?
If yes then which machine type should be used. I tried quite many combinations but every time it gave error. Please help.


--
Have a great day!

Thanks and Warm Regards
Davesh Shingari
Master's in Computer Engineering [EE]
Arizona State University

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冰兲轌地 | 26 May 06:59 2015

about DVFS Futher Experiments in Per-core DVFS

Hi,everyone:

when I was test the DVFS experiments in per-core DVFS,the page is http://www.m5sim.org/Running_gem5#Experimenting_with_DVFS ,there is a sentence I don't know how to do. It is 
  • Change the socket_id to have a separate socket per CPU core
Does anyone konws which file should I modify to change the socket_id ,and how to change the socket_id?
thanks for any help!
Bing Liang
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Vanchinathan Venkataramani | 25 May 12:56 2015
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Re: Maximum ARM cores in FS mode

Hi Tony

Is it possible to run 8 cores on 32 bit ARM?

Thanks

On Mon, May 25, 2015 at 6:52 PM, Vanchinathan Venkataramani <dcsvave <at> nus.edu.sg> wrote:
Hi Tony

Is it possible to run 8 cores on 32 bit ARM?

Thanks

On Sat, May 23, 2015 at 2:24 AM, Gutierrez, Anthony <Anthony.Gutierrez <at> amd.com> wrote:

I thought I updated the system files to have support for 8 cores in aarch64. If you use aarch64 and the system files here: http://www.gem5.org/dist/current/arm/aarch-system-2014-10.tar.xz you

may be able to use 8 cores. If not, you need to build an updated dtb file with support for 8 cores. I have one somewhere and I’ll put it up on the wiki, but I won’t be able to get to it today.

 

-Tony

 

From: gem5-users [mailto:gem5-users-bounces <at> gem5.org] On Behalf Of Vanchinathan Venkataramani
Sent: Friday, May 22, 2015 11:06 AM
To: gem5 users mailing list
Subject: [gem5-users] Maximum ARM cores in FS mode

 

Hi all

 

I found that the maximum number of cores in arm fs mode is four. What do I need to do enable 8 cores?

Thanks a lot in advance.


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Vanchinathan Venkataramani | 25 May 11:46 2015
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Re: Maximum ARM cores in FS mode

Hi Tony

I tried the image you sent in the previous e-mail. However, the dtb file for 8 cores (binaries/vexpress.aarch32.ll_20131205.0-gem5.8cpu.dtb) is not present in it.

Thanks

On Mon, May 25, 2015 at 5:46 PM, Vanchinathan Venkataramani <dcsvave <at> nus.edu.sg> wrote:
Hi Tony

I tried the image you sent in the previous e-mail. However, the dtb file for 8 cores (binaries/vexpress.aarch32.ll_20131205.0-gem5.8cpu.dtb) is not present in it.

On Sat, May 23, 2015 at 2:24 AM, Gutierrez, Anthony <Anthony.Gutierrez <at> amd.com> wrote:

I thought I updated the system files to have support for 8 cores in aarch64. If you use aarch64 and the system files here: http://www.gem5.org/dist/current/arm/aarch-system-2014-10.tar.xz you

may be able to use 8 cores. If not, you need to build an updated dtb file with support for 8 cores. I have one somewhere and I’ll put it up on the wiki, but I won’t be able to get to it today.

 

-Tony

 

From: gem5-users [mailto:gem5-users-bounces <at> gem5.org] On Behalf Of Vanchinathan Venkataramani
Sent: Friday, May 22, 2015 11:06 AM
To: gem5 users mailing list
Subject: [gem5-users] Maximum ARM cores in FS mode

 

Hi all

 

I found that the maximum number of cores in arm fs mode is four. What do I need to do enable 8 cores?

Thanks a lot in advance.


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http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


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Ayaz Akram | 25 May 02:06 2015
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Definition of "width" in gem5

I have a very basic question, Is width defined in terms of No. of Instructions always? For instance let's say I want to simulate an x86 pipeline with issue width of 8 simple uops/cycle. Should I set issue width as 8 or 4 (fused uops/instructions ) ?
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Kaiyuan | 23 May 11:15 2015
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How to add new registers to ARM architecture

Hello, guys

I need to make some modification to ARM architecture by adding new registers. I searched source code, but didn't find files where define ARM registers.  How to add new registers to ARM architecture?

Could anyone give some suggestions? Thank you!


-Kaiyuan

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Vanchinathan Venkataramani | 22 May 20:05 2015
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Maximum ARM cores in FS mode

Hi all


I found that the maximum number of cores in arm fs mode is four. What do I need to do enable 8 cores?
Thanks a lot in advance.
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Ayaz Akram | 21 May 16:34 2015
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X86 In Order CPU Model

What is the current level of support for In Order pipeline configuration for X86 in gem5?
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Junaid Shuja | 21 May 04:14 2015
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Re: Android Boot error (Davesh Shingari)

Hi Davesh,
I got the frames from the folder you pointed out. But is there a way to interact with ANdroid GUI using gem5. Qemu lets you to do so. I was looking into gem5 for similar functionality.

On Wed, May 20, 2015 at 12:00 AM, <gem5-users-request <at> gem5.org> wrote:
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Today's Topics:

   1. Re: Android Boot error (Davesh Shingari)


----------------------------------------------------------------------

Message: 1
Date: Mon, 18 May 2015 10:37:43 -0700
From: Davesh Shingari <shingaridavesh <at> gmail.com>
To: gem5 users mailing list <gem5-users <at> gem5.org>
Subject: Re: [gem5-users] Android Boot error
Message-ID:
        <CAFVcd_zzdkdNvNZ5r_2b6jNsrrX7aqpzMRTUuKtBVWCy_Bok3g <at> mail.gmail.com>
Content-Type: text/plain; charset="utf-8"

Hi Junaid

When you specify the frame capture as the arguments, then you can see the
frames captured. And even though you got a shell, the system will continue
to keep on booting the Android OS (at ~2.5 seconds you get shell because
kernel boots up, but the Android OS boots at ~6.5 seconds). So just wait
for some more time and keep on checking the folder:
m5out/frames_system.vncserver and you will see something
like fb.000042.6170768127000.bmp.gz which is one frame captured. Extract it
and you will view the GUI frames.

Let me know if something is not clear.


On Sun, May 17, 2015 at 10:20 PM, Junaid Shuja <junaidshuja <at> siswa.um.edu.my>
wrote:

> Respected,
> I am booting android with the following command,
> junaid <at> junaid:~/gem5$ build/ARM/gem5.opt configs/example/fs.py -b
> bbench-ics --kernel=vmlinux.smp.mouse.arm --frame-capture
> --machine-type=RealView_PBX
>
> The telnet session boots into a root <at> android: command line instead of a
> GUI.
> How can I get the Android GUI from here?
>
>
> --
> Junaid Shuja
> WHA130039
> PhD Student, FSKTM
> University of Malaya
>
> _______________________________________________
> gem5-users mailing list
> gem5-users <at> gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>



--
Have a great day!

Thanks and Warm Regards
Davesh Shingari
Master's in Computer Engineering [EE]
Arizona State University

dshingar <at> asu.edu
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Junaid Shuja
WHA130039
PhD Student, FSKTM
University of Malaya
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Guru Prasad | 19 May 18:42 2015

Writing miscRegs from dram_ctrl.cc

Hi,

We've built an interface through which the kernel can poll miscRegs to
access some gem5 statistics. To ensure that multiple runs of the same
benchmark across different frequencies are doing the same work (in
userspace), I need to filter out the stat changes caused by hdlcd.
This is because the benchmark takes longer to execute at lower
frequencies which leads to more hdlcd accesses and higher stat values.

I fully understand that this is something that should be accounted for
in a real system, but for the purposes of creating comparable points
across simulations, we're opting to ignore hdlcd for now.

I've been trying to filter out the stat changes caused by the hdlcd
component but I notice that when i execute
system()->getThreadContext(0)->setMiscReg(register, value) from
DRAMCtrl::doDRAMAccess()
I break checkpointing.

Upon restoring from a checkpoint with arm_detailed, I get the following message.
gem5.opt: build/ARM/cpu/o3/inst_queue_impl.hh:1259: void
InstructionQueue<Impl>::doSquash(ThreadID) [with Impl = O3CPUImpl;
ThreadID = short int]: Assertion `squashed_inst->getFault() != NoFault
|| squashed_inst->isMemRef()' failed.
Program aborted at cycle 6087803509000
Aborted (core dumped)

Is there an easier way to separate hdlcd memory statistics?

Regards
Guru
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Gmane