Mohammad Malkawie | 26 Apr 01:36 2015

Fw: Problem in Running Interconnection Samples



On Sunday, April 26, 2015 2:34 AM, Mohammad Malkawie <mohammad.malkawie <at> ymail.com> wrote:


I tried to run sample configuration to start using GARNET in my NoC research, but after I run the sample commands which were written in http://www.gem5.org/Interconnection_Network, i got the following problem 

gem5 compiled Apr 20 2015 18:30:54
gem5 started Apr 21 2015 17:46:06
gem5 executing on Malkawie
command line: ./build/ALPHA/gem5.debug configs/example/ruby_random_test.py --num-cpus=16 --num-dirs=16 --topology=Mesh --mesh-rows=4 --garnet-network=fixed
Error: could not create sytem for ruby protocol MI_example
Traceback (most recent call last):
  File "<string>", line 1, in <module>
  File "/home/mmalkawie/new/gem5/src/python/m5/main.py", line 388, in main
    exec filecode in scope
  File "configs/example/ruby_random_test.py", line 108, in <module>
    Ruby.create_system(options, False, system)
  File "/home/mmalkawie/new/gem5/configs/ruby/Ruby.py", line 191, in create_system
    % protocol)
  File "<string>", line 1, in <module>
  File "/home/mmalkawie/new/gem5/configs/ruby/MI_example.py", line 85, in create_system
    clk_domain=system.cpu[i].clk_domain,
  File "/home/mmalkawie/new/gem5/src/python/m5/SimObject.py", line 1156, in __getitem__
    raise IndexError, "Non-zero index '%s' to SimObject" % key
IndexError: Non-zero index '1' to SimObject


The same problem displayed when I tried to run simple network. Please note that I tried the gem5 copy with GARNET on 3 copies of ubuntu, 14.04 64bit, 12.04 64bit, and 12.04 32bit, and fedora 20 32bit. All prerequisite packages were installed.

Please give me the solution for this problem if it exist as soon as possible.

 

Best Regards,
Mohammad Latayfeh



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Chongxi Bao | 25 Apr 03:31 2015
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X86 Full-system simulation hang shortly after restoring from a checkpoint

Hi all,

I am using the latest version of gem5-dev. I encountered a system hang shortly after restoring from a checkpoint. Here is what I did:

1. Take a checkpoint with atomic CPU, with X86_MOESI_hammer protocol:
./build/X86/gem5.opt configs/example/fs.py --num-cpus=4 --caches --l2cache --l1d_size=32768B --l1d_assoc=8 --l2_size=256kB --l2_assoc=8 --cacheline_size=64 --l1i_size=32768B --l1i_assoc=8 --cpu-type=atomic --num-l2caches=4 --script=configs/boot/hack_back_ckpt.rcS

2. Restore from this checkpoint using O3 CPU:
./build/X86_MOESI_CMP_directory/gem5.opt  configs/example/fs.py --num-cpus=4 --caches --l2cache --l1d_size=32768B --l1d_assoc=8 --l2_size=256kB --l2_assoc=8 --cacheline_size=64 --l1i_size=32768B --l1i_assoc=8 --num-l2caches=4  -r 1 --script=../scripts/blackscholes_4c_test.rcS  --cpu-type=detailed

Then I connected to port 3456, the system freezed shortly after displaying: loading new script...  I did a google search and found out that somebody else had reported this behavior but I did not find any solutions yet.

Any thoughts on this? Thank you in advance.

Best,
Chongxi

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Mohammad A Khasawneh | 23 Apr 17:13 2015

system.tol2bus has two ports

Hi everyone,

I'm working with the updated scripts from this link:
http://comments.gmane.org/gmane.comp.emulators.m5.users/14015, however
when I had some issues which I fixed, but there is one that popped up
and from the looks of things it seems to be the last, I get the
following error:

fatal: system.tol2bus has two ports responding within range [0 :
0xffffffffffffffff]:
        system.l2.cpu_side
        system.cpu.interrupts.pio

I can see the following lines in se2.py:
system.tol2bus = CoherentXBar(width = 32)
system.l2.cpu_side = system.tol2bus.master

but I can't find the code for system.cpu.interrupts.pio and how to
correctly connect the bus.

Thank you for your time,
Mohammad Khasawneh
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hancleyan | 21 Apr 23:35 2015
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"stack smashing detected" when built x86 full system

Hi,
I’m currently trying to build full system under x86 in order to run splash2 benchmarks with multi-cpus processor.
Here’s my system environment: 32-bit ubuntu linux system under VM on OS X.
To achieve my cache requirements, I built X86_MOESI_hammer in order to have private l2caches.
Here are my steps to build full system so far:

1. Downloaded x86-system and config-x86 packages and extracted them. Moved them to dictionary ~/gem5.
2. Downloaded ALPHA full system files and copied linux-bigswap2.img to ~/gem5/x86-system/disks/.
3. Modified path in /configs/common/SysPath.py to "path = [ '/dist/m5/system', '~/gem5/x86-system’ ]”.
4. Changed name of ~/gem5/x86-system/disks/linux-x86.img to x86root.img.

Then I typed following command "build/X86_MOESI_hammer/gem5.opt -d m5out configs/example/fs.py —kernel=x86_64-vmlinux-2.6.22.9”.
I didn’t get error but the program terminated due to “stack smashing detected”.
Here’s what I got after typing the commands above:

gem5 Simulator System. http://gem5.org 
gem5 is copyrighted software; use the --copyright option for details. 
gem5 compiled Apr 20 2015 18:12:20 
gem5 started Apr 21 2015 16:17:51 
gem5 executing on ubuntu 
command line: build/X86_MOESI_hammer/gem5.opt -d m5out configs/example/fs.py --kernel=x86_64-vmlinux-2.6.22.9 
Global frequency set at 1000000000000 ticks per second 
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) 
info: kernel located at: /home/hancle/gem5/x86-system/binaries/x86_64-vmlinux-2.6.22.9 
Listening for com_1 connection on port 3456 
 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000 
warn: Reading current count from inactive timer. 
**** REAL SIMULATION ****
info: Entering event queue <at> 0. Starting simulation… 
warn: Don't know what interrupt to clear for console. 
*** stack smashing detected ***: build/X86_MOESI_hammer/gem5.opt terminated 
Program aborted at cycle 7027708000 
Aborted (core dumped)

I couldn’t find any idea in previous postings, if anyone knows where the problem is please let know. 

Thanks 
Hancle  
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Kumail Ahmed | 21 Apr 21:22 2015
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PMU in GEM5

Hello everyone,

Is it possible to use the PMU with Arm ISA?

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Polydoros Petrakis | 21 Apr 16:20 2015
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Dynamically change options of BasicLink / BaseGarnetNetwork class

Hello,
I would like to be able to change the bandwidth_factor and ni_flit_size variables dynamically without the need to rebuild gem5 executable.

The variables are found in BasicLink.py and BaseGarnetNetwork.py.
( ruby network and garnet )

I have cheched Options.py, Ruby.py and network_test.py and have managed to add new options for classes like the NetworkTester (networktest.cc.)

However I 'm still searching for the aforementioned cases.
Could anyone help me with it?

Thanks in advance!
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Dao Lu | 20 Apr 21:21 2015
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arm-none-linux-gnueabi version?

HI,

On the tutorial where it has the following steps,

*Now, to build the 2.6.35 kernel.*

   1. Get the kernel source: git clone
   git://linux-arm.org/linux-2.6-armdroid.git -b 2.6.35-armdroid
   2. Get the 2.6.35 config file packaged with the linux kernel above.
   3. Copy it to the kernel source directory as .config.
   4. Build the kernel source: make ARCH=arm
   CROSS_COMPILE=arm-none-linux-gnueabi- -jn vmlinux
   EXTRA_CFLAGS=-mno-unaligned-access

I am wondering what version of the cross compiler it is referring?

I am using the following version
arm-none-linux-gnueabi-gcc (Sourcery CodeBench Lite 2014.05-29) 4.8.3
20140320 (prerelease)
and it seems like the compiled kernel does not work(the pre-built
version works). I am wonderng if the version of the compiler might be
the issue here?

Thanks,
Dao
--

-- 
Dao Lu
Graduate Student
Research Assistant
University of Illinois at Urbana-Champaign
(219)-208-5115
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Mohammad A Khasawneh | 20 Apr 17:31 2015

SimPoint Checkpoints in SE mode

Hi,

I have generated SimPoint files and now I'd like to get the
checkpoints from gem5, the sample instructions on the gem5 wiki use
fs.py but I'd like to use se.py, I tried to run it but it said "no
workload specified" since I didn't use the -c option. has anyone ever
successfully used SE mode for this operation?

Thanks,
Mohammad Khasawneh
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Abhishek Joshi | 20 Apr 15:04 2015
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Out-of-order-memory execution architecture support

Does gem5 simulate any Arm implementation with out-of-order memory execution support?, for example Cortex-A9 .

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Sreejith K M | 19 Apr 18:42 2015
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Implementing a queue for getting direct values for load instruction

Hi all,

   I want to give the memory load values directly from a queue to simulate a no-cache miss scenario. But I cant properly find out in which source file I should implement this queue for arm-detailed cpu. Where lies the variable which holds the data value loaded from memory/cache? While generating the trace file , we can find these load values corresponding to different addresses.   Please help.

thanks and regards,

Sreejith K M
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Swatilekha Majumdar | 19 Apr 16:37 2015
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Setting L2 cache in ruby as direct mapped

Hi,

I have been trying to set the L2 cache in gem5 (ruby) by using "--l2_assoc=1".
Command line: build/alpha/gem5.opt configs/example/se.py -n 1 --cpu-type=timing --caches --l2cache  --l2_size=64kB --l2_assoc=1 --script=runscript_canneal.rcs

But when simulating,  am getting an error:

terminate called after throwing an instance of 'std::bad_alloc'
what():  std::bad_alloc
Program aborted at cycle 0

Do you have any suggestions on where I am going wrong in this case?

Regards,
Swati
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