DIP replacement Policy

In Dynamic Insertion Policy (DIP) how do i track the misses incurrred? What is the condition to be stated in insertblock() function? Is it if(blk==NULL){PSEL++}?
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Ben James via gem5-users | 3 Mar 20:09 2015

Deadlock detected. Aborting!

Hi all, 

I tried to run the following command via Gem5. However, I recieved the following error. Could anyone help me with that.

Thanks,
Ben

Command:
./build/ALPHA/gem5.fast configs/example/fs.py --ruby --num-cpus=16 --l1i_size=32kB --l1d_size=32kB --l2_size=16MB --num-l2caches=1 --caches --mem-type ddr3_1600r_x64  --garnet-network=fixed --kernel=/home/b41/parsec/binaries/vmlinux --disk-image=/home/b41/parsec/disks/linux-parsec-2-1-m5.img --cpu-clock=2.5GHz --script=./runscript.rcS

Error:

info: Entering event queue <at> 0.  Starting simulation...
panic: Possible Deadlock detected. Aborting!
version: 15 request.paddr: 0x[0x8d00, line 0x8d00] m_readRequestTable: 1 current time: 400000000 issue_time: 10341200 difference: 389658800
  <at> tick 400000000
[wakeup:build/ALPHA/mem/ruby/system/Sequencer.cc, line 100]
Memory Usage: 854888 KBytes
Program aborted at cycle 400000000
Aborted


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How to get a streamline academic license?

Hi, I'm a research student getting started with gem5

Is anyone using the eclipse "streamline" plugin from ARM?

If so, how did you go about getting the license? The download page says to E-mail their university engagement staff but I get a reply saying they don't support research projects :/

Thanks and best,

Mike

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ARM full system simulation

I want to build a 16 arm core system, connected with mesh network, which means I have to use Ruby.
Unfortunately from the status matrix, arm and ruby combination definitely doesn't work together.

Is there any workaround?

Thanks

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Jianghao via gem5-users | 2 Mar 20:22 2015

NOC Network

In Mesh topology network, why there is requirement that the number of directories to be equal to the number of cpus?

How to specify number of L2 caches connected to the NOC network?

Thanks
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Raul Garcia via gem5-users | 2 Mar 19:18 2015

Cycle count for individual applications

Hello gem5 Team,

I'm interested in counting CPU cycles for a particular application (e.g. dhrystone benchmark) running in FS mode.

I found this old thread:  https://www.mail-archive.com/gem5-users <at> gem5.org/msg00396.html

This is what they suggest for a similar question: "Yes, you need to reset stats before app run and dump stats at the end of app" . But they do not provide more details how to do this.

Can you provide the procedure to reset, run and dump the stats for a particular program?

Best Regards,
Raul.

 
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n26001482 via gem5-users | 1 Mar 09:36 2015

What are the switch criterion ?

 Sorry about the mistake made in previous letter.

 hi, all.

 I found there are some switchs like switch cases (C/C++) in the files 
 "decode.cc" or "arm.isa"

 here's the code below:

 -----------------------------------------------------------------

 StaticInstPtr ArmISA::Decoder::decodeInst(ArmISA::ExtMachInst machInst){

 using namespace ArmISAInst; 
     switch (THUMB) { 
         case 0x0:
     switch (AARCH64) { 
         case 0x0:
     switch (COND_CODE) {
         case 0xf:
             // ArmUnconditional::armUnconditional(([], {})) {
                 ...
                 break;
         default: switch (ENCODING) {
             case 0x0:
                 switch (SEVEN_AND_FOUR) {
                 ...
                 ...
                 ...

 -----------------------------------------------------------------

 I'd like know what's the switch criterion?

 Such as "THUMB" , "AARCH64" , "COND_CODE" , "ENCODING" , "SEVEN_AND_FOUR" 
 ...etc.

 Are they defined in the file "arch/arm/types.hh" ? But it seem to be   
different?

 here's the code below:

 -----------------------------------------------------------------

 BitUnion64(ExtMachInst)
     // ITSTATE bits
     Bitfield<55, 48> itstate;
     Bitfield<55, 52> itstateCond;
     Bitfield<51, 48> itstateMask;

     // FPSCR fields
     Bitfield<41, 40> fpscrStride;
     Bitfield<39, 37> fpscrLen;

     // Bitfields to select mode.
     Bitfield<36>     thumb;    // here it's what I mentioned
     Bitfield<35>     bigThumb; // here it's what I mentioned
     Bitfield<34>     aarch64;  // here it's what I mentioned

     // Made up bitfields that make life easier.
     Bitfield<33>     sevenAndFour; // here it's what I mentioned
     Bitfield<32>     isMisc;       // here it's what I mentioned
     uint32_t         instBits;

     // All the different types of opcode fields.
     Bitfield<27, 25> encoding;
     ...
     ...
     ...

 -----------------------------------------------------------------
 And in the file "arm.isa" there's a paragraph

 '''
 // The actual ARM ISA decoder
 // --------------------------
 // The following instructions are specified in the ARM ISA
 // Specification. Decoding closely follows the style specified
 // in the ARM ISA specification document starting with Table B.1 or 3-1
 '''

 What's Table B.1 or 3-1? Where's it?
 I've read "ARM Architecture Reference Manual", but I did not find it.

 Thanks!
n26001482 via gem5-users | 1 Mar 08:39 2015

What are the switch criterion?

hi, all.
I found there are some switchs like switch cases (C/C++) in the file "decode.cc"
here's the code below:
------------------------------------------------------------------------------------------
StaticInstPtr
ArmISA::Decoder::decodeInst(ArmISA::ExtMachInst machInst)
{
    using namespace ArmISAInst;
  switch (THUMB) {
    
    case 0x0:
      switch (AARCH64) {
        
        case 0x0:
          switch (COND_CODE) {
            
            case 0xf:  
              // ArmUnconditional::armUnconditional(([], {}))
              
                  {
...
break;
    default: switch (ENCODING) { 

 case 0x0:
switch (SEVEN_AND_FOUR) {
...
...
...
------------------------------------------------------------------------------------------

I'd like know what's the switch criterion? 
Such as "THUMB" , "AARCH64" , "COND_CODE" , "ENCODING" , "SEVEN_AND_FOUR" ...etc
Are they defined in the file "arch/arm/types.hh" ?
here's the code below:
------------------------------------------------------------------------------------------
    BitUnion64(ExtMachInst)
        // ITSTATE bits
        Bitfield<55, 48> itstate;
        Bitfield<55, 52> itstateCond;
        Bitfield<51, 48> itstateMask;

        // FPSCR fields
        Bitfield<41, 40> fpscrStride;
        Bitfield<39, 37> fpscrLen;

        // Bitfields to select mode.
        Bitfield<36>     thumb; // here it's what I mentioned 
        Bitfield<35>     bigThumb; // here it's what I mentioned 
        Bitfield<34>     aarch64; // here it's what I mentioned 

        // Made up bitfields that make life easier.
        Bitfield<33>     sevenAndFour; // here it's what I mentioned 
        Bitfield<32>     isMisc; // here it's what I mentioned 

        uint32_t         instBits;

        // All the different types of opcode fields.
        Bitfield<27, 25> encoding;
...
...
...
------------------------------------------------------------------------------------------

Thanks!
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n26001482 via gem5-users | 1 Mar 06:54 2015

What are the switch criterion?

hi, all.
I found there are some switchs like switch cases (C/C++) in the file "decode.cc"
here's the code below:
------------------------------------------------------------------------------------------
StaticInstPtr
ArmISA::Decoder::decodeInst(ArmISA::ExtMachInst machInst)
{
    using namespace ArmISAInst;
  switch (THUMB) {
    
    case 0x0:
      switch (AARCH64) {
        
        case 0x0:
          switch (COND_CODE) {
            
            case 0xf:  
              // ArmUnconditional::armUnconditional(([], {}))
              
                  {
...
break;
    default: switch (ENCODING) { 

 case 0x0:
switch (SEVEN_AND_FOUR) {
...
...
...
------------------------------------------------------------------------------------------

I'd like know what's the switch criterion? 
Such as "THUMB" , "AARCH64" , "COND_CODE" , "ENCODING" , "SEVEN_AND_FOUR" ...etc
Are they defined in the file "arch/arm/types.hh" ?
here's the code below:
------------------------------------------------------------------------------------------
    BitUnion64(ExtMachInst)
        // ITSTATE bits
        Bitfield<55, 48> itstate;
        Bitfield<55, 52> itstateCond;
        Bitfield<51, 48> itstateMask;

        // FPSCR fields
        Bitfield<41, 40> fpscrStride;
        Bitfield<39, 37> fpscrLen;

        // Bitfields to select mode.
        Bitfield<36>     thumb; // here it's what I mentioned 
        Bitfield<35>     bigThumb; // here it's what I mentioned 
        Bitfield<34>     aarch64; // here it's what I mentioned 

        // Made up bitfields that make life easier.
        Bitfield<33>     sevenAndFour; // here it's what I mentioned 
        Bitfield<32>     isMisc; // here it's what I mentioned 

        uint32_t         instBits;

        // All the different types of opcode fields.
        Bitfield<27, 25> encoding;
...
...
...
------------------------------------------------------------------------------------------

Thanks!


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Fulya via gem5-users | 28 Feb 22:44 2015

Number of ROI instructions for Parsec with simlarge input

Hi,
I would like to know the number of ROI instructions for Parsec with simlarge input. In order to find that out,
I ran simulations using the timing simple CPU from the beginning to the end. I am wondering if the number of
ROI instructions would be the same or close to each other when running with detailed CPU?
Thanks in advance for your input.
Best,
Fulya
Ivan Stalev via gem5-users | 27 Feb 17:03 2015

Ethernet Bandwidth

Hi,

Is there a way to achieve more ethernet bandwidth than 1000mbps when simulating a client-server model? I am not really interested in a detailed simulation of the ethernet connection itself. I am simulating memory intensive applications with the goal of maxing out the server's memory bandwidth. The server receives thousands of queries per second from the client, but the sever's throughput is currently limited by the ethernet bandwidth as opposed to the memory. 

I could run the client and server applications on the same machine and have them communicate over TCP/IP loopback, but I want them to have completely separate caches/memories so that they do not interfere with each other. 

I am running GEM5 using ARMv8 64-bit. Any help/tips would be greatly appreciated!

Thank you,

Ivan
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Gmane