Cross bars and buses in classic memory model

I would like to know if a bus that has header_cycles = 0 will behave similar to a cross-bar.

Also, is it possible to replace the bus between L1 D and L2 D with a cross bar in classic memory model.

Any help is really appreciated.

Thanks
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huxain via gem5-users | 30 Jul 04:30 2014

ARM memory trace

hello,

how can i get a memory trace to use in DRAMPower using gem5?

and how can i use mcpat to calculate the processor power usage?

thanks a lot
jerry yin via gem5-users | 29 Jul 18:49 2014

DaCapo benchmarks

Hi all,

I'm trying to install and run java on gem5 full system mode. I follow the tutorial shown here: http://www.m5sim.org/DaCapo_benchmarks and did what exactly is told here. As I understand, the tutorial is not doing much but setting up the alias for java. However, when I start up the img file using gem5. Typing "java" will give output "-bash: /usr/bin/java: No such file or directory". Even if I go to the directory where java is installed: "/usr/lib/jvm/java-7-sun/bin# ./java" will not work, showing "-bash: ./java: No such file or directory"

I don't know what is happening here. I tried both jre ARMv6/7 Linux - Headless *, on http://www.oracle.com/technetwork/java/embedded/embedded-se/downloads/index.html#javase7update. The img file is used as provided. And I'm using build/ARM/gem5.opt. Any suggestion on running java program is welcomed. Thanks a lot!

Best regards,
Jer
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McPAT integration

hello,

I am trying to integrate McPAT with gem5 but I seem to be stuck with a small problem. The perl script which takes am xml input file to run McPAT seems to run into some error :  "no valid tag organizations found".

now, I have parsed through the mailing threads and found out that quite a number of people have had this problem. Has anybody found a solution to fix this or for that matter, has anyone got a patch running for this problem

-Anway
Utah State University

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Naman Jain via gem5-users | 28 Jul 12:08 2014

mem: Tag Addition in se.py


Hello,
I am willing to change BaseCache Tags (mem/cache/BaseCache.py) without having to compile repeatedly. Therefore, I plan to add ’tags’ in se.py or fs.py. After adding parser options in Options.py, what exactly should I add in se.py or fs.py?

I added BaseCache.tags = options.tag in se.py, but get this error:

command line: build/X86/gem5.opt configs/example/se.py -c mibench/office/stringsearch/search_small --output=mibench/office/stringsearch/output_small.txt --cpu-type=detailed --caches --tag=LRU()
Traceback (most recent call last):
  File "<string>", line 1, in <module>
  File "/home/namanjain/Documents/gem5/src/python/m5/main.py", line 388, in main
    exec filecode in scope
  File "configs/example/se.py", line 165, in <module>
    BaseCache.tags = options.tag
  File "/home/namanjain/Documents/gem5/src/python/m5/SimObject.py", line 339, in __setattr__
    cls._set_param(attr, value, param)
  File "/home/namanjain/Documents/gem5/src/python/m5/SimObject.py", line 276, in _set_param
    value = param.convert(value)
  File "/home/namanjain/Documents/gem5/src/python/m5/params.py", line 177, in convert
    return self.ptype(value)
TypeError: __init__() takes exactly 1 argument (2 given)
Error setting param BaseCache.tags to LRU()

Thanks,

Naman Jain

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CPU ID in cache and dram controller

Hi,

I need to manipulate requests received at cache and dram_ctrl on the basis of their original CPU/Thread source. I tried to get the cpuId from masterId by writing a function in system class , but found (or atleast suspect) that for writeback requests, the original owner (masterId) of the request is lost. I tried with contextId but found that sometimes the contextId is not set. 

Moreover, when I try to get the masterId of the request in dram_ctrl, sometimes I find that the request is NULL throwing a segfault.

I find that their is a field name _cpuId in BaseCPU class, but unfortunately it is not forwarded in any request object.

Is there any other means of knowing which CPU or Thread made the request to the cache and dram controller?

Thanks,
Debiprasanna Sahoo
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Besta Maciej via gem5-users | 26 Jul 02:09 2014

Simulating an IOMMU in gem5

Hello!

I'm trying to add the IOMMU to gem5 in the ARM full system simulation.
The model should be simple and it can essentially be just an element that adds
some delay, plus a TLB cache analogous to what we have in the MMU.

In the current ARM configuration, there is an iobus connected to a bridge, and the bridge connects
to the memory bus; so it looks like this:

==== mem bus ====  | Bridge |  ==== IO bus ====

My idea was to add one more Bridge and/or a cache (simulating the IOMMU), plus an additional
iobus2:

==== mem bus ====  | Bridge |  ==== IO bus ==== | Bridge-IOMMU | ==== IO bus 2 ====

Does anyone have an idea on how to achieve this goal? Is my idea valid, or is there a simpler/more
obvious approach that I'm not aware of?

I tried to modify the fs.py + FSConfig.py files, but I'm getting various panic errors. For example,
for the configuration above, I get:

> fatal: Unable to find destination for addr 0x1c090018 on bus testsys.iobus

and if I also connect a bridge-iommu for the traffic from the memory back, then I'm getting

>fatal: testsys.iobus2 has two ports with same range:
>        testsys.iommu_back.slave
>        testsys.realview.vram.port

thanks,
Mac

Runing multiple applications on different cpus in fs mode

Hi all,

How we can run multiple applications on different cpus in fs mode.
 
--
Kind Regards,
Mohammad Sadegh Sadeghi
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李佳坤 via gem5-users | 25 Jul 04:03 2014

cpu.numCycle does not correspond to sim_ticks and cpu-clock

Hello! I'm using gem5 to simulate a multi-workload 4-core system(1 workload for each core) under SE mode. I set the cpu clock to 3.2GHz( in Options.py) and max sim_ticks to 4*10^11 in command line. In the first test, the stats file shows that "cpu0.numCycles" is 1277955212 cycles, approximately 4*10^11 ticks. 

1277955212 * 1000/3.2 = 4 * 10 ^11.

However, after I made some modification to the cache part, the simulation result shows that ""cpu0.numCycles" becomes 652324098, which doesn't correspond to the sim_ticks and cpu clock frequency.

Does anyone have any idea about this? Thanks.

--

Department of Microelectronics and Nanoelectronics in Tsinghua University

Class 02     Li Jiakun

Mobile Phone: 8610-13693564079

Email: jiakunli2010 <at> gmail.com

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via gem5-users | 25 Jul 01:45 2014

ARM compiler flags


Hi all,

When I try running my own hello world binary for ARM, compiled  
natively on the BeagleBone, SE simulation fails as shown below.
Running the binary from tests/test-progs/hello/bin/arm/linux/hello,  
however, works just fine.

Are there any specific options that were used to compile the binary in  
the repository? Maybe any flags regarding the non-supported  
instructions for ARM in system call emulation?

This is the output from gem5:

---Simulation begins.
0: system.remote_gdb.listener: listening for remote gdb on port 7000
**** REAL SIMULATION ****
info: Entering event queue  <at>  0.  Starting simulation...
panic: Page table fault when accessing virtual address 0x1c
   <at>  cycle 698500
[invoke:build/ARM_SE/sim/faults.cc, line 64]
Memory Usage: 608316 KBytes
For more information see: http://www.m5sim.org/panic/4f0b3472
Program aborted at cycle 698500
Aborted

This is the command line:
./build/ARM_SE/m5.debug configs/example/se.py

I compiled my hello world binary on the BeagleBone Black, running  
Debian, with gcc-4.4. The binary in test-progs is compiled with  
gcc-4.3 on an Ubuntu machine. Passing both binaries through the  
file-command results in this:

hello world on BeagleBone:
ELF 32-bit LSB executable, ARM, version 1 (SYSV), statically linked,  
for GNU/Linux 2.6.26, not stripped
hello world from repository:
ELF 32-bit LSB executable, ARM, version 1 (SYSV), statically linked,  
for GNU/Linux 2.6.16, not stripped

I run a rather old version of gem5, however I am surprised that the  
binary in the repository passes simulation, but mine won't. Do you  
have any pointers that could help me out?

Thanks,
Max

Re: gem5-users Digest, Vol 96, Issue 17

Hello Senni Sophianne,

To configure gem5 according to parameters mentioned in O3_ARM_v7a.py file you need to first type on the command line :

build/ARM/gem5.opt   configs/common/O3_ARM_v7a.py

and then once the executable is configured with the parameters in O3_ARM_v7a.py you give the command line options as you mentioned in the mail.


On Wed, Jul 23, 2014 at 6:00 PM, via gem5-users <gem5-users <at> gem5.org> wrote:
Send gem5-users mailing list submissions to
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Today's Topics:

   1. Compile Linux kernel v3 for gem5 FS (saber nabavi via gem5-users)
   2. Re: Compile Linux kernel v3 for gem5 FS
      (Anthony Gutierrez via gem5-users)
   3. Re: Compile Linux kernel v3 for gem5 FS (Zi Yan via gem5-users)
   4. AttributeError when creating own configuration
      (Weber, Fabian via gem5-users)
   5. Cache configuration of arm_detailed
      (senni sophiane via gem5-users)


----------------------------------------------------------------------

Message: 1
Date: Tue, 22 Jul 2014 22:55:49 +0430
From: saber nabavi via gem5-users <gem5-users <at> gem5.org>
To: gem5-users <at> gem5.org
Subject: [gem5-users] Compile Linux kernel v3 for gem5 FS
Message-ID:
        <CAP6Eee-LjrgLBiVmof0+pKG+rgd3H3kTmNZc1rLfGojBzU9gDg <at> mail.gmail.com>
Content-Type: text/plain; charset="iso-8859-1"

Hi,
I was wondering if I could compile and use linux kernel version 3 or above
with gem5. I mean is it compatible with 2.6.* or will gem5 patches work
with it?

Saber.
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Message: 2
Date: Tue, 22 Jul 2014 14:29:08 -0400
From: Anthony Gutierrez via gem5-users <gem5-users <at> gem5.org>
To: gem5 users mailing list <gem5-users <at> gem5.org>
Subject: Re: [gem5-users] Compile Linux kernel v3 for gem5 FS
Message-ID:
        <CAEQEbpT4qG+OnmAXL+MLeF1rTS1EE16ykFxOZcf_2QJqgrK_Ug <at> mail.gmail.com>
Content-Type: text/plain; charset="utf-8"

For ARM you definitely can. Use the patch and kernel config contained here:

http://www.gem5.org/dist/current/arm/vmlinux-emm-pcie-3.3.tar.bz2

And the kernel source here:

http://www.gem5.org/dist/current/arm/linux-arm-arch.tar.bz2


Anthony Gutierrez
http://web.eecs.umich.edu/~atgutier


On Tue, Jul 22, 2014 at 2:25 PM, saber nabavi via gem5-users <
gem5-users <at> gem5.org> wrote:

> Hi,
> I was wondering if I could compile and use linux kernel version 3 or above
> with gem5. I mean is it compatible with 2.6.* or will gem5 patches work
> with it?
>
> Saber.
>
> _______________________________________________
> gem5-users mailing list
> gem5-users <at> gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>
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Message: 3
Date: Tue, 22 Jul 2014 14:58:49 -0400
From: Zi Yan via gem5-users <gem5-users <at> gem5.org>
To: "gem5 users mailing list" <gem5-users <at> gem5.org>
Subject: Re: [gem5-users] Compile Linux kernel v3 for gem5 FS
Message-ID: <A2F0F75A-BDEA-4CC6-9E78-CB4E5F7C3380 <at> gmail.com>

How about DTB(device tree blob) file? Do we need a DTB file for
kernel running on gem5-ARM?

Thanks.

--
Best Regards
Yan Zi

On 22 Jul 2014, at 14:29, Anthony Gutierrez via gem5-users wrote:

> For ARM you definitely can. Use the patch and kernel config contained here:
>
> http://www.gem5.org/dist/current/arm/vmlinux-emm-pcie-3.3.tar.bz2
>
> And the kernel source here:
>
> http://www.gem5.org/dist/current/arm/linux-arm-arch.tar.bz2
>
>
> Anthony Gutierrez
> http://web.eecs.umich.edu/~atgutier
>
>
> On Tue, Jul 22, 2014 at 2:25 PM, saber nabavi via gem5-users <
> gem5-users <at> gem5.org> wrote:
>
>> Hi,
>> I was wondering if I could compile and use linux kernel version 3 or above
>> with gem5. I mean is it compatible with 2.6.* or will gem5 patches work
>> with it?
>>
>> Saber.
>>
>> _______________________________________________
>> gem5-users mailing list
>> gem5-users <at> gem5.org
>> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
>>
> _______________________________________________
> gem5-users mailing list
> gem5-users <at> gem5.org
> http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users


------------------------------

Message: 4
Date: Tue, 22 Jul 2014 21:10:51 +0000
From: "Weber, Fabian via gem5-users" <gem5-users <at> gem5.org>
To: "gem5-users <at> gem5.org" <gem5-users <at> gem5.org>
Subject: [gem5-users] AttributeError when creating own configuration
Message-ID:
        <A837B72F7988834E815986A038ABDD1C11EEEAAC <at> mail4.ad.uni-siegen.de>
Content-Type: text/plain; charset="iso-8859-1"

Hi everyone,

I've a problem creating an own configuration. Starting from the ruby_network_test.py I copied this configuration file and the network_test folder which includes networktest.cc/hh and NetworkTest.py. Then I renamed them to tt_network ... (and also the class and methods in the source file).

It compiles successfully but does not execute:

Traceback (most recent call last):
  File "<string>", line 1, in <module>
  File "/gem5/src/python/m5/main.py", line 388, in main
    exec filecode in scope
  File "configs/example/ruby_tt_network_test.py", line 123, in <module>
    for ruby_port in system.ruby._cpu_ruby_ports:
  File "/gem5/src/python/m5/SimObject.py", line 736, in __getattr__
    raise AttributeError, err_string
AttributeError: object 'RubySystem' has no attribute '_cpu_ruby_ports'
  (C++ object is not yet constructed, so wrapped C++ methods are unavailable.)

Does somebody knows this error and could explain what I forgot/have to do?

Best regards,
Fabian

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Message: 5
Date: Wed, 23 Jul 2014 11:17:41 +0200
From: senni sophiane via gem5-users <gem5-users <at> gem5.org>
To: gem5 users mailing list <gem5-users <at> gem5.org>
Subject: [gem5-users] Cache configuration of arm_detailed
Message-ID: <53CF7DB5.2060405 <at> gmail.com>
Content-Type: text/plain; charset=ISO-8859-1

Hi all,

When I am using the options --cpu_type=arm_detailed --caches --l2cache
in the command line, the cache configuration of the system is not the
one specified in the O3_ARM_v7a.py file. Instead it is the cache
configuration described in Caches.py
This is the command line I used :

build/ARM/gem5.opt configs/example/fs.py --caches --l2cache
--cpu-type=arm_detailed -n4 -b splash2_fmm


Does someone know what could be the reason ? Am I missing something ?

Thanks for your help.

--
Cordialement / Best Regards

SENNI Sophiane
Ph.D. candidate - Microelectronics
LIRMM - www.lirmm.fr



------------------------------

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End of gem5-users Digest, Vol 96, Issue 17
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