Re: svc Instruction

At the end of svc instruction, R0 is being updated. On what case is R0 changed?

Thanks
V Vanchinathan


On Thu, Aug 28, 2014 at 2:20 PM, Vanchinathan Venkataramani <dcsvave <at> nus.edu.sg> wrote:
At the end of svc instruction, R0 is being updated. On what case is R0 changed?

Thanks
V Vanchinathan


On Wed, Aug 27, 2014 at 5:23 PM, Vanchinathan Venkataramani <dcsvave <at> gmail.com> wrote:
Hi all

I would like to know how svc (trap) instruction is implemented in gem5.

In particular I want to know on what condition the register values are changed when svc syscall is present.

Thanks a lot!


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Hussain Asad via gem5-users | 28 Aug 08:01 2014

Debug flag DRAMPower

Hi,

I have been running with the debug flag option for DRAMPower for memory power consumption however I noticed that there are no writes in any of the traces generated no matter the CPU type, seems write commands does not get registered from mem_cntrls.

Best Regards
Hussain
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Local Directory in MOESI L2 in Ruby

Hi All,

MOESI CMP directory in Ruby models the L2 controller with a L2 cache and a Local Directory(modelled as PerfectCacheMemory).
MOESI_CMP_directory being a Non-Exclusive Protocol, stores the meta data about the lines not present in L2 but present in one of the L1s, in the Local Directory.

This Local Directory number of entries can grow to a number equal to the number of entries in each L1 multiplied by number of L1s.
4core 64K I and D cache with 64Byte LineSize will have maximum 8kentries in the Local Directory.

I was wondering, could anyone please guide me as to what kind of data storage will be used for such a structure?
8k entries with address and meta data stored for each entry.

I think its not correctly modelled. There are no replacements from the data structure(PerfectCacheMemory) which is a unordered_map like the tbe.
TBEs dont grow in size much and there is limit to that as well.
However Local Directory has no limit.

I wanted to know, how could we model such a structure in a real hardware?
The way its modelled, it looks like a large CAM/Fully Associative Cache with no Data Array.
The access time to this cache is not accounted for as well. If we assume a Fully Associative cache, the current model works as if L2 Cache and the Fully Associative cache are accessed in parallel.

Am I correct in this interpretation?

Thanks,

--
Pushkar Nandkar
Graduate Student
Department of Electrical and Computer Engineering
University of Minnesota, Twin Cities
Minneapolis, MN - 55414
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Zi Yan via gem5-users | 27 Aug 19:02 2014

Big executed instruction difference between X86 atomic adn X86 O3

Hi all,

I am running kmeans via hadoop in gem5 X86 FS mode. I am using 
linux kernel 3.2.60 with configuration file linux-2.6.28.4 from 
gem5.org.

I take a checkpoint before a map task and put a "m5 exit" after the map task.
I am using *X86kvmCPU* to take checkpoints.

When I restore from the same checkpoint, atomic CPU and O3 CPU give me
quite different executed instructions:
1) atomic CPU executes about 350 million instructions, reaches "m5 exit",
then stops simulation.
2) O3 CPU executes more than 12 billion instructions, and still not reaches
"m5 exit" to stop the simulation.

I dump out committed PCs from atomic CPU and O3 CPU, finding out that
after about 500,000 instructions, the systems behave differently,
where atomic CPU is still executing user code, but O3 CPU switch to 
apic_timer_interrupt(a kernel function, it also appears in atomic CPU
execution, but somewhere else).

Could anyone please give some advice about why this happen?

Thanks.

--
Best Regards
Yan Zi
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svc Instruction

Hi all

I would like to know how svc (trap) instruction is implemented in gem5.

In particular I want to know on what condition the register values are changed when svc syscall is present.

Thanks a lot!
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Chao Zhang via gem5-users | 27 Aug 08:47 2014

How many cpu does the x86 vmlinux SMP kernel support?

Dear all,

I’m currently working on x86 FS on classical memory system to simulate cache system. But I found the kernel booting just hangs before loading benchmark script. It does not work when I set 3 or more x86 timing simple cpus, but it does work when I set them as atomic cores. And it also works when I set cpu number to 1. The gem5 change set version is 10242, the kernel is the SMP version from gem5 website (x86_64-vmlinux-2.6.28.4-smp), and I use default fs.py configuration. 

So I want to know how many x86 timing cores does this SMP kernel support? Or is this a memory system problem? 

Chao Zhang
Peking University





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How to add shared nonblocking L3 cache in gem5?

Hi Users,


I am new to gem5 and I want to add nonblacking shared Last level cache(L3). I could see L3 cache options in Options.py with default values set. However there is no entry for L3 in Caches.py and CacheConfig.py. 

So extending Cache.py and CacheConfig.py would be enough to create L3 cache?


Thanks,
Prathap

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Fulya via gem5-users | 26 Aug 22:12 2014

Kernel version vs Gem5 version

Hi all,
It seems like using the kernel version x86_64-vmlinux-2.6.22.9.smp may have solved my problem that was
posted in this thread:
http://www.mail-archive.com/gem5-users <at> gem5.org/msg10387.html
However, I am using the latest gem5 version gem5-stable-aaf017eaad7d and I only tested the atomic cpu
without any checkpointing or fast forwarding. Are the any problems related to using an older kernel
version (such as x86_64-vmlinux-2.6.22.9.smp) with gem5?
Best,
Fulya

O3 fetch throughput when i-cache hit latency is more than 1 cycle

Hi,

Looking at the codes for the fetch unit in O3, I realized that the fetch unit does not take advantage of non-blocking i-caches. The fetch unit does not initiate a new i-cache request while it is waiting for the an i-cache response. Since fetch unit in O3 does not pipeline i-cache requests, fetch unit throughput reduces significantly when the i-cache hit latency is more than 1 cycle. I expected that fetch unit should be able to initiate a new i-cache request each cycle (based on BTB addr or next sequential fetch addr) even when fetch unit is waiting for i-cache responses. Any thoughts on this?

I understand a large fetch buffer can mitigate this to some degree...

Thanks,
Amin
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Hussain Asad via gem5-users | 26 Aug 12:03 2014

Re: Gem5 on multiple cores

Thank you, Andreas
*moved to gem5-users :)


On Tue, Aug 26, 2014 at 8:39 AM, Andreas Hansson <Andreas.Hansson <at> arm.com> wrote:
Hi Hussain,

I’d suggest to ask on the gem5-users list for everyone’s benefit.

Multi-threading invariably comes at a cost, and if you want to run say 10 experiments, they are embarrassingly parallel. As one of the main purposes of gem5 is design-space exploration most users will be running 10’s or 100’s of experiments. Thus, instead of making gem5 multi-threaded and “throwing performance away”, it is efficient as a single-threaded simulator, and I suggest to run your experiments in parallel to make use of your many cores/servers etc.

Andreas

From: Hussain Asad <x7xcloudstrife <at> gmail.com>
Date: Tuesday, 26 August 2014 04:13
To: Andreas Hansson <andreas.hansson <at> arm.com>
Subject: Gem5 on multiple cores

Hi Andreas,

I have a quick question, I am running gem5 build on a core i7 system, but gem5 uses just one core of the available 8(4cores +4threads).

Is this feature not yet implemented or am I compiling the system not correctly, As I would assume if it was using all my CPU cores the simulation would be much faster.

running gem5 on Ubuntu 14 LTS, core i7, 8GB of RAM at the moment, should I move my system to University servers would it be faster in a server system?

Thanks
Best Regards
Hussain

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Errors on compiling gem5.fast

Hi,

I am unable to build gem5.fast and its terminating with the following error.
"g++: error: -fuse-linker-plugin is not supported in this configuration"

I am using  gcc/4.8.2.  I did run into similar error for --plugin for gcc/4.6.3
Is anyone aware why would I be running into this while compiling
gem5.fast. I was able to build gem5.opt without any such issues.

Thanks,
Nishant Borse

Gmane