hoda aghaei khouzani | 5 May 23:55 2016
Picon

TLB, TimingSimpleCPU

Hello,

I'm trying to change the latency of miss and hit in TLB for x86.
However, I don't know in which files these latencies are set. 

Also, handling the miss in TLB is not clear for me. My problem is, after 
TLB code calls start function in the walker, I can't figure out control 
path in it. It seems to me the translation is finished there, and nothing 
happens after invoking walker functions. Would you please let me know what 
will happen after that.

Regards

_______________________________________________
gem5-users mailing list
gem5-users <at> gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
dipesh ingawale | 4 May 23:58 2016
Picon

How can I trace vector multiplication instruction

Hi Everyone,

I want to trace vector multiplication instructions in X86 architecture which uses XMM registers. How can I extract those Instruction's informations such as the instruction and their operand's values?

When I use debug-trace flags, the type of floating point multiplication Instructions such as mulsd is shown as FloatAdd. I don't understand why is it not showing as FloatMult or SimdFloatMult?

Thank you.

-Dipesh
_______________________________________________
gem5-users mailing list
gem5-users <at> gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
anoir nechi | 4 May 15:55 2016
Picon

Creating a Multi-core system

Hi

I am new with Gem5 simulator
So, i intend to create a multi-core system as a first step then inject some faults scenarios to  see how much is the system fault tolerant. But, i have no idea about how to make a multi-core system, i wonder if i have just to instantiate the CPU more then once or MAYBE it's not as simple as that?

If someone could give me some examples
and one more thing can i use the ARM11 as CPU or Gem5 do not support it yet?

Thank you

--
Anouar NECHI
IT Engineer : Industrial systems
Higher Institute of Computer Science
Tunis - El Manar University
Phone : (+216) 50 311 536
_______________________________________________
gem5-users mailing list
gem5-users <at> gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Tanmay Gangwani | 4 May 12:26 2016
Picon

Repeated switching between timing and atomic

Hi,

I have a multi-threaded program which runs great on GEM5 with :

--cpu-type=timing, or

--cpu-type=atomic

I have now been trying to run the same code, but with periodic repeated switching between the timing and atomic type CPUs. Here's my command line - 

./build/X86/gem5.opt configs/example/se.py --repeat-switch=1000000000 --cpu-type=atomic --restore-with-cpu=timing --checkpoint-restore=1 --caches -n64 --mem-size=8GB -c <application-64-threads>

The code runs for a while, but then I get a segmentation fault. A run under GDB tells me that this happens at -

0x000000000068ee86 in MasterPort::sendAtomic(Packet*) () at build/X86/mem/port.cc:168

168         return _slavePort->recvAtomic(pkt);

(gdb) bt

#0  0x000000000068ee86 in MasterPort::sendAtomic(Packet*) () at build/X86/mem/port.cc:168

#1  0x00000000005736ef in AtomicSimpleCPU::tick() () at build/X86/cpu/simple/atomic.cc:615

#2  0x00000000008000c1 in EventQueue::serviceOne() () at build/X86/sim/eventq.cc:228

#3  0x0000000000820c18 in doSimLoop(EventQueue*) () at build/X86/sim/simulate.cc:218


Could someone confirm if this is the best way to switch between timing and atomic models?

Any pointers on which source files to start from to debug this? 

Also, I sometimes get the following print on the console when the simulator switches from atomic to timing: 

WARNING: Bank is already active!

Command: 0, Timestamp: 6448, Bank: 4

WARNING: Bank is already active!

Command: 0, Timestamp: 8074, Bank: 2

WARNING: Bank is already active!

Command: 0, Timestamp: 6860, Bank: 1


Thanks.

_______________________________________________
gem5-users mailing list
gem5-users <at> gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Rodrigo Cataldo | 3 May 18:30 2016
Picon

Re: Core dump at a fresh installation of Gem5

Hello,
According to the TOPAZ simulator (https://github.com/abadp/tpzsimul/wiki/GEM5Integration), the Ruby Network Tester is broken since commit 10089. See the link for more details

On Thu, Apr 28, 2016 at 3:30 PM, Ahmadian, Hamidreza <hamidreza.ahmadian <at> uni-siegen.de> wrote:

Dear all,

 

I just installed a fresh stable version of Gem5 and tried to run the simulation but I get core dumped error.

Below are the details:

 

Linux version: Linux Gem5 3.13.0-43-generic #72-Ubuntu SMP Mon Dec 8 19:35:06 UTC 2014 x86_64 x86_64 x86_64 GNU/Linux

 

Cloned using: hg clone http://repo.gem5.org/gem5-stable gem5

Compiled using: scons -j 4 build/ALPHA_Network_test/gem5.opt PROTOCOL=Network_test

Ran the simulation: ./build/ALPHA_Network_test/gem5.opt configs/example/ruby_network_test.py --num-cpus=16 --num-dirs=16 --topology=Mesh --mesh-rows=4 --sim-cycles=1000 --injectionrate=0.01 --synthetic=0 --fixed-pkts --maxpackets=1 --garnet-network=fixed

 

But I get the following error at the end of simulation:

panic: Cannot test intersection of [0 : 0x1fffffff], [9 : 6] XOR [23 : 20] = 0 and [0 : 0x7ffffff]

<at> tick 0

[intersects:build/ALPHA_Network_test/base/addr_range.hh, line 304]

Memory Usage: 112276 KBytes

Program aborted at cycle 0

Aborted (core dumped)

 

When I try to debug it I get the following messages:

panic: Cannot test intersection of [0 : 0x1fffffff], [9 : 6] XOR [23 : 20] = 0 and [0 : 0x7ffffff]

<at> tick 0

[intersects:build/ALPHA_Network_test/base/addr_range.hh, line 304]

Memory Usage: 113300 KBytes

 

Program received signal SIGABRT, Aborted.

0x00007ffff641dcc9 in __GI_raise (sig=sig <at> entry=6) at ../nptl/sysdeps/unix/sysv/linux/raise.c:56

56      ../nptl/sysdeps/unix/sysv/linux/raise.c: No such file or directory.

(gdb) back

#0  0x00007ffff641dcc9 in __GI_raise (sig=sig <at> entry=6) at ../nptl/sysdeps/unix/sysv/linux/raise.c:56

#1  0x00007ffff64210d8 in __GI_abort () at abort.c:89

#2  0x00000000007f4d1c in __exit_epilogue (code=code <at> entry=-1, func=func <at> entry=0xdeef8d <AddrRange::intersects(AddrRange const&) const::__FUNCTION__> "intersects", file=file <at> entry=0xdee8e8 "build/ALPHA_Network_test/base/addr_range.hh", line=line <at> entry=304,

    format=format <at> entry=0xdeeb58 "Cannot test intersection of %s and %s\n") at build/ALPHA_Network_test/base/misc.cc:94

#3  0x000000000061970e in __exit_message<std::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::basic_string<char, std::char_traits<char>, std::allocator<char> > > (format=0xdeeb58 "Cannot test intersection of %s and %s\n", line=304,

    file=0xdee8e8 "build/ALPHA_Network_test/base/addr_range.hh", func=0xdeef8d <AddrRange::intersects(AddrRange const&) const::__FUNCTION__> "intersects", code=-1, prefix=0x10285af "panic") at build/ALPHA_Network_test/base/misc.hh:81

#4  AddrRange::intersects (this=this <at> entry=0x27d4360, r=...) at build/ALPHA_Network_test/base/addr_range.hh:304

#5  0x000000000061610a in AddrRangeMap<AbstractMemory*>::find (this=this <at> entry=0x2633628, r=...) at build/ALPHA_Network_test/base/addr_range_map.hh:86

#6  0x0000000000617b28 in find (r=..., this=0x2633628) at build/ALPHA_Network_test/base/trace.hh:68

#7  intersect (r=..., this=0x2633628) at build/ALPHA_Network_test/base/addr_range_map.hh:120

#8  insert (d= <at> 0x1de2680: 0x252b480, r=..., this=0x2633628) at build/ALPHA_Network_test/base/addr_range_map.hh:126

#9  PhysicalMemory::PhysicalMemory (this=0x2633618, _name=..., _memories=..., mmap_using_noreserve=<optimized out>) at build/ALPHA_Network_test/mem/physical.cc:94

#10 0x000000000085826a in System::System (this=0x2633500, p=0x1eb01e0) at build/ALPHA_Network_test/sim/system.cc:99

#11 0x0000000000858c41 in SystemParams::create (this=0x1eb01e0) at build/ALPHA_Network_test/sim/system.cc:492

#12 0x0000000000d1643b in _wrap_SystemParams_create (args=<optimized out>) at build/ALPHA_Network_test/python/m5/internal/param_System_wrap.cc:4852

#13 0x00007ffff77e50d4 in PyEval_EvalFrameEx () from /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0

#14 0x00007ffff77e654d in PyEval_EvalCodeEx () from /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0

#15 0x00007ffff77e4dd8 in PyEval_EvalFrameEx () from /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0

#16 0x00007ffff77e654d in PyEval_EvalCodeEx () from /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0

#17 0x00007ffff77e4dd8 in PyEval_EvalFrameEx () from /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0

#18 0x00007ffff77e654d in PyEval_EvalCodeEx () from /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0

#19 0x00007ffff77e4dd8 in PyEval_EvalFrameEx () from /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0

#20 0x00007ffff77e654d in PyEval_EvalCodeEx () from /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0

#21 0x00007ffff77e4dd8 in PyEval_EvalFrameEx () from /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0

#22 0x00007ffff77e654d in PyEval_EvalCodeEx () from /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0

#23 0x00007ffff77e6682 in PyEval_EvalCode () from /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0

#24 0x00007ffff77e5b3e in PyEval_EvalFrameEx () from /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0

#25 0x00007ffff77e654d in PyEval_EvalCodeEx () from /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0

#26 0x00007ffff77e4dd8 in PyEval_EvalFrameEx () from /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0

#27 0x00007ffff77e654d in PyEval_EvalCodeEx () from /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0

#28 0x00007ffff77e6682 in PyEval_EvalCode () from /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0

#29 0x00007ffff77e04b9 in PyRun_StringFlags () from /usr/lib/x86_64-linux-gnu/libpython2.7.so.1.0

#30 0x000000000083863f in m5Main (argc=argc <at> entry=12, argv=argv <at> entry=0x7fffffffe438) at build/ALPHA_Network_test/sim/init.cc:221

#31 0x00000000005ab463 in main (argc=12, argv=0x7fffffffe438) at build/ALPHA_Network_test/sim/main.cc:58

 

Can you help me to find the error?

 

Best regards,

Hamidreza Ahmadian


_______________________________________________
gem5-users mailing list
gem5-users <at> gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

_______________________________________________
gem5-users mailing list
gem5-users <at> gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Andreas Sandberg | 3 May 15:25 2016

Re: Global objects

Hi Louisa,

I think what you¹re looking for is a pretty standard singleton pattern.
See for example [1] or [2].

The basic idea is that you make the constructor private and provide a
static method (usually called MyClass::instance()) that returns the global
instance. Depending on what you¹re doing, you could statically instantiate
the global instance or create it dynamically the first time instance() is
called.

//Andreas

[1] https://sourcemaking.com/design_patterns/singleton/cpp/1

[2] http://stackoverflow.com/questions/1008019/c-singleton-design-pattern

On 29/04/2016, 09:21, "gem5-users on behalf of Louisa Bessad"
<gem5-users-bounces <at> gem5.org on behalf of louisa.bessad <at> lirmm.fr> wrote:

>Hi all,
>
>I want to use global unique objects in gem5. I am wondering where should
>I instantiate these objects in the source code.
>
>I saw that the instantiate() method initialize all SimObjects[1] but my
>objects are not SimObjects.
>
>[1] http://gem5.org/SimObject_Initialization
>
>
>Thank you
>
>+-------------------------------+
>| Louisa Bessad                 |
>| PhD student - LIRMM - SYSMIC  |
>| Bâtiment 4 Bureau 2.92        |
>+-------------------------------+
>_______________________________________________
>gem5-users mailing list
>gem5-users <at> gem5.org
>http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be
privileged. If you are not the intended recipient, please notify the sender immediately and do not
disclose the contents to any other person, use it for any purpose, or store or copy the information in any
medium. Thank you.

_______________________________________________
gem5-users mailing list
gem5-users <at> gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Marcos Horro Varela | 3 May 13:34 2016
Picon

Data cache L1 in classic model

Hello all,

I was looking through the configuration of cache memories in the classic model, and I found that in the
configs/common/Caches.py, in the L1_DCACHE class, the value writeback_clean is set to False.
Nevertheless, in src/mem/cache/Caches.py it is said that: "In general this (param) should be set to True
for anything but the last-level cache". Thus, is this instantiaton coherent? Because in the
CacheConfig.py it is NOT set to True either.

Thanks

Best regards,

--

-- 
Marcos Horro Varela,
BSc student, University of A Coruña (UDC)
+34 618 62 67 37
http://markos-horro.com
_______________________________________________
gem5-users mailing list
gem5-users <at> gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
mengyu liang | 3 May 09:05 2016
Picon

Ruby random test failed!

Hi everyone,
I am new to gem5 and now studying the network topology with multi processors.
Today I tried to run the ruby random test with ALPHA architecture and followed the first example from the link:
http://www.gem5.org/Interconnection_Network

with all default settings. However the simulation ONLY succeeded with one SINGLE cpu. That means the --num_cpu and --num_dirs have to be 1. If I increase the numbers larger than 1, I will get following error messages:

command line: ./build/ALPHA/gem5.debug configs/example/ruby_random_test.py --num-cpus=16 --num-dirs=16 --topology=Mesh --mesh-rows=4

Error: could not create sytem for ruby protocol MI_example
Traceback (most recent call last):
  File "<string>", line 1, in <module>
  File "/home/gu47liy/Work/NewGem5/gem5-stable/src/python/m5/main.py", line 388, in main
    exec filecode in scope
  File "configs/example/ruby_random_test.py", line 108, in <module>
    Ruby.create_system(options, False, system)
  File "/home/gu47liy/Work/NewGem5/gem5-stable/configs/ruby/Ruby.py", line 191, in create_system
    % protocol)
  File "<string>", line 1, in <module>
  File "/home/gu47liy/Work/NewGem5/gem5-stable/configs/ruby/MI_example.py", line 85, in create_system
    clk_domain=system.cpu[i].clk_domain,
  File "/home/gu47liy/Work/NewGem5/gem5-stable/src/python/m5/SimObject.py", line 1156, in __getitem__
    raise IndexError, "Non-zero index '%s' to SimObject" % key
IndexError: Non-zero index '1' to SimObject

By the way, I have used MI-example as coherence protocol by building ALPHA.
Can anybody help? Should I probably use other coherence protocol than MI-example for ruby random test?

Thanks in advance,
Best regards,
Leo
_______________________________________________
gem5-users mailing list
gem5-users <at> gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Ayaz Akram | 1 May 21:16 2016
Picon

Branch Predictor in Minor Cpu

I have observed that branch predictor stats do not update for Minor Cpu when used with x86 (every branch predictor related stat stay 0). Changing ISA to Arm with same Minor Cpu configurations show branch predictor stats in output stats.txt file. I wonder if anyone else experienced such issue ?
P.S: I have observed this on various benchmarks.
_______________________________________________
gem5-users mailing list
gem5-users <at> gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Abdul Mutaal | 1 May 13:26 2016
Picon

Re: Measuring latency & bandwidth accurately

Hi Radhika,

Thanks for your answer. 

My system consists of Traffic generator replaying some recorded traces. I would like to measure the latency & bandwidth of my system attached with traffic generator. 

Just a side question - After running the trace I see that there is stat called 'numRetries' and 'retryTicks' , which are the ticks wasted during back pressure. So my question is, does CommMonitor has the ability to count latency of packet if the packet experiences a back-pressure and retry is being done from traffic generator. 

Thanks

2016-04-29 9:42 GMT+02:00 Radhika Jagtap <radhika.jagtap <at> arm.com>:

Hi Abdul,

 

What do you mean by certain architecture? As you may know, CommMonitor is connected between two ports and so it (reliably and accurately) measures the latency and bandwidth statistics of requests between those two ports. I you want to measure these as seen by the application, you could connect the CommMonitor between the core and L1 data cache ports. If you are looking for characterizing, that is things like maximum bandwidth and static latency (ie round trip latency per single request is in flight), then running lmbench benchmarks could be useful .

 

Radhika

 

From: gem5-users [mailto:gem5-users-bounces <at> gem5.org] On Behalf Of Abdul Mutaal
Sent: 25 April 2016 22:20
To: gem5 users mailing list
Subject: [gem5-users] Measuring latency & bandwidth accurately

 

Hi, 

 

How can I accurately measure bandwidth & latency of certain architecture ? I am currently using CommMonitor. Is that reliable or is there any other method to measure accurately in gem5.

 

 

 

Thanks

 

--

 

Regards,

Abdul Mutaal 

 

 

IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

_______________________________________________
gem5-users mailing list
gem5-users <at> gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users



--

Regards,
Abdul Mutaal 


_______________________________________________
gem5-users mailing list
gem5-users <at> gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users
Ayaz Akram | 30 Apr 19:58 2016
Picon

SIMD instructions on Arm

This question is not directly related to gem5, but I am asking here as a lot of community members are using gem5 for Arm simulations. I am trying to  compile some SPEC2006 benchmarks for Arm without any simd instructions. I am using -mcpu=generic+nosimd flag but, when I run the benchmarks with gem5, stats still show simd operation types. I wonder if anyone has experienced such problem.

Thanks
Ayaz
_______________________________________________
gem5-users mailing list
gem5-users <at> gem5.org
http://m5sim.org/cgi-bin/mailman/listinfo/gem5-users

Gmane