Nizamudheen Ahmed | 2 Sep 17:55 2015
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PW$ in ARM MMU lookup

Hi Champs,

I poured through the TLB and Table-walker code for ARM architecture... The TLB stores the recent translation. The table-walker helps walk the translation table and arrive at the mapped PA for a VA... 

As i understood, the GEM5 code does not seem to implement the page-walk cache. Is my assessment correct? 

The walker port is connected to the mem-bus. Hence, the walks are not cached in L1D caches, either (that could be an architecture decision). I believe the page-table entries are cached only at L2 level. Is that a correct understanding.

Thanks in advance.

BR/Nizam

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Virendra Kumar Pathak | 2 Sep 11:05 2015
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aarch64 (armv8-a) - question on adding a new processor support

Hi gem5 group,

I am new to gem5 and working on adding a new processor (similar to cortex-A57 64bit armv8-a architecture) support in gem5.

Currently I want to boot gem5 with armv8-a aarch64 O3 (out of order) cpu model.
I am using below command:
build/ARM/gem5.opt configs/example/fs.py --kernel= <PATH>vmlinux.aarch64.20140821 --machine-type=VExpress_EMM64  --dtb-file=<PATH>/vexpress.aarch64.20140821.dtb --caches --cpu-type=arm_detailed --disk-image=<PATH>/aarch64-ubuntu-trusty-headless.img

Please guide me on below questions -
  1. Is 'cpu-type=arm_detailed' correct for O3 cpu model for aarch64? It seems 'arm_detailed' is derived from 'O3_ARM_v7a_3', which is further derived from 'O3_ARM_v7a'. Does it mean that 'arm_detailed' is only for armv7-a architecture?
  2. I want to modify instruction latency, number of pipeline stages and functional units, so that gem5 can simulate our processor more accurately. Please provide some starting pointers on the same.
  3. What other factors should be considered while adding new processor support, assuming that we may want to upstream our work to gem5 organization later.
Thanks.

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with regards,
Virendra Kumar Pathak
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Himanshi Garg | 2 Sep 08:06 2015

How to run Timing CPU model in gem5

Hi,

I wanted to run some examples using simple atomic and simple timing model, to 
see the difference between these two in gem5. The mwait example doesnt 
compile and throws this error :
g++: error: pthread.o: No such file or directory

I dont seem to see any visible difference between them when I run hello test.
I want to understand the concept of timing, please suggest how to run it.

Regards,
Himanshi

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‪Niloofar Shakiba‬ ‪ | 1 Sep 20:17 2015
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size of main memory for running PARSEC

hi,
I'm working on a project that i should simulate main memory in c++ to process the traces that i get from running PARSEC.
i want to know if we suppose that there is just main memory without any secondary memory how much memory is needed for running PARSEC?
actually i want to define an array as main memory , and the size of array is limited. so i need the minimum size.
best regards,
Niloofar

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n26001482 | 1 Sep 09:02 2015
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Performance of multi-thread ?

Hi, all.

I wrote a simple multi-thread code and executed it on GEM5 SE mode with 
m5thread. As compared with the sequential code(not multi-thread), the 
performance of multi-thread code is not better. Does anyone try this? Could 
you share your opinions?

Thanks!

BEST.
MY Lin
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Abhishek Rajgadia | 1 Sep 06:34 2015
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ready registers for effAddr

Dear All,
I am new to gem5. I am trying to figure out if memory instructions in the instruction queue have those registers ready which are used for effective address calculation.
How to perform this check?


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Abhishek Rajgadia
Electrical Engineering,
IIT Bombay
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chelin | 1 Sep 01:23 2015
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un-answered read request

HI there

I was doing research about analyzing the communication between components in SoC platform in GEM5. What I
did was add commMonitor between each components and recorded the packet information.

After analyzing what I collected from running a simple write program, I found two read functions that
didn't receive any responses at all. 

One of the read request was sent from cpu1, and after cpu1 sending the storeCondreq to memory bus, and memory
bus sent to memory and cpu0, it just ended like this.
Another instance is after cache received the read request from cpu1, it never send any response back.

Is this a normal behavior for GEM5?

Best,
Yuting
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Dilip Kotadiya | 31 Aug 21:01 2015
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Problems installing gem5 on Ubuntu

Hello,
I am trying to install gem5 on a Ubuntu system and I am getting some errors while building it. I have attached the errors I am getting.

It would be great if you can help me with this errors.

Thank you 
Dilip Kotadiya
Attachment (nohup.out): application/octet-stream, 16 KiB
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Abhishek Rajgadia | 31 Aug 20:42 2015
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calcEA() function crashes

Dear All,
I am trying to compute effective address by calling  calcEA() given in src/cpu/o3/dyn_inst.hh . But when i call this function, it gives a segmentation fault. This is because the pointer used inside the function points to NULL. What changes should I make to compute Effective Address.

I am new to gem5. I would be obliged for your help.

Regards,
Abhishek

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Parvathy N | 31 Aug 17:34 2015
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TLB documentation

Hi all
                   Where can i find documentation for  TLB ( x86 architecture ). I am unable to understand much from the code. I just started gem5 with this.If somebody can give documentation,it would really help!

Thanks in advance

Regards
Parvathy
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Yu Gan | 28 Aug 22:52 2015
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A possible bug in gem5

Hi,

I think there is a possible bug in gem5/src/mem/ruby/common/Set.hh:69

69    static const int LONG_BITS =
70        std::numeric_limits<unsigned long>::digits + 1;
71   static const int INDEX_SHIFT = LONG_BITS == 64 ? 6 : 5;
72    static const int INDEX_MASK = (1 << INDEX_SHIFT) - 1;

There was a bug fix in 2011, stating that <unsigned long>::digits was either 31 or 63, so they added by 1 to make LONG_BITS=64 (https://www.mail-archive.com/gem5-dev <at> gem5.org/msg00004.html). But now, <unsigned long>::digits already equals to 32 or 64, possibly because of the renewal of g++ or c/c++ library. I don't know if the problem universally exists but for me and other desktops with Python 2.7.10 and gcc/g++ 4.9.2, I will get the value of LONG_BITS equal to 65.

In addition, in gem5/src/mem/ruby/common/Set.hh:51

51   const int NUMBER_WORDS_PER_SET = 1;

The comment suggests that the default value should be 4, but somehow it is current 1. My system with more than 32 traffic generators will brake down when it's set to be 1 due to the overflow error. I think changing it to the default value is better because we will at least not encounter any error with a larger value. Or we can just fix the comments in case there are some misunderstanding on it and tell people to increase it when they want more cores in a more explicit way. I am not sure but I just guess when increase it by one, you can have 32 more cores supported.

Best regards,
--
Yu Gan
Research Intern
CSE Department, University of Michigan, Ann Arbor
Undergraduate Student
Department of EE, Tsinghua University, Beijing, China
TEL: 1 (734) 834-2395
        (86) 15652775983
Email: yugan <at> umich.edu
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Gmane