Murat Koksal | 26 May 22:20 2016
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Cache properties

Hello,

I am trying to find certain information about the caches employed in se.py. I am aware that some configuration options are available in gem5/configs/common/Caches.py file, but so far I haven't found what I am looking for. I was wondering if anybody could direct me in the right direction. What I would like to know is

1) where is it specified that a cache uses physical/virtual addresses for indices/tags, and
2) what happens to the cache contents upon a syscall?

Thanks.

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Renju Boben | 26 May 10:40 2016
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n155 register

Hi,
    What is the equivalent register of n155(used in gem5) in actual x86 architecture?

Thanks in advance

Regards,
Renju Boben
M Tech
Electronic Systems
IIT Bombay
Ph - 7506112155
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Ejjeh, Adel | 24 May 17:37 2016

Get gem5 CPU pipeline configuration

Hi All

I am new to gem5, and I am trying to extract from a simulation that I ran (using SE mode) the details of the pipeline configuration. Where can I find things like the pipe stage widths?

Thanks!
Adel


--
Adel Ejjeh
PhD Student | Computer Science
University of Illinois at Urbana-Champaign
Siebel Center for Computer Science
201 N Goodwin Ave, Urbana, IL 61801

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mengyu liang | 24 May 14:08 2016
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Is it possible to simulate a network system on classic memory system?

Hello everyone,

I'm still trying to simulate a network structure using gem5. In this structure, I want to create several clusters, which encompasses multiple cpus, separate L1s to each CPU and a shared L2 cache. Those clusters are further connected with network topology. The structure is as following:
cluster1(cpus->L1s->Xbar->shared L2)->NOC
cluster2(cpus->L1s->Xbar->shared L2)->NOC
......

Instead of Ruby network system, I now prefer the classic one. Because in classical system the cache coherency MOESI snooping is used, which has allegedly much better flexibility in cache hierarchy than those protocols in Ruby. Moreover in classic memory system, I don't have to deal with complex objects such as sequencer, l1 controller, directory controller, etc. as in Ruby.

But now the problem is, is it possible to connect L2 cache directly to the router of NOC topology (e.g. MESH, Crossbar, ...)? I'm not sure if such connection is supported by functionality of router. In Ruby, it seems that network nodes (l1 controller, dma controller, directory controller, etc.) communicates via message buffer. However no message buffer is used in classic memory system. Therefore I doubt if my simulation can succeed by just implementing those (topology).py into my main configuration file. But at least, the documentation on gem5.org didn't say NO to network simulation on classic memory system.

Does anybody have an idea? An easy but definite YES/NO answer will also help me a lot.

Thanks,
Mengyu
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李益昌 | 23 May 21:10 2016
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Frame buffer & LCD display simulation in gem5

Hi all,

I am wondering if Gem5 support any simulation for Frame buffer and LCD display like timing simulation or power simulation. Is it for SE mode or FS mode?

Thanks,
YiChung 
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Anirudh Kaushik | 21 May 20:32 2016
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Ruby tester coherence protocol

Hi,

I am trying to validate a home-brewed cache coherence protocol using
the ruby tester. For a single core, I can validate for a large number
of loads. However, when I test it with 2 or more cores, I get the
following error:

Error: could not create sytem for ruby protocol..

It looks like this problem exists even for the protocols provided in
the repository such as MOESI_hammer. It works for a single core but
not for multi-cores. I am running the ruby tester using the following
command:
build/X86_MOESI_HMMER/gem5.opt ./configs/example/ruby_random_test.py --ruby -n 2

Any suggestions or hints would be useful.

Thanks
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Tanmay Gangwani | 20 May 08:00 2016
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Snoop filter capacity exceeded!

Hi,

I am running a 64-thread program in SE mode. My memory hierarchy is configured to have private instruction and data L1s, and one single L2 (connected to the L2XBar on the cpu-side and SystemXBar on the mem-side). The program runs fine upto 16 threads. For 32 threads, I get the following error at the start of the simulation :

fatal condition id > 8 * sizeof(SnoopMask) occurred: Snoop filter only supports 64 snooping ports, got 128

Could someone provide pointers on how to proceed with this?

Also, is it possible to set up a shared distributed (sliced) L2 in SE mode?


Thanks,

Tanmay

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Shail Dave | 19 May 22:26 2016
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How To Compile And Link C File (uses pthreads) To Get Binary For ARM Using m5threads (GEM5 SE)

Hi,

Hope you are doing good. I am trying to execute two pthreads on gem5 in SE mode.  What I want is to run two light-weight threads on gem5 in SE mode. So I found m5threads. But, I am unsure that how I should compile and link my test file with m5threads (I want to test basically creation and joining of 2 threads several times or wait and execute 2 threads through conditional signaling).

I am not finding the exact information and struggling to progress about how I should compile and execute a file test.c . I want to execute it on ARM ISA in gem5 and I want to have binary generated through arm cross compiler.  I am appending my attempt for given test program in m5threads for your kind reference.
------------------------------------------------------------------------------------------------
My attempt: (For Sample File test_pthreadbasic.cpp in m5threads/tests/)

cd ~/
cd m5threads/

make
cd ~/m5threads/tests/
arm-linux-gnueabi-g++ -c test_pthreadbasic.cpp -I ~/gem5/util/m5/ --static
arm-linux-gnueabi-g++ -o test_pthreadbasic test_pthreadbasic.o ../pthread.o ~/gem5/util/m5/m5op_arm.S -I ~/gem5/util/m5/ --static or
arm-linux-gnueabi-g++ test_pthreadbasic.cpp -I ~/gem5/util/m5/ ~/gem5/util/m5/m5op_arm.S -static ~/m5threads/libpthread.a -o test_temp)

I am getting an error as 

/home/shail/m5threads/libpthread.a: error adding symbols: File format not recognized    collect2: error: ld returned 1 exit status
------------------------------------------------------------------------------------------------

It would be great if I can know what command exactly should I apply to get binary for ARM with simple c/cpp file.  Thank you very much!

Best Regards,
Shail

=========================================

Shail Dave
Research Assistant, Compiler Micro-architecture Lab
Graduate Student, Computer Engineering
Ira A. Fulton Schools of Engineering 
Arizona State University
Shail Dave, ASU Directory Profile
=========================================

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Renju Boben | 19 May 19:43 2016
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gem5 - Very low no. of committed instructions

Hi,
    I am running mcf benchmarks, from SPEC 2006. To verify the progress I am dumping the stats after every 1000000000000 ticks. Initially it is simulating without any issues. After some time I am getting the following stats repeatedly 

sim_insts                                 10997285  # Number of instructions simulated
system.cpu.committedInsts  0               # Number of instructions committed

   For hmmer benchmarks also the system.cpu.committedInsts  is less than 10 instructions for 1000000000000 ticks, most of the time. Sometimes it becomes 5000 instruction for the same no. of ticks. 
   
  Does any one know the reason for this anomaly?

Thanks in advance

Regards,
Renju Boben
M Tech
Electronic Systems
IIT Bombay
Ph - 7506112155
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anoir nechi | 19 May 12:36 2016
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Multiple CPU's in GEM5


I'm trying to configure a system with multiple CPU's using gem5 ... i looked for some examples with multiple CPU's but i did not find any, So, i tried one myself but it looks that my essay is wrong, could someone put me in right direction please,

This is my first try:

system=System() system.clk_domain=SrcClockDomain() system.clk_domain.clock='1GHz' system.clk_domain.voltage_domain=VoltageDomain() system.mem_mode='timing' system.mem_ranges=[AddrRange('512MB')] system.cpu_1=TimingSimpleCPU() system.cpu_2=TimingSimpleCPU() system.sys_bus=CoherentXBar() system.cpu_1.icache_port=system.sys_bus.slave system.cpu_1.dcache_port=system.sys_bus.slave system.cpu_2.icache_port=system.sys_bus.slave system.cpu_2.dcache_port=system.sys_bus.slave

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Ayaz Akram | 17 May 19:43 2016
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Physical Address of Instructions

I wonder if there is a way to get the physical address of an instruction itself at commit stage. DynInst provides methods to get physical address of memory access but, I am not able to figure out a way to get physical address of instructions when they commit . Did someone try something similar ? (I am working with full system mode).

Thanks for you time !

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