Kuk-Hwan Kim | 19 Apr 03:10 2014

[Simple Question on the kernel display]


Dear Gem5 Community, 

I have simple questions, I used m5term to connect to simulator. I guess the
messages printed in the display is from "printk" statement in the C++ source
file. I am just wonder if what is the information on the numbers inside [  
2.250590 ] ? 

Any information or insight to interpret the following information would be
greatly appreciated. Thank you for your help in advance,

Regards
Kuk-Hwan

VFS: Mounted root (ext2 filesystem) on device 8:1.
[    2.250590] VFS: Mounted root (ext2 filesystem) on device 8:1.
<6>Freeing init memory: 148K
[    2.250604] Freeing init memory: 148K
<3>init: cannot open '/initlogo.rle'
[    2.265621] init: cannot open '/initlogo.rle'
<3>init: cannot find '/system/etc/install-recovery.sh', disabling
'flash_recovery'
[    2.274298] init: cannot find '/system/etc/install-recovery.sh',
disabling 'flash_recovery'
<3>init: using deprecated syntax for specifying property
'persist.sys.usb.config', use ${name} instead
[    2.274393] init: using deprecated syntax for specifying property
'persist.sys.usb.config', use ${name} instead
<3>init: using deprecated syntax for specifying property 'sys.usb.config',
use ${name} instead
(Continue reading)

Kuk-Hwan Kim | 19 Apr 02:58 2014

[trace options?


Dear Gem5 community, 

My simulation (there are some modification on Caches.py and CachesConfig.py
from originally downloaded gem5 files) is showing panic in kernel. So, I
would like to generate traces from caches by using following command line.
It showed that --trace-start is not appropriate option. My questions is

1) What is the file which define --trace-start ?
2) if --trace-start is not working?, how other gem5 community member use
trace information for their own sake?

Any help or information would be greatly appreciated. Thank you for your
help in advance,

Regards
Kuk-Hwan

gem5.opt: error: no such option: --trace-start
root <at> ubuntu:/mnt/lnx-arch/gem5# ./build/ARM/gem5.opt
--debug-flag=Fetch,Ethernet,TLB,DMA,Bus,Cache,O3CPUAll --trace-start=300
--trace-file=my_trace.out --stats-file=./L2cahce.txt ./configs/example/fs.py
--kernel=../../asimbench/asimbench_android_arm_kernel
/vmlinux.smp.ics.arm.asimbench.2.6.35
--disk-image=../../asimbench/asimbench_disk_image/ARMv7a-
ICS-Android.SMP.Asimbench-v3.img
--mem-size=128MB --l2cache --caches

Usage
=====
(Continue reading)

anonymous | 19 Apr 01:04 2014
Picon

Prefetcher / Cache Address

Hi, 

I am attempting to write a custom Prefetcher.
However I am having some significant difficulties.
 Particuarlly during the development. 

I have added a new fetcher (right now a copy of Tagged.cc/.hh)
recompiled gem5 and added it to CacheConfig.py and it links fine
I can turn on HWPrefetch debug and see a custom message
I added into the code so add good here. 

My problem is 2 fold.

First I want to ensure I am printing the request data correctly, 
 Addr blkAddr = pkt->getAddr() & ~(Addr)(blkSize-1);

 Addr data_addr = pkt->getAddr();

DPRINTF(HWPrefetch, "BlockAddr %x data_addr %x Data: %x %s\n",
 blkAddr, data_addr,*(pkt->
getPtr<uint8_t>()))

Secondly if I translate this address say data_addr+8 
how can I view the data at this location? It 
doesn't seem possible to make sure I am accessing the correct data?

Any help would be greatly appreciated thank you
Picon

ruby_random_test with prefetcher

Hi everyone,

I based my work on the MESI protocol to develop my own coherence protocol and I am running
ruby_random_test.py for the verification, however I noted that there are only requests from the
sequencer (Ifetch, Load, and Store) but not from the prefetcher (PF_Load, PF_Ifetch, PF_Store).

I made sure that enable_prefetch=True in MESI_CMP_directory.py and MESI_CMP_directory-L1cache.sm
Actually when see the traces after running a ruby_fs.py simulation I can see the occurrence of events due to
the prefetcher which makes e think that this problem is not because the changes I did.

I dig into the code and found in src/cpu/testers/rubytest/Check.cc:60 which will never be executed and
where apparently the prefetch is initiated. I modified that line to support prefetches but Im getting
more errors.

Is that the best way to make ruby_random_test support prefetchers?

--

-- 
Alberto Javier Naranjo-Carmona
M.S. Student Computer Engineering
tanmayGadre | 18 Apr 17:49 2014
Picon

RUNNING SPEC 2006 BENCHMARKS

I want to run SPEC 2006 BENCHMARK FOR SE mode in gem5 . 
I read some documentation on this page : 
http://www.m5sim.org/SPEC2006_benchmarks

What id the DVD that they are talking about ?

Has anybody run the above benchmark ?if yes  , please mention the details
Kuk-Hwan Kim | 17 Apr 20:25 2014

[How to create separate stats.files with different names]


Dear Gem5 community,

I would like to run all the asimbenchmark application in one script file. 

let's say, I would like to create separate stats.file with different name as
a result of one particular benchmark software execution. Following examples
are running two software packages and put their stats in the same file.. But
I would like to create two separate files as a result of two benchmark
software run. 

#!/system/bin/sh

stop_m5() {
    /sbin/m5 exit

    return
}

wait_stop() {

        busybox usleep 2000000
        run_var=1
        run_related=1
        while [ $run_var -eq 1 ]
        do
                #counter=$(busybox ps -o user,stat,args -T | busybox grep
'10061' | busybox grep -v 'S' | busybox wc -l)
                if [$run_related -eq 1 ]
                then
(Continue reading)

Picon

Dynamic Cache Partitioning on Shared L2/L3 cache

Hi Team, I would like to partition the shared L2/LLC cache in a certain way so that one core could use more L2 cache comparing with the other ones, could anyone suggest a good way to implement this?


--
Thanks and Regards
Pavan Kumar Reddy K

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Kuk-Hwan Kim | 17 Apr 10:36 2014

Two questions - Cortex-M3 model and PARSEC 3.0 ported to ARMv7a


Dear Gem5 community,

I have simple two questions.

1. Do we have gem5 models which is similar to Cortex-M3 core + on-chip SRAM 
+ on-chip flash? If not, what would be the most efficient building out of 
currently available component sets? Cortex-M3 has in-order CPU. 

2. PARSEC 3.0 for ARM

I am looking forwards to have PARSEC 3.0 benchmark binaries ported to 
ARMv7a. 

As described in the following website, 
http://gem5.org/PARSEC_benchmarks

arm-system-2011-08.tar.bz2 supposed to have 11 applications compiled to 
ARMv7 binaries. But I couldn't find the benchmark binaries inside the disk 
image file? Did I download wrong file or the post is not currently 
reflecting reality? 

Any information or recommendation would be greatly appreciated

Regards
Kuk-Hwan
Srinivasan Narayanamoorthy | 17 Apr 05:25 2014
Picon

ARM WFI implementation

Hi all,

I am trying to run some android benchmarks in gem5 and often, the cpu is put to sleep by executing a 'WFI'(Wait
for interrupt) instruction. The task requires me to take checkpoints frequently during program execution.

I found that when performing drain before writing the checkpoint, all cores (cpu0,cpu1,cpu3) except the
one which has executed WFI(cpu2), drain successfully. The WFI core does not drain at all since other cores
cannot interrupt to wake the sleeping core (because they are drained). 

As a stop gap solution, I am calling the wakeup() routine in cpu.cc during drain operation. Though this
solution does not cause any immediate problems, this does not appear to be a good solution as there may be
other cases that might break. 

I would be very grateful if a solution is suggested.

Thanks
Srini
Hadi | 17 Apr 04:51 2014
Picon

fatal: Unable to find destination addr

Hi,

I was trying to run Spec2006 benchmarks with OoO + Ruby + MESI with numerous frequencies. I have a single checkpoint for each benchmark (for example Calculix), my simulation works for all frequencies except 2.2GHz. This happens to other frequencies in other applications (gcc, tonto, ...). Following is the error I get:

fatal: Unable to find destination for addr 0x21767480 on bus system.piobus
  <at> cycle 9286964138000
[findPort:build/X86_MESI_CMP_directory/mem/bus.cc, line 353]

Could someone please help me on this error.

Thank you

Hadi Moghaddam
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Vanchinathan Venkataramani | 16 Apr 06:14 2014
Picon

Sharing LoadStoreQueue

Hi all

I am trying to share the load store queue across CPUs in gem5.

Since loadStoreQueue is an object in IEW stage, I'm not sure how it can be shared across CPUs.

I would like to know if there is a way to do this.

Thanks a lot in advance.
V Vanchinathan
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Gmane