Dimitri Sotnik | 29 Nov 12:16 2015

Ruby Trace

Hi all,

I want to trace the Interconnection Network in Ruby on Alpha_Moesi_hammer_FS. Can someone tell me where I
have to connect the CommMonitor? Or is there another way for tracing in Ruby?

Thanks in advance

Dimitri S.
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Pierre-Yves Péneau | 27 Nov 11:43 2015

Number of write in L2 cache

Hi all,

I would like to know the amount of write accesses in the l2 cache. I am
using the current version. Before some changes, there was one line in
the stats file with this information:


Now, there is two parameters :


Do I have to add those values to get my information ? To Thank you.

Best regards.


| Pierre-Yves Péneau            |  first.last at lirmm.fr  |
| PhD student - LIRMM - Sysmic  |    + 33 4 67 41 85 85    |
| Bâtiment 4 Bureau H2.2        |    http://walafc0.org    |

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(Continue reading)

Hongce Zhang | 26 Nov 16:28 2015

Check Failure and Panic for ruby_random_test

Hi, all!

Happy Thanksgiving!

I'm new to Gem5, and as I ran ruby_random_test as the Wiki: http://www.m5sim.org/Interconnection_Network, with the following command,

./build/ALPHA/gem5.debug \ configs/example/ruby_random_test.py \ --num-cpus=16 \ --num-dirs=16 \ --topology=Mesh \ --mesh-rows=4 \ --garnet-network=fixed

I got the message

panic: Action/check failure: proc: 2 address: 14056 data: 0x3a5a2f0 byte_number: 0 m_value+byte_number: 120 byte: 202 [14056, value: 120, status: Check_Pending, initiating node: 8, store_count: 4]Time: 1523
  <at> tick 1523
[performCallback:build/ALPHA_Network_test/cpu/testers/rubytest/Check.cc, line 309]

It seems that there is inconsistency in the message, but it is a fresh build and I didn't tweak anything. So I'd like to ask, what's wrong and how to fix it.

Thanks a lot!

Warm regards,
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Tod | 26 Nov 11:23 2015

How to get number of clock cycles (gem5 ticks) for ROI


I am interested to get the number of clock cycles (gem5 ticks) taken by a region of code in gem5 FS mode. 

For example, if the following is my code snippet:

int main() { int i; int j = 10; pt.1 for( i = 0; i <= j; i ++ ) { if( i == 5 ) { continue; } printf("Hello %d\n", i ); }pt.2 return 0;}

How can I know the gem5 tick value at pt.1 (i.e. before entering ROI) and at pt.2 (i.e. after leaving ROI)?


In other words, how many clock cycles will it take in ROI?



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Kaiyuan | 26 Nov 09:20 2015

Problem when running FS gem5 in kernel for arm I build

I am trying to build kernel for ARM from source code and running it by gem5 FS mode.

I follow this guide http://gem5.org/ARM_Linux_Kernel 

But results show error like follows:

~/src/gem5-stable $ build/ARM/gem5.debug configs/example/fs.py --machine-type=VExpress_EMM --mem-size=512MB --caches --cpu-type=MinorCPU --kernel=vmlinux --disk-image=rootfs.img.gz
gem5 Simulator System.  http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.

gem5 compiled Nov  5 2015 11:15:35
gem5 started Nov 26 2015 16:09:41
gem5 executing on kail-kern
command line: build/ARM/gem5.debug configs/example/fs.py --mem-size=512MB --caches --cpu-type=MinorCPU --kernel=vmlinux --disk-image=rootfs.img.gz

Global frequency set at 1000000000000 ticks per second
warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes)
info: kernel located at: /home/kail/test/ARM/binaries/vmlinux
Listening for system connection on port 5900
Listening for system connection on port 3456
0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
info: Using bootloader at address 0x10
info: Using kernel entry physical address at 0x80008000
warn: DTB file specified, but no device tree support in kernel
warn: Existing EnergyCtrl, but no enabled DVFSHandler found.
info: Entering event queue <at> 0.  Starting simulation...
warn: Device system.membus.badaddr_responder accessed by read to address 0x101f1018 size=4
fatal: Received error response packet for inst: 0/12.4/25/113.116 pc: 0x8001a098 (ldr)
  <at> tick 1429000
[handleMemResponse:build/ARM/cpu/minor/execute.cc, line 349]
Memory Usage: 772708 KBytes
Program aborted at cycle 1429000
Aborted (core dumped)

I don't know how to resolve this problem. Could anyone give me some suggestions?


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| 26 Nov 04:02 2015

PMU not counted in gem5


  When I use the perf to collect pmu counters in gem5, it says some counters is not counted in gem5. And after I read the gem5 source code, I find the pmu module in gem5 is disabled, so how can i enable the pmu module and add pmu counters. Thanks.

Best Regards
Kong Weiguang



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Qingsen Wang | 26 Nov 02:56 2015

Some questions about cache


I have some quick questions about cache.

1. For the cache configuration (as shown below from configs\common\Caches.py), what is the unit of latency? Is it in nano-seconds or cycles?
class L2Cache(BaseCache):
    assoc = 8
    hit_latency = 20
    response_latency = 20
    mshrs = 20
    tgts_per_mshr = 12
    write_buffers = 8

2. What is the difference between hit_latency and response latency? (Some one has asked this question before but I still can't find the answer)

3. As in the result file stats.txt, I found 
system.l2.overall_avg_miss_latency::total   83965.126869  # average overall miss latency
  Similar to the first question, what is the unit of the value  83965.126869 ?

Thanks in advance for anyone's help!

Have a great day! (Or have a good holiday if you in US)

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Uzair Sharif | 25 Nov 11:36 2015

gem5-users <at> gem5.org


Is it possible that I can hook CPU model within full system to SystemC?? I have gone through util/tlm example but that hooks the mem_bus to SystemC module. 

Can I just simply disable all caches, membus, mem_ctrls and connect CPU's icache_port, dcache_port to ExternalSlave (like in the TLM example) and implement the entire memory system functionality in SystemC?? What should I be careful about in doing this??


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Ejjeh, Adel | 25 Nov 01:35 2015

Error: not enough memory

Hi all. I’m trying to simulate a C application that I compiled for arm using arm-gcc on the gem5 arm simulator. When I run gem5 I get the following error (almost a quarter through the execution of the program):
*** Error: Not enough memory

Any way I can solve that?

Adel Ejjeh
PhD Student | Computer Science
University of Illinois at Urbana-Champaign
Siebel Center for Computer Science
201 N Goodwin Ave, Urbana, IL 61801

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Arthur Perais | 24 Nov 22:51 2015

x86 Instruction missing serialize flag

Hello gem5 users (more specifically x86 users),

I ran into an issue today where the panic in tlb.cc (line 225) is 
triggered by a WRMSR (write model specific register) that writes to some 
bogus address because it is on the wrong path.

The Intel manual states that "The WRMSR instruction is a serializing 
instruction (see "Serializing Instructions" in Chapter 8 of the IA-32 
Intel Architecture Software Developer's Manual, Volume 3)." and the 
microcode in src/arch/x86/isa/insts/system/msrs.py declares the WRMSR 
macroop as serializing, but the O3 model considers it to be 
SerializeAfter only, while it should also wait for all previous 
instructions to have executed (so be SerializeBefore).

I'm not yet clear if this is a flag missing in the instruction object or 
if this is due to the way Rename handles the instruction (looks like the 
former though).

So I am merely wondering if someone else ran into the issue, and I will 
try to check if the problem arises on newer versions of gem5, but the 
src/arch/x86/isa/insts/system/msrs.py did not change between head and 
the revision I use. If it has already been caught/fixed then my bad (I 
did not really find anything related on the mailing list).



Arthur Perais
INRIA Bretagne Atlantique
Bâtiment 12E, Bureau E303, Campus de Beaulieu
35042 Rennes, France

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Louisa Bessad | 23 Nov 22:25 2015


Hash: SHA256


I want to implement two ARM cores in gem5: one Cortex-A53 and one 
Cortex-A57. I was wondering if it has been already done or if you have
some informations about this subject.

Thank you.

Best regards.

| Louisa Bessad                 |  
| PhD student - LIRMM - Sysmic  |
| Bâtiment 4 Bureau H2.2        |

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