Dimitar Dobrev | 22 Jul 20:09 2014
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How to get the symbols from a .so file?


    Hello all,

    I develop a project based on Clang where I need to read all symbols from a library. For symbols libraries (.a/.lib) I use the following code:

    auto &FM = C->getFileManager();
    ...
    auto Buffer = FM.getBufferForFile(FileEntry);
    ...
    auto Object = llvm::object::ObjectFile::createObjectFile(Buffer);

    This code crashes at the last line if the file in question is a shared object (.so). Apparently I need to use different code to parse a shared object but I have little idea what. Any help will be appreciated.

    Thank you for your time,
    Dimitar Dobrev

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Francis ANDRE | 22 Jul 15:16 2014
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[LLVMDev][3.5]: assertion failed in RuntimeDyldELF.cpp

Hi LLVMDev list

I am building LLVM from the SVN trunk at 213638 on a W7/X86_64/Cygwin 
system and running make check leads to a series of failed assertions like

********************
FAIL: LLVM :: ExecutionEngine/MCJIT/test-setcond-fp.ll (6185 of 11245)
******************** TEST 'LLVM :: 
ExecutionEngine/MCJIT/test-setcond-fp.ll' FAILED ********************
Script:
--
/cygdrive/z/dev/llvm/x64/static/Release+Asserts/bin/lli -use-mcjit 
-mtriple=x86_64-unknown-cygwin-elf 
/cygdrive/z/dev/llvm/x64/llvm/test/ExecutionEngine/MCJIT/test-setcond-fp.ll 
 > /dev/null
--
Exit Code: 134

Command Output (stderr):
--
assertion "RealOffset <= INT32_MAX && RealOffset >= INT32_MIN" failed: 
file 
"/cygdrive/z/dev/llvm/x64/llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp", 
line 308, function: void 
llvm::RuntimeDyldELF::resolveX86_64Relocation(const llvm::SectionEntry&, 
uint64_t, uint64_t, uint32_t, int64_t, uint64_t)
Stack dump:
0.      Program arguments: 
/cygdrive/z/dev/llvm/x64/static/Release+Asserts/bin/lli -use-mcjit 
-mtriple=x86_64-unknown-cygwin-elf

/cygdrive/z/dev/llvm/x64/llvm/test/ExecutionEngine/MCJIT/test-setcond-fp.ll
/cygdrive/z/dev/llvm/x64/static/test/ExecutionEngine/MCJIT/Output/test-setcond-fp.ll.script: 
line 1:  5552 Aborted 
/cygdrive/z/dev/llvm/x64/static/Release+Asserts/bin/lli -use-mcjit 
-mtriple=x86_64-unknown-cygwin-elf 
/cygdrive/z/dev/llvm/x64/llvm/test/ExecutionEngine/MCJIT/test-setcond-fp.ll 
 > /dev/null

--

How could I deal with the configuration of LLVM to avoid such assertion 
error?

FA
Renato Golin | 22 Jul 23:15 2014

Sanitizer test failure

I'm compiling compiler-rt via CMake+Ninja on x86_64+ArchLinux and one
of the tests fails on ToT:

MemorySanitizer :: chained_origin_with_signals.cc

The text expects uninitialized warnings while the execution prints
nothing, thus FileCheck fails.

Anyone seeing this?

cheers,
--renato
Dan Liew | 22 Jul 16:27 2014
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Policy and advise for working with LLVM release branch with git-svn

Hi,

I noticed that the LLVM 3.5 release branch landed recently.

I have a few patches (these are all part of my recent work to fix up
the CMake interface) that I'd like in both LLVM3.5 release branch and
trunk that I'd like to commit

Is there any policy on how should do this be done, or can I just
commit the patch to both trunk and then the release branch with
identical commit messages? Or should these be the same commit (I think
SVN lets you do this...)

I'm also currently using git-svn to push to trunk by following [1].
There isn't any advise there about working with the release branches.
I have never pushed to a svn branch from git-svn before I'd like to
not screw this up.

Should I

- Just use svn for committing to the release branch
- Create a new git repository on my local machine and set it up in [1]
but use the release URL instead of trunk
- Do some kind of magic so I can continue to use existing LLVM git
repository and be able to push either trunk or the release branch
- Something else...
?

[1] http://llvm.org/docs/GettingStarted.html#for-developers-to-work-with-git-svn

Thanks,
Dan
Thomas Ströder | 22 Jul 13:06 2014
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Picon

Publication "Proving Termination and Memory Safety for Programs with Pointer Arithmetic" at IJCAR 2014

Dear all,

We have recently published a paper at the International Joint Conference 
on Automated Reasoning (IJCAR) being held in Vienna, Austria in July 
2014 as part of the Vienna Summer of Logic (VSL, http://vsl2014.at/) on 
fully automated termination and memory-safety analysis of programs 
involving pointer arithmetic based on LLVM. The title is "Proving 
Termination and Memory Safety for Programs with Pointer Arithmetic" and 
the authors are Thomas Ströder, Jürgen Giesl, Marc Brockschmidt, Florian 
Frohn, Carsten Fuhs, Jera Hensel, and Peter Schneider-Kamp. You can find 
the paper at this link:

http://link.springer.com/chapter/10.1007%2F978-3-319-08587-6_15

A preprint is also available at our own website:

http://verify.rwth-aachen.de/giesl/papers/IJCAR14-LLVM.pdf

We would be happy if you could add this paper to the list of LLVM 
Related Publications.

Thank you very much,

   Thomas

--

-- 
Thomas Ströder        mailto:stroeder <at> informatik.rwth-aachen.de
LuFG Informatik 2     http://verify.rwth-aachen.de/stroeder
RWTH Aachen           phone: +49 241 80-21241
Vasileios Koutsoumpos | 22 Jul 12:59 2014
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InsertElementInst and ExtractElementInst

Hello,

I am create a <3 x i32> vector in LLVM IR. Then I insert 3 instructions 
and later on I try to load one instruction from the vector. The 
insertion seems to work, however, when I try to load a specific 
instruction from a vector I seems that it does not work.

This is the part of my IR:

%"ins or1" = insertelement <3 x i32> undef, i32 %38, i32 0
%"ins and2" = insertelement <3 x i32> undef, i32 %41, i32 1
%"ins xor3" = insertelement <3 x i32> undef, i32 %43, i32 2
%extract4 = extractelement <3 x i32> undef, i32 %35
...
store i32 %extract4, i32* %46, align 4

The output of my program is different that the expected one, like the 
extractelement takes an undefined value.

The instructions I used are:
Instruction *Insert0 = InsertElementInst::Create(vector, Or_set, index0, 
"ins or");
..
Instruction *extract = ExtractElementInst::Create(vector, ch, 
"extract"); //where ch takes a value from 0 to 2
instr->replaceAllUsesWith(extract); //where I want to replace the instr 
instruction with the instruction from the vector.

I am new in the LLVM and I am not sure if I have done something wrong. 
Any suggestions are welcomed.

Regards,
Vasilis
Brian Faull | 21 Jul 22:33 2014

VMKit build problems; can't use LLVM3.4.2 ?

Greetings,

I've been using LLVM and Clang for some time, but I'm new to the list and new to VMKit; please advise if I should
post this elsewhere.

VMKit doesn't seem to build with LLVM/Clang 3.4.2 -- seems that one must use LLVM3.3.  I see the following error:

VmkitGCPrinter.cpp:363:53: error: too many arguments to function call, expected 2, have 3
      AP.OutStreamer.EmitValue(address, IntPtrSize, 0);

I now see the vmkit build instructions (http://vmkit.llvm.org/get_started.html) explicitly say to use
LLVM and Clang 3.3; using that version fixes the above.  It seems to be that the signature of (at least) one
function from the LLVM library (e.g., llvm/MC/MCStreamer.h::EmitValue(...)) changed from LLVM 3.3 =>
3.4.2 .  

Is there any plan to migrate vmkit to build to build against LLVM >= 3.4.2 ?  This is probably disruptive (ABI
breakage?) but seems prudent; perhaps there are other fundamental problems in this migration.  I'd be
willing to contribute to a 3.4.2-compatible branch if there is one (I don't see an obvious candidate in svn
repo http://llvm.org/svn/llvm-project/vmkit/branches).

Have I got this correct, or I missing something else?

Incidentally, this seems to be the same behavior/problem as reported on 20 January 2014 by neoedmund
(http://lists.cs.uiuc.edu/pipermail/llvmdev/2014-January/069558.html), which is solved by
building using LLVM3.3 (no response seen).

Thank you!
Brian
Richard Gorton | 21 Jul 20:38 2014

need advice on approach for backend (llvm3.4.2)


Hi,

I'm working on a backend for a 64-bit RISC-like architecture; all registers are 64-bits.  I have load/store
granularity of 8/16/32/64 bits (pretty normal stuff), but also 128-bit load/stores (involving a pair of
registers).  Because all registers can be used in integer and float instructions, I only have a single
register class (so far).

I'm trying to figure out a good way to utilize our 128-bit loads/stores - the data  can be in any two 64-bit
registers, but the memory locations must be strongly aligned and adjacent (aka first register to 0mod16
address, 2nd register to 8mod16 address).  The stack is guaranteed to be 0mod16 aligned.

I was thinking of doing this coalescing in CogERgisterInfo::eliminateFrameIndex (Our target == 'CogE')
but then spotted some code  re: register scavenging which could make this problematic.

I also see that there is ARM/ARMLoadStoreOptimizer.cpp, which performs a similar coalescence.

The two questions then:
1) for those of you who are working on retargeting the backend, what approach would you recommend that I use
for this kind of coalescence?
2) What are the pitfalls I am likely to encounter?

Thanks in advance,

	Richard Gorton
	Cognitive Electronics
	www.cog-e.com
Vasileios Koutsoumpos | 21 Jul 16:56 2014
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extract a specific element from a vector in LLVM IR

Hello everybody,

I am creating a vector in llvm IR and I am able to insert and extract 
elements.
However, I want to take a specific index from the vector but I am not 
able to do that. I found in the doxygen the getIndexOperand(), but I 
have an error during the compilation.
The code I use is the following:

Instruction *extract = ExtractElementInst::Create(emptyVec, ch, "extract");
b->getInstList().insertAfter(Insert3, extract);

Value *index_val = extract->getIndexOperand();

The error I get is:
error: ‘class llvm::Instruction’ has no member named ‘getIndexOperand’
Value *index_val = extract->getIndexOperand();

I see that I cannot use the getIndexOperand() in an Instruction Type, 
but only through an ExtractElementInst Type.

Do you have any suggestions to get the elements?

Best Regards,
Vasilis
Zinovy Nis | 21 Jul 16:25 2014
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New AVX512{VL,BW,DQ} features enabled in LLVM

Hi all!

We (Intel compiler team, Moscow) would like to announce enabling in
LLVM/Clang the additional AVX512 instructions, introduced in the
newest release of Intel Architecture Instruction Set Extensions
Programming Reference
(https://software.intel.com/sites/default/files/managed/c6/a9/319433-020.pdf).

This ISA adds 3 new features:

- AVX512VL ("vector length" extension): many of AVX512 instructions
were extended to support %XMM and %YMM registers, not only %ZMM.

- AVX512BW ("byte and word" instructions): new instructions for vector
elements lengths of 8 and 16 bits .

- AVX512DQ ("doubleword and quadword" instructions): new instructions
for vector elements lengths of 32 and 64 bits (those not implemented
in AVX512F).

We've implemented or working on:

- 3 features above (1000+ instructions);

- lowering for many of masked operations , so it can be utilized in vectorizers;

- intrinsics, compatible with those from gcc/icc;

- thousands of encoding and lowering tests for these features;

Contribution details:

- We are going to contribute new features into LLVM/Clang starting today.

- The major contributor and the maintainer of these features in our
team is Robert Khasanov. You may address him your questions on
AVX512{BW,DQ,VL} implementation and support in LLVM.

- Our LLVM patches were kindly reviewed and approved by Elena
Demikhovsky (Intel), the author of AVX512 support in LLVM.

Your feedback is welcome!

More information:

- James Reinders blog post:
https://software.intel.com/en-us/blogs/additional-avx-512-instructions

- SDE emulator supporting new features (use SKX target):
https://software.intel.com/en-us/articles/intel-software-development-emulator

- ISA: https://software.intel.com/sites/default/files/managed/c6/a9/319433-020.pdf

Intel Compiler Team, Moscow.
Haishan | 21 Jul 16:04 2014

Any update for Pre-increment preparation pass in PowerPC?

Hi, Hal
    I read your pass "Pre-increment preparation pass" on LLVM-commits mail-list.
I appreciate your idea in the talking with Andrew.
Recently, I plan to implement a relative pre-increment of memory ops of my back-end in the
stage of LSR(LoopStrengthReduce).
And now, do you have update your thought and code of this pass?
    Any suggestion will be great.
    Thank you very much in advance.
-Haishan
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