1 May 2009 01:10
Re: Disable features
Derek Ou <derek <at> siconix.com>
2009-04-30 23:10:53 GMT
2009-04-30 23:10:53 GMT
Hi, Ben, Ben Warren wrote: > Do you have CONFIG_RESET_PHY_R defined? It forces a call to eth_init(), > which most likely causes the delay you're seeing. Try commenting it out > in your config file. Yes, CONFIG_RESET_PHY_R is defined by default. And I can see it linking to the eth_init and then macb_init which results in the auto-negotiation. I am going to comment it out and test it. But what is the use for this config? Why does ATMEL define it in many of their boards? Thanks, Derek
> It sounds like Shinya has some pretty odd (read "broken") hardware that
> is decoding the registers with a 16 byte stride, although his example
> above shows a 4 byte stride (less broken).
Let me reword:
* my UART registers are located with 16 byte stride.
* The address decoder in my UART block rounds +1/+2/+3 offsets down
to zero offset. Therefore we can't do byte read/write to ns16550
registers properly; i.e. the return value of readb(x + 3) will be
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