Re: PCI express

On Wed, 2007-08-01 at 03:29, robert lazarski wrote:
> Hi all,
> 
> I'm preparing u-boot for my custom MPC8548E board which is arriving
> soon. Here's my memory map:
> 
> 0x0000_0000     0x7fff_ffff     DDR                     2G
> 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
> 0xa000_0000     0xbfff_ffff     PCI2 MEM                512M
> 0xe000_0000     0xe000_ffff     CCSR                    1M
> 0xe200_0000     0xe20f_ffff     PCI1 IO                 1M
> 0xe210_0000     0xe21f_ffff     PCI2 IO                 1M
> 0xf800_0000     0xffff_ffff     FLASH (boot bank)       128M
> 
> We also have a PCI-X . Are TLB and LAW entries required for PCI-X ?
You do not need to specify TLB/LAW for PCI-X. it uses the same memory
map as PCI1. Check the manual.  
> I've seen some PCI-X stuff in the u-boot distro CPU and Driver
> section, but nothing much in the board section. Any clarification on
> what, if anything, is needed for u-boot to setup on a custom board
> with PCI-X would be appreciated.
PCI-X should use the same stuff as PCI1.
Roy

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atmel at91sam9260 error"undefined reference to 'raise'"

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Re: atmel at91sam9260 error"undefined reference to 'raise'"

In message <OF4D5133B8.79ED2FA9-ONC225732A.001B3B70-C325732A.0015A680 <at> visonic.com> you wrote:
> 
> I am trying to build u-boot using buildroot toolchain for the atmel 
> AT91SAM9260EK cpu with the following configuration:

This is completely off topic here.

> --=_alternative 0015A67DC325732A_=
> Content-Type: text/html; charset="US-ASCII"

Also, HTML is forbidden here.

Best regards,

Wolfgang Denk

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[PATCH] mpc83xx: Correct the burst length for DDR2 with 32 bits

The burst length should be 4 for DDR2 with 32 bits bus

Signed-off-by: Dave Liu<daveliu <at> freescale.com>
---
 cpu/mpc83xx/spd_sdram.c |    8 ++++++--
 1 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 647813f..5e89add 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
 <at>  <at>  -730,8 +730,12  <at>  <at>  long int spd_sdram()
 		sdram_cfg |= 0x10000000;

 	/* The DIMM is 32bit width */
-	if (spd.dataw_lsb == 0x20)
-		sdram_cfg |= 0x000C0000;
+	if (spd.dataw_lsb == 0x20) {
+		if (spd.mem_type == SPD_MEMTYPE_DDR)
+			sdram_cfg |= 0x000C0000;
+		if (spd.mem_type == SPD_MEMTYPE_DDR2)
+			sdram_cfg |= 0x00080000;
+	}

 	ddrc_ecc_enable = 0;

--

-- 
1.5.3.rc2.29.gc4640f

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[PATCH] mpc83xx: Consolidate the ECC support of 83xx

Remove the duplicated source code of ecc command on the <board>.c,
for reused, move these code to cpu/mpc83xx directory.

Signed-off-by: Dave Liu <daveliu <at> freescale.com>
---
 board/mpc8349emds/mpc8349emds.c |  327 --------------------------------
 board/mpc8360emds/mpc8360emds.c |  378 -------------------------------------
 cpu/mpc83xx/Makefile            |    2 +-
 cpu/mpc83xx/ecc.c               |  390 +++++++++++++++++++++++++++++++++++++++
 4 files changed, 391 insertions(+), 706 deletions(-)
 create mode 100644 cpu/mpc83xx/ecc.c

diff --git a/board/mpc8349emds/mpc8349emds.c b/board/mpc8349emds/mpc8349emds.c
index 071591e..521d1bb 100644
--- a/board/mpc8349emds/mpc8349emds.c
+++ b/board/mpc8349emds/mpc8349emds.c
 <at>  <at>  -29,7 +29,6  <at>  <at> 
 #include <i2c.h>
 #include <spd.h>
 #include <miiphy.h>
-#include <command.h>
 #if defined(CONFIG_SPD_EEPROM)
 #include <spd_sdram.h>
 #endif
 <at>  <at>  -258,332 +257,6  <at>  <at>  void sdram_init(void)
 }
 #endif

-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
-/*
- * ECC user commands
- */
-void ecc_print_status(void)
-{
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ddr83xx_t *ddr = &immap->ddr;
-
-	printf("\nECC mode: %s\n\n", (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
-
-	/* Interrupts */
-	printf("Memory Error Interrupt Enable:\n");
-	printf("  Multiple-Bit Error Interrupt Enable: %d\n",
-			(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
-	printf("  Single-Bit Error Interrupt Enable: %d\n",
-			(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
-	printf("  Memory Select Error Interrupt Enable: %d\n\n",
-			(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
-
-	/* Error disable */
-	printf("Memory Error Disable:\n");
-	printf("  Multiple-Bit Error Disable: %d\n",
-			(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
-	printf("  Sinle-Bit Error Disable: %d\n",
-			(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
-	printf("  Memory Select Error Disable: %d\n\n",
-			(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
-
-	/* Error injection */
-	printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
-			ddr->data_err_inject_hi, ddr->data_err_inject_lo);
-
-	printf("Memory Data Path Error Injection Mask ECC:\n");
-	printf("  ECC Mirror Byte: %d\n",
-			(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
-	printf("  ECC Injection Enable: %d\n",
-			(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
-	printf("  ECC Error Injection Mask: 0x%02x\n\n",
-			ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
-
-	/* SBE counter/threshold */
-	printf("Memory Single-Bit Error Management (0..255):\n");
-	printf("  Single-Bit Error Threshold: %d\n",
-			(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
-	printf("  Single-Bit Error Counter: %d\n\n",
-			(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
-
-	/* Error detect */
-	printf("Memory Error Detect:\n");
-	printf("  Multiple Memory Errors: %d\n",
-			(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
-	printf("  Multiple-Bit Error: %d\n",
-			(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
-	printf("  Single-Bit Error: %d\n",
-			(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
-	printf("  Memory Select Error: %d\n\n",
-			(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
-
-	/* Capture data */
-	printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
-	printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
-			ddr->capture_data_hi, ddr->capture_data_lo);
-	printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
-		ddr->capture_ecc & CAPTURE_ECC_ECE);
-
-	printf("Memory Error Attributes Capture:\n");
-	printf("  Data Beat Number: %d\n",
-			(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >> ECC_CAPT_ATTR_BNUM_SHIFT);
-	printf("  Transaction Size: %d\n",
-			(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >> ECC_CAPT_ATTR_TSIZ_SHIFT);
-	printf("  Transaction Source: %d\n",
-			(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >> ECC_CAPT_ATTR_TSRC_SHIFT);
-	printf("  Transaction Type: %d\n",
-			(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >> ECC_CAPT_ATTR_TTYP_SHIFT);
-	printf("  Error Information Valid: %d\n\n",
-			ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
-}
-
-int do_ecc ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
-	volatile ddr83xx_t *ddr = &immap->ddr;
-	volatile u32 val;
-	u64 *addr, count, val64;
-	register u64 *i;
-
-	if (argc > 4) {
-		printf ("Usage:\n%s\n", cmdtp->usage);
-		return 1;
-	}
-
-	if (argc == 2) {
-		if (strcmp(argv[1], "status") == 0) {
-			ecc_print_status();
-			return 0;
-		} else if (strcmp(argv[1], "captureclear") == 0) {
-			ddr->capture_address = 0;
-			ddr->capture_data_hi = 0;
-			ddr->capture_data_lo = 0;
-			ddr->capture_ecc = 0;
-			ddr->capture_attributes = 0;
-			return 0;
-		}
-	}
-
-	if (argc == 3) {
-		if (strcmp(argv[1], "sbecnt") == 0) {
-			val = simple_strtoul(argv[2], NULL, 10);
-			if (val > 255) {
-				printf("Incorrect Counter value, should be 0..255\n");
-				return 1;
-			}
-
-			val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
-			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
-
-			ddr->err_sbe = val;
-			return 0;
-		} else if (strcmp(argv[1], "sbethr") == 0) {
-			val = simple_strtoul(argv[2], NULL, 10);
-			if (val > 255) {
-				printf("Incorrect Counter value, should be 0..255\n");
-				return 1;
-			}
-
-			val = (val << ECC_ERROR_MAN_SBET_SHIFT);
-			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
-
-			ddr->err_sbe = val;
-			return 0;
-		} else if (strcmp(argv[1], "errdisable") == 0) {
-			val = ddr->err_disable;
-
-			if (strcmp(argv[2], "+sbe") == 0) {
-				val |= ECC_ERROR_DISABLE_SBED;
-			} else if (strcmp(argv[2], "+mbe") == 0) {
-				val |= ECC_ERROR_DISABLE_MBED;
-			} else if (strcmp(argv[2], "+mse") == 0) {
-				val |= ECC_ERROR_DISABLE_MSED;
-			} else if (strcmp(argv[2], "+all") == 0) {
-				val |= (ECC_ERROR_DISABLE_SBED |
-					ECC_ERROR_DISABLE_MBED |
-					ECC_ERROR_DISABLE_MSED);
-			} else if (strcmp(argv[2], "-sbe") == 0) {
-				val &= ~ECC_ERROR_DISABLE_SBED;
-			} else if (strcmp(argv[2], "-mbe") == 0) {
-				val &= ~ECC_ERROR_DISABLE_MBED;
-			} else if (strcmp(argv[2], "-mse") == 0) {
-				val &= ~ECC_ERROR_DISABLE_MSED;
-			} else if (strcmp(argv[2], "-all") == 0) {
-				val &= ~(ECC_ERROR_DISABLE_SBED |
-					ECC_ERROR_DISABLE_MBED |
-					ECC_ERROR_DISABLE_MSED);
-			} else {
-				printf("Incorrect err_disable field\n");
-				return 1;
-			}
-
-			ddr->err_disable = val;
-			__asm__ __volatile__ ("sync");
-			__asm__ __volatile__ ("isync");
-			return 0;
-		} else if (strcmp(argv[1], "errdetectclr") == 0) {
-			val = ddr->err_detect;
-
-			if (strcmp(argv[2], "mme") == 0) {
-				val |= ECC_ERROR_DETECT_MME;
-			} else if (strcmp(argv[2], "sbe") == 0) {
-				val |= ECC_ERROR_DETECT_SBE;
-			} else if (strcmp(argv[2], "mbe") == 0) {
-				val |= ECC_ERROR_DETECT_MBE;
-			} else if (strcmp(argv[2], "mse") == 0) {
-				val |= ECC_ERROR_DETECT_MSE;
-			} else if (strcmp(argv[2], "all") == 0) {
-				val |= (ECC_ERROR_DETECT_MME |
-					ECC_ERROR_DETECT_MBE |
-					ECC_ERROR_DETECT_SBE |
-					ECC_ERROR_DETECT_MSE);
-			} else {
-				printf("Incorrect err_detect field\n");
-				return 1;
-			}
-
-			ddr->err_detect = val;
-			return 0;
-		} else if (strcmp(argv[1], "injectdatahi") == 0) {
-			val = simple_strtoul(argv[2], NULL, 16);
-
-			ddr->data_err_inject_hi = val;
-			return 0;
-		} else if (strcmp(argv[1], "injectdatalo") == 0) {
-			val = simple_strtoul(argv[2], NULL, 16);
-
-			ddr->data_err_inject_lo = val;
-			return 0;
-		} else if (strcmp(argv[1], "injectecc") == 0) {
-			val = simple_strtoul(argv[2], NULL, 16);
-			if (val > 0xff) {
-				printf("Incorrect ECC inject mask, should be 0x00..0xff\n");
-				return 1;
-			}
-			val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
-
-			ddr->ecc_err_inject = val;
-			return 0;
-		} else if (strcmp(argv[1], "inject") == 0) {
-			val = ddr->ecc_err_inject;
-
-			if (strcmp(argv[2], "en") == 0)
-				val |= ECC_ERR_INJECT_EIEN;
-			else if (strcmp(argv[2], "dis") == 0)
-				val &= ~ECC_ERR_INJECT_EIEN;
-			else
-				printf("Incorrect command\n");
-
-			ddr->ecc_err_inject = val;
-			__asm__ __volatile__ ("sync");
-			__asm__ __volatile__ ("isync");
-			return 0;
-		} else if (strcmp(argv[1], "mirror") == 0) {
-			val = ddr->ecc_err_inject;
-
-			if (strcmp(argv[2], "en") == 0)
-				val |= ECC_ERR_INJECT_EMB;
-			else if (strcmp(argv[2], "dis") == 0)
-				val &= ~ECC_ERR_INJECT_EMB;
-			else
-				printf("Incorrect command\n");
-
-			ddr->ecc_err_inject = val;
-			return 0;
-		}
-	}
-
-	if (argc == 4) {
-		if (strcmp(argv[1], "test") == 0) {
-			addr = (u64 *)simple_strtoul(argv[2], NULL, 16);
-			count = simple_strtoul(argv[3], NULL, 16);
-
-			if ((u32)addr % 8) {
-				printf("Address not alligned on double word boundary\n");
-				return 1;
-			}
-
-			disable_interrupts();
-			icache_disable();
-
-			for (i = addr; i < addr + count; i++) {
-				/* enable injects */
-				ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
-				__asm__ __volatile__ ("sync");
-				__asm__ __volatile__ ("isync");
-
-				/* write memory location injecting errors */
-				*i = 0x1122334455667788ULL;
-				__asm__ __volatile__ ("sync");
-
-				/* disable injects */
-				ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
-				__asm__ __volatile__ ("sync");
-				__asm__ __volatile__ ("isync");
-
-				/* read data, this generates ECC error */
-				val64 = *i;
-				__asm__ __volatile__ ("sync");
-
-				/* disable errors for ECC */
-				ddr->err_disable |= ~ECC_ERROR_ENABLE;
-				__asm__ __volatile__ ("sync");
-				__asm__ __volatile__ ("isync");
-
-				/* re-initialize memory, write the location again
-				 * NOT injecting errors this time */
-				*i = 0xcafecafecafecafeULL;
-				__asm__ __volatile__ ("sync");
-
-				/* enable errors for ECC */
-				ddr->err_disable &= ECC_ERROR_ENABLE;
-				__asm__ __volatile__ ("sync");
-				__asm__ __volatile__ ("isync");
-			}
-
-			icache_enable();
-			enable_interrupts();
-
-			return 0;
-		}
-	}
-
-	printf ("Usage:\n%s\n", cmdtp->usage);
-	return 1;
-}
-
-U_BOOT_CMD(
-	ecc,     4,     0,      do_ecc,
-	"ecc     - support for DDR ECC features\n",
-	"status              - print out status info\n"
-	"ecc captureclear        - clear capture regs data\n"
-	"ecc sbecnt <val>        - set Single-Bit Error counter\n"
-	"ecc sbethr <val>        - set Single-Bit Threshold\n"
-	"ecc errdisable <flag>   - clear/set disable Memory Error Disable, flag:\n"
-	"  [-|+]sbe - Single-Bit Error\n"
-	"  [-|+]mbe - Multiple-Bit Error\n"
-	"  [-|+]mse - Memory Select Error\n"
-	"  [-|+]all - all errors\n"
-	"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
-	"  mme - Multiple Memory Errors\n"
-	"  sbe - Single-Bit Error\n"
-	"  mbe - Multiple-Bit Error\n"
-	"  mse - Memory Select Error\n"
-	"  all - all errors\n"
-	"ecc injectdatahi <hi>  - set Memory Data Path Error Injection Mask High\n"
-	"ecc injectdatalo <lo>  - set Memory Data Path Error Injection Mask Low\n"
-	"ecc injectecc <ecc>    - set ECC Error Injection Mask\n"
-	"ecc inject <en|dis>    - enable/disable error injection\n"
-	"ecc mirror <en|dis>    - enable/disable mirror byte\n"
-	"ecc test <addr> <cnt>  - test mem region:\n"
-	"  - enables injects\n"
-	"  - writes pattern injecting errors\n"
-	"  - disables injects\n"
-	"  - reads pattern back, generates error\n"
-	"  - re-inits memory"
-);
-#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
-
 #if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
 void
 ft_board_setup(void *blob, bd_t *bd)
diff --git a/board/mpc8360emds/mpc8360emds.c b/board/mpc8360emds/mpc8360emds.c
index b109317..3fa093d 100644
--- a/board/mpc8360emds/mpc8360emds.c
+++ b/board/mpc8360emds/mpc8360emds.c
 <at>  <at>  -1,8 +1,6  <at>  <at> 
 /*
  * Copyright (C) 2006 Freescale Semiconductor, Inc.
- *
  * Dave Liu <daveliu <at> freescale.com>
- * based on board/mpc8349emds/mpc8349emds.c
  *
  * See file CREDITS for list of people who contributed to this
  * project.
 <at>  <at>  -19,7 +17,6  <at>  <at> 
 #include <i2c.h>
 #include <spd.h>
 #include <miiphy.h>
-#include <command.h>
 #if defined(CONFIG_PCI)
 #include <pci.h>
 #endif
 <at>  <at>  -288,381 +285,6  <at>  <at>  void sdram_init(void)
 }
 #endif

-#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
-/*
- * ECC user commands
- */
-void ecc_print_status(void)
-{
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
-	volatile ddr83xx_t *ddr = &immap->ddr;
-
-	printf("\nECC mode: %s\n\n",
-	       (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
-
-	/* Interrupts */
-	printf("Memory Error Interrupt Enable:\n");
-	printf("  Multiple-Bit Error Interrupt Enable: %d\n",
-	       (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
-	printf("  Single-Bit Error Interrupt Enable: %d\n",
-	       (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
-	printf("  Memory Select Error Interrupt Enable: %d\n\n",
-	       (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
-
-	/* Error disable */
-	printf("Memory Error Disable:\n");
-	printf("  Multiple-Bit Error Disable: %d\n",
-	       (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
-	printf("  Sinle-Bit Error Disable: %d\n",
-	       (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
-	printf("  Memory Select Error Disable: %d\n\n",
-	       (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
-
-	/* Error injection */
-	printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
-	       ddr->data_err_inject_hi, ddr->data_err_inject_lo);
-
-	printf("Memory Data Path Error Injection Mask ECC:\n");
-	printf("  ECC Mirror Byte: %d\n",
-	       (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
-	printf("  ECC Injection Enable: %d\n",
-	       (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
-	printf("  ECC Error Injection Mask: 0x%02x\n\n",
-	       ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
-
-	/* SBE counter/threshold */
-	printf("Memory Single-Bit Error Management (0..255):\n");
-	printf("  Single-Bit Error Threshold: %d\n",
-	       (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
-	printf("  Single-Bit Error Counter: %d\n\n",
-	       (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
-
-	/* Error detect */
-	printf("Memory Error Detect:\n");
-	printf("  Multiple Memory Errors: %d\n",
-	       (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
-	printf("  Multiple-Bit Error: %d\n",
-	       (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
-	printf("  Single-Bit Error: %d\n",
-	       (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
-	printf("  Memory Select Error: %d\n\n",
-	       (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
-
-	/* Capture data */
-	printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
-	printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
-	       ddr->capture_data_hi, ddr->capture_data_lo);
-	printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
-	       ddr->capture_ecc & CAPTURE_ECC_ECE);
-
-	printf("Memory Error Attributes Capture:\n");
-	printf(" Data Beat Number: %d\n",
-	       (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >>
-	       ECC_CAPT_ATTR_BNUM_SHIFT);
-	printf("  Transaction Size: %d\n",
-	       (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >>
-	       ECC_CAPT_ATTR_TSIZ_SHIFT);
-	printf("  Transaction Source: %d\n",
-	       (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >>
-	       ECC_CAPT_ATTR_TSRC_SHIFT);
-	printf("  Transaction Type: %d\n",
-	       (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >>
-	       ECC_CAPT_ATTR_TTYP_SHIFT);
-	printf("  Error Information Valid: %d\n\n",
-	       ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
-}
-
-int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
-{
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
-	volatile ddr83xx_t *ddr = &immap->ddr;
-	volatile u32 val;
-	u64 *addr;
-	u32 count;
-	register u64 *i;
-	u32 ret[2];
-	u32 pattern[2];
-	u32 writeback[2];
-
-	/* The pattern is written into memory to generate error */
-	pattern[0] = 0xfedcba98UL;
-	pattern[1] = 0x76543210UL;
-
-	/* After injecting error, re-initialize the memory with the value */
-	writeback[0] = 0x01234567UL;
-	writeback[1] = 0x89abcdefUL;
-
-	if (argc > 4) {
-		printf("Usage:\n%s\n", cmdtp->usage);
-		return 1;
-	}
-
-	if (argc == 2) {
-		if (strcmp(argv[1], "status") == 0) {
-			ecc_print_status();
-			return 0;
-		} else if (strcmp(argv[1], "captureclear") == 0) {
-			ddr->capture_address = 0;
-			ddr->capture_data_hi = 0;
-			ddr->capture_data_lo = 0;
-			ddr->capture_ecc = 0;
-			ddr->capture_attributes = 0;
-			return 0;
-		}
-	}
-	if (argc == 3) {
-		if (strcmp(argv[1], "sbecnt") == 0) {
-			val = simple_strtoul(argv[2], NULL, 10);
-			if (val > 255) {
-				printf("Incorrect Counter value, "
-				       "should be 0..255\n");
-				return 1;
-			}
-
-			val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
-			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
-
-			ddr->err_sbe = val;
-			return 0;
-		} else if (strcmp(argv[1], "sbethr") == 0) {
-			val = simple_strtoul(argv[2], NULL, 10);
-			if (val > 255) {
-				printf("Incorrect Counter value, "
-				       "should be 0..255\n");
-				return 1;
-			}
-
-			val = (val << ECC_ERROR_MAN_SBET_SHIFT);
-			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
-
-			ddr->err_sbe = val;
-			return 0;
-		} else if (strcmp(argv[1], "errdisable") == 0) {
-			val = ddr->err_disable;
-
-			if (strcmp(argv[2], "+sbe") == 0) {
-				val |= ECC_ERROR_DISABLE_SBED;
-			} else if (strcmp(argv[2], "+mbe") == 0) {
-				val |= ECC_ERROR_DISABLE_MBED;
-			} else if (strcmp(argv[2], "+mse") == 0) {
-				val |= ECC_ERROR_DISABLE_MSED;
-			} else if (strcmp(argv[2], "+all") == 0) {
-				val |= (ECC_ERROR_DISABLE_SBED |
-					ECC_ERROR_DISABLE_MBED |
-					ECC_ERROR_DISABLE_MSED);
-			} else if (strcmp(argv[2], "-sbe") == 0) {
-				val &= ~ECC_ERROR_DISABLE_SBED;
-			} else if (strcmp(argv[2], "-mbe") == 0) {
-				val &= ~ECC_ERROR_DISABLE_MBED;
-			} else if (strcmp(argv[2], "-mse") == 0) {
-				val &= ~ECC_ERROR_DISABLE_MSED;
-			} else if (strcmp(argv[2], "-all") == 0) {
-				val &= ~(ECC_ERROR_DISABLE_SBED |
-					 ECC_ERROR_DISABLE_MBED |
-					 ECC_ERROR_DISABLE_MSED);
-			} else {
-				printf("Incorrect err_disable field\n");
-				return 1;
-			}
-
-			ddr->err_disable = val;
-			__asm__ __volatile__("sync");
-			__asm__ __volatile__("isync");
-			return 0;
-		} else if (strcmp(argv[1], "errdetectclr") == 0) {
-			val = ddr->err_detect;
-
-			if (strcmp(argv[2], "mme") == 0) {
-				val |= ECC_ERROR_DETECT_MME;
-			} else if (strcmp(argv[2], "sbe") == 0) {
-				val |= ECC_ERROR_DETECT_SBE;
-			} else if (strcmp(argv[2], "mbe") == 0) {
-				val |= ECC_ERROR_DETECT_MBE;
-			} else if (strcmp(argv[2], "mse") == 0) {
-				val |= ECC_ERROR_DETECT_MSE;
-			} else if (strcmp(argv[2], "all") == 0) {
-				val |= (ECC_ERROR_DETECT_MME |
-					ECC_ERROR_DETECT_MBE |
-					ECC_ERROR_DETECT_SBE |
-					ECC_ERROR_DETECT_MSE);
-			} else {
-				printf("Incorrect err_detect field\n");
-				return 1;
-			}
-
-			ddr->err_detect = val;
-			return 0;
-		} else if (strcmp(argv[1], "injectdatahi") == 0) {
-			val = simple_strtoul(argv[2], NULL, 16);
-
-			ddr->data_err_inject_hi = val;
-			return 0;
-		} else if (strcmp(argv[1], "injectdatalo") == 0) {
-			val = simple_strtoul(argv[2], NULL, 16);
-
-			ddr->data_err_inject_lo = val;
-			return 0;
-		} else if (strcmp(argv[1], "injectecc") == 0) {
-			val = simple_strtoul(argv[2], NULL, 16);
-			if (val > 0xff) {
-				printf("Incorrect ECC inject mask, "
-				       "should be 0x00..0xff\n");
-				return 1;
-			}
-			val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
-
-			ddr->ecc_err_inject = val;
-			return 0;
-		} else if (strcmp(argv[1], "inject") == 0) {
-			val = ddr->ecc_err_inject;
-
-			if (strcmp(argv[2], "en") == 0)
-				val |= ECC_ERR_INJECT_EIEN;
-			else if (strcmp(argv[2], "dis") == 0)
-				val &= ~ECC_ERR_INJECT_EIEN;
-			else
-				printf("Incorrect command\n");
-
-			ddr->ecc_err_inject = val;
-			__asm__ __volatile__("sync");
-			__asm__ __volatile__("isync");
-			return 0;
-		} else if (strcmp(argv[1], "mirror") == 0) {
-			val = ddr->ecc_err_inject;
-
-			if (strcmp(argv[2], "en") == 0)
-				val |= ECC_ERR_INJECT_EMB;
-			else if (strcmp(argv[2], "dis") == 0)
-				val &= ~ECC_ERR_INJECT_EMB;
-			else
-				printf("Incorrect command\n");
-
-			ddr->ecc_err_inject = val;
-			return 0;
-		}
-	}
-	if (argc == 4) {
-		if (strcmp(argv[1], "testdw") == 0) {
-			addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
-			count = simple_strtoul(argv[3], NULL, 16);
-
-			if ((u32) addr % 8) {
-				printf("Address not alligned on "
-				       "double word boundary\n");
-				return 1;
-			}
-			disable_interrupts();
-
-			for (i = addr; i < addr + count; i++) {
-
-				/* enable injects */
-				ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
-				__asm__ __volatile__("sync");
-				__asm__ __volatile__("isync");
-
-				/* write memory location injecting errors */
-				ppcDWstore((u32 *) i, pattern);
-				__asm__ __volatile__("sync");
-
-				/* disable injects */
-				ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
-				__asm__ __volatile__("sync");
-				__asm__ __volatile__("isync");
-
-				/* read data, this generates ECC error */
-				ppcDWload((u32 *) i, ret);
-				__asm__ __volatile__("sync");
-
-				/* re-initialize memory, double word write the location again,
-				 * generates new ECC code this time */
-				ppcDWstore((u32 *) i, writeback);
-				__asm__ __volatile__("sync");
-			}
-			enable_interrupts();
-			return 0;
-		}
-		if (strcmp(argv[1], "testword") == 0) {
-			addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
-			count = simple_strtoul(argv[3], NULL, 16);
-
-			if ((u32) addr % 8) {
-				printf("Address not alligned on "
-				       "double word boundary\n");
-				return 1;
-			}
-			disable_interrupts();
-
-			for (i = addr; i < addr + count; i++) {
-
-				/* enable injects */
-				ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
-				__asm__ __volatile__("sync");
-				__asm__ __volatile__("isync");
-
-				/* write memory location injecting errors */
-				*(u32 *) i = 0xfedcba98UL;
-				__asm__ __volatile__("sync");
-
-				/* sub double word write,
-				 * bus will read-modify-write,
-				 * generates ECC error */
-				*((u32 *) i + 1) = 0x76543210UL;
-				__asm__ __volatile__("sync");
-
-				/* disable injects */
-				ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
-				__asm__ __volatile__("sync");
-				__asm__ __volatile__("isync");
-
-				/* re-initialize memory,
-				 * double word write the location again,
-				 * generates new ECC code this time */
-				ppcDWstore((u32 *) i, writeback);
-				__asm__ __volatile__("sync");
-			}
-			enable_interrupts();
-			return 0;
-		}
-	}
-	printf("Usage:\n%s\n", cmdtp->usage);
-	return 1;
-}
-
-U_BOOT_CMD(ecc, 4, 0, do_ecc,
-	   "ecc     - support for DDR ECC features\n",
-	   "status              - print out status info\n"
-	   "ecc captureclear        - clear capture regs data\n"
-	   "ecc sbecnt <val>        - set Single-Bit Error counter\n"
-	   "ecc sbethr <val>        - set Single-Bit Threshold\n"
-	   "ecc errdisable <flag>   - clear/set disable Memory Error Disable, flag:\n"
-	   "  [-|+]sbe - Single-Bit Error\n"
-	   "  [-|+]mbe - Multiple-Bit Error\n"
-	   "  [-|+]mse - Memory Select Error\n"
-	   "  [-|+]all - all errors\n"
-	   "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
-	   "  mme - Multiple Memory Errors\n"
-	   "  sbe - Single-Bit Error\n"
-	   "  mbe - Multiple-Bit Error\n"
-	   "  mse - Memory Select Error\n"
-	   "  all - all errors\n"
-	   "ecc injectdatahi <hi>  - set Memory Data Path Error Injection Mask High\n"
-	   "ecc injectdatalo <lo>  - set Memory Data Path Error Injection Mask Low\n"
-	   "ecc injectecc <ecc>    - set ECC Error Injection Mask\n"
-	   "ecc inject <en|dis>    - enable/disable error injection\n"
-	   "ecc mirror <en|dis>    - enable/disable mirror byte\n"
-	   "ecc testdw <addr> <cnt>  - test mem region with double word access:\n"
-	   "  - enables injects\n"
-	   "  - writes pattern injecting errors with double word access\n"
-	   "  - disables injects\n"
-	   "  - reads pattern back with double word access, generates error\n"
-	   "  - re-inits memory\n"
-	   "ecc testword <addr> <cnt>  - test mem region with word access:\n"
-	   "  - enables injects\n"
-	   "  - writes pattern injecting errors with word access\n"
-	   "  - writes pattern with word access, generates error\n"
-	   "  - disables injects\n" "  - re-inits memory");
-#endif				/* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
-
 #if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \
      && defined(CONFIG_OF_BOARD_SETUP)

diff --git a/cpu/mpc83xx/Makefile b/cpu/mpc83xx/Makefile
index bb96f77..2329970 100644
--- a/cpu/mpc83xx/Makefile
+++ b/cpu/mpc83xx/Makefile
 <at>  <at>  -29,7 +29,7  <at>  <at>  LIB	= $(obj)lib$(CPU).a

 START	= start.o
 COBJS	= traps.o cpu.o cpu_init.o speed.o interrupts.o \
-	  spd_sdram.o qe_io.o pci.o
+	  spd_sdram.o ecc.o qe_io.o pci.o

 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
diff --git a/cpu/mpc83xx/ecc.c b/cpu/mpc83xx/ecc.c
new file mode 100644
index 0000000..6f13094
--- /dev/null
+++ b/cpu/mpc83xx/ecc.c
 <at>  <at>  -0,0 +1,390  <at>  <at> 
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * Dave Liu <daveliu <at> freescale.com>
+ * based on the contribution of Marian Balakowicz <m8 <at> semihalf.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <mpc83xx.h>
+#include <command.h>
+
+#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
+void ecc_print_status(void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile ddr83xx_t *ddr = &immap->ddr;
+
+	printf("\nECC mode: %s\n\n",
+	       (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
+
+	/* Interrupts */
+	printf("Memory Error Interrupt Enable:\n");
+	printf("  Multiple-Bit Error Interrupt Enable: %d\n",
+	       (ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
+	printf("  Single-Bit Error Interrupt Enable: %d\n",
+	       (ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
+	printf("  Memory Select Error Interrupt Enable: %d\n\n",
+	       (ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
+
+	/* Error disable */
+	printf("Memory Error Disable:\n");
+	printf("  Multiple-Bit Error Disable: %d\n",
+	       (ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
+	printf("  Sinle-Bit Error Disable: %d\n",
+	       (ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
+	printf("  Memory Select Error Disable: %d\n\n",
+	       (ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
+
+	/* Error injection */
+	printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
+	       ddr->data_err_inject_hi, ddr->data_err_inject_lo);
+
+	printf("Memory Data Path Error Injection Mask ECC:\n");
+	printf("  ECC Mirror Byte: %d\n",
+	       (ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
+	printf("  ECC Injection Enable: %d\n",
+	       (ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
+	printf("  ECC Error Injection Mask: 0x%02x\n\n",
+	       ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
+
+	/* SBE counter/threshold */
+	printf("Memory Single-Bit Error Management (0..255):\n");
+	printf("  Single-Bit Error Threshold: %d\n",
+	       (ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
+	printf("  Single-Bit Error Counter: %d\n\n",
+	       (ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
+
+	/* Error detect */
+	printf("Memory Error Detect:\n");
+	printf("  Multiple Memory Errors: %d\n",
+	       (ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
+	printf("  Multiple-Bit Error: %d\n",
+	       (ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
+	printf("  Single-Bit Error: %d\n",
+	       (ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
+	printf("  Memory Select Error: %d\n\n",
+	       (ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
+
+	/* Capture data */
+	printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
+	printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
+	       ddr->capture_data_hi, ddr->capture_data_lo);
+	printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
+	       ddr->capture_ecc & CAPTURE_ECC_ECE);
+
+	printf("Memory Error Attributes Capture:\n");
+	printf(" Data Beat Number: %d\n",
+	       (ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >>
+	       ECC_CAPT_ATTR_BNUM_SHIFT);
+	printf("  Transaction Size: %d\n",
+	       (ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >>
+	       ECC_CAPT_ATTR_TSIZ_SHIFT);
+	printf("  Transaction Source: %d\n",
+	       (ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >>
+	       ECC_CAPT_ATTR_TSRC_SHIFT);
+	printf("  Transaction Type: %d\n",
+	       (ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >>
+	       ECC_CAPT_ATTR_TTYP_SHIFT);
+	printf("  Error Information Valid: %d\n\n",
+	       ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
+}
+
+int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile ddr83xx_t *ddr = &immap->ddr;
+	volatile u32 val;
+	u64 *addr;
+	u32 count;
+	register u64 *i;
+	u32 ret[2];
+	u32 pattern[2];
+	u32 writeback[2];
+
+	/* The pattern is written into memory to generate error */
+	pattern[0] = 0xfedcba98UL;
+	pattern[1] = 0x76543210UL;
+
+	/* After injecting error, re-initialize the memory with the value */
+	writeback[0] = 0x01234567UL;
+	writeback[1] = 0x89abcdefUL;
+
+	if (argc > 4) {
+		printf("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	if (argc == 2) {
+		if (strcmp(argv[1], "status") == 0) {
+			ecc_print_status();
+			return 0;
+		} else if (strcmp(argv[1], "captureclear") == 0) {
+			ddr->capture_address = 0;
+			ddr->capture_data_hi = 0;
+			ddr->capture_data_lo = 0;
+			ddr->capture_ecc = 0;
+			ddr->capture_attributes = 0;
+			return 0;
+		}
+	}
+	if (argc == 3) {
+		if (strcmp(argv[1], "sbecnt") == 0) {
+			val = simple_strtoul(argv[2], NULL, 10);
+			if (val > 255) {
+				printf("Incorrect Counter value, "
+				       "should be 0..255\n");
+				return 1;
+			}
+
+			val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
+			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
+
+			ddr->err_sbe = val;
+			return 0;
+		} else if (strcmp(argv[1], "sbethr") == 0) {
+			val = simple_strtoul(argv[2], NULL, 10);
+			if (val > 255) {
+				printf("Incorrect Counter value, "
+				       "should be 0..255\n");
+				return 1;
+			}
+
+			val = (val << ECC_ERROR_MAN_SBET_SHIFT);
+			val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
+
+			ddr->err_sbe = val;
+			return 0;
+		} else if (strcmp(argv[1], "errdisable") == 0) {
+			val = ddr->err_disable;
+
+			if (strcmp(argv[2], "+sbe") == 0) {
+				val |= ECC_ERROR_DISABLE_SBED;
+			} else if (strcmp(argv[2], "+mbe") == 0) {
+				val |= ECC_ERROR_DISABLE_MBED;
+			} else if (strcmp(argv[2], "+mse") == 0) {
+				val |= ECC_ERROR_DISABLE_MSED;
+			} else if (strcmp(argv[2], "+all") == 0) {
+				val |= (ECC_ERROR_DISABLE_SBED |
+					ECC_ERROR_DISABLE_MBED |
+					ECC_ERROR_DISABLE_MSED);
+			} else if (strcmp(argv[2], "-sbe") == 0) {
+				val &= ~ECC_ERROR_DISABLE_SBED;
+			} else if (strcmp(argv[2], "-mbe") == 0) {
+				val &= ~ECC_ERROR_DISABLE_MBED;
+			} else if (strcmp(argv[2], "-mse") == 0) {
+				val &= ~ECC_ERROR_DISABLE_MSED;
+			} else if (strcmp(argv[2], "-all") == 0) {
+				val &= ~(ECC_ERROR_DISABLE_SBED |
+					 ECC_ERROR_DISABLE_MBED |
+					 ECC_ERROR_DISABLE_MSED);
+			} else {
+				printf("Incorrect err_disable field\n");
+				return 1;
+			}
+
+			ddr->err_disable = val;
+			__asm__ __volatile__("sync");
+			__asm__ __volatile__("isync");
+			return 0;
+		} else if (strcmp(argv[1], "errdetectclr") == 0) {
+			val = ddr->err_detect;
+
+			if (strcmp(argv[2], "mme") == 0) {
+				val |= ECC_ERROR_DETECT_MME;
+			} else if (strcmp(argv[2], "sbe") == 0) {
+				val |= ECC_ERROR_DETECT_SBE;
+			} else if (strcmp(argv[2], "mbe") == 0) {
+				val |= ECC_ERROR_DETECT_MBE;
+			} else if (strcmp(argv[2], "mse") == 0) {
+				val |= ECC_ERROR_DETECT_MSE;
+			} else if (strcmp(argv[2], "all") == 0) {
+				val |= (ECC_ERROR_DETECT_MME |
+					ECC_ERROR_DETECT_MBE |
+					ECC_ERROR_DETECT_SBE |
+					ECC_ERROR_DETECT_MSE);
+			} else {
+				printf("Incorrect err_detect field\n");
+				return 1;
+			}
+
+			ddr->err_detect = val;
+			return 0;
+		} else if (strcmp(argv[1], "injectdatahi") == 0) {
+			val = simple_strtoul(argv[2], NULL, 16);
+
+			ddr->data_err_inject_hi = val;
+			return 0;
+		} else if (strcmp(argv[1], "injectdatalo") == 0) {
+			val = simple_strtoul(argv[2], NULL, 16);
+
+			ddr->data_err_inject_lo = val;
+			return 0;
+		} else if (strcmp(argv[1], "injectecc") == 0) {
+			val = simple_strtoul(argv[2], NULL, 16);
+			if (val > 0xff) {
+				printf("Incorrect ECC inject mask, "
+				       "should be 0x00..0xff\n");
+				return 1;
+			}
+			val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
+
+			ddr->ecc_err_inject = val;
+			return 0;
+		} else if (strcmp(argv[1], "inject") == 0) {
+			val = ddr->ecc_err_inject;
+
+			if (strcmp(argv[2], "en") == 0)
+				val |= ECC_ERR_INJECT_EIEN;
+			else if (strcmp(argv[2], "dis") == 0)
+				val &= ~ECC_ERR_INJECT_EIEN;
+			else
+				printf("Incorrect command\n");
+
+			ddr->ecc_err_inject = val;
+			__asm__ __volatile__("sync");
+			__asm__ __volatile__("isync");
+			return 0;
+		} else if (strcmp(argv[1], "mirror") == 0) {
+			val = ddr->ecc_err_inject;
+
+			if (strcmp(argv[2], "en") == 0)
+				val |= ECC_ERR_INJECT_EMB;
+			else if (strcmp(argv[2], "dis") == 0)
+				val &= ~ECC_ERR_INJECT_EMB;
+			else
+				printf("Incorrect command\n");
+
+			ddr->ecc_err_inject = val;
+			return 0;
+		}
+	}
+	if (argc == 4) {
+		if (strcmp(argv[1], "testdw") == 0) {
+			addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
+			count = simple_strtoul(argv[3], NULL, 16);
+
+			if ((u32) addr % 8) {
+				printf("Address not alligned on "
+				       "double word boundary\n");
+				return 1;
+			}
+			disable_interrupts();
+
+			for (i = addr; i < addr + count; i++) {
+
+				/* enable injects */
+				ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
+				__asm__ __volatile__("sync");
+				__asm__ __volatile__("isync");
+
+				/* write memory location injecting errors */
+				ppcDWstore((u32 *) i, pattern);
+				__asm__ __volatile__("sync");
+
+				/* disable injects */
+				ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
+				__asm__ __volatile__("sync");
+				__asm__ __volatile__("isync");
+
+				/* read data, this generates ECC error */
+				ppcDWload((u32 *) i, ret);
+				__asm__ __volatile__("sync");
+
+				/* re-initialize memory, double word write the location again,
+				 * generates new ECC code this time */
+				ppcDWstore((u32 *) i, writeback);
+				__asm__ __volatile__("sync");
+			}
+			enable_interrupts();
+			return 0;
+		}
+		if (strcmp(argv[1], "testword") == 0) {
+			addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
+			count = simple_strtoul(argv[3], NULL, 16);
+
+			if ((u32) addr % 8) {
+				printf("Address not alligned on "
+				       "double word boundary\n");
+				return 1;
+			}
+			disable_interrupts();
+
+			for (i = addr; i < addr + count; i++) {
+
+				/* enable injects */
+				ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
+				__asm__ __volatile__("sync");
+				__asm__ __volatile__("isync");
+
+				/* write memory location injecting errors */
+				*(u32 *) i = 0xfedcba98UL;
+				__asm__ __volatile__("sync");
+
+				/* sub double word write,
+				 * bus will read-modify-write,
+				 * generates ECC error */
+				*((u32 *) i + 1) = 0x76543210UL;
+				__asm__ __volatile__("sync");
+
+				/* disable injects */
+				ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
+				__asm__ __volatile__("sync");
+				__asm__ __volatile__("isync");
+
+				/* re-initialize memory,
+				 * double word write the location again,
+				 * generates new ECC code this time */
+				ppcDWstore((u32 *) i, writeback);
+				__asm__ __volatile__("sync");
+			}
+			enable_interrupts();
+			return 0;
+		}
+	}
+	printf("Usage:\n%s\n", cmdtp->usage);
+	return 1;
+}
+
+U_BOOT_CMD(ecc, 4, 0, do_ecc,
+	   "ecc     - support for DDR ECC features\n",
+	   "status              - print out status info\n"
+	   "ecc captureclear        - clear capture regs data\n"
+	   "ecc sbecnt <val>        - set Single-Bit Error counter\n"
+	   "ecc sbethr <val>        - set Single-Bit Threshold\n"
+	   "ecc errdisable <flag>   - clear/set disable Memory Error Disable, flag:\n"
+	   "  [-|+]sbe - Single-Bit Error\n"
+	   "  [-|+]mbe - Multiple-Bit Error\n"
+	   "  [-|+]mse - Memory Select Error\n"
+	   "  [-|+]all - all errors\n"
+	   "ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
+	   "  mme - Multiple Memory Errors\n"
+	   "  sbe - Single-Bit Error\n"
+	   "  mbe - Multiple-Bit Error\n"
+	   "  mse - Memory Select Error\n"
+	   "  all - all errors\n"
+	   "ecc injectdatahi <hi>  - set Memory Data Path Error Injection Mask High\n"
+	   "ecc injectdatalo <lo>  - set Memory Data Path Error Injection Mask Low\n"
+	   "ecc injectecc <ecc>    - set ECC Error Injection Mask\n"
+	   "ecc inject <en|dis>    - enable/disable error injection\n"
+	   "ecc mirror <en|dis>    - enable/disable mirror byte\n"
+	   "ecc testdw <addr> <cnt>  - test mem region with double word access:\n"
+	   "  - enables injects\n"
+	   "  - writes pattern injecting errors with double word access\n"
+	   "  - disables injects\n"
+	   "  - reads pattern back with double word access, generates error\n"
+	   "  - re-inits memory\n"
+	   "ecc testword <addr> <cnt>  - test mem region with word access:\n"
+	   "  - enables injects\n"
+	   "  - writes pattern injecting errors with word access\n"
+	   "  - writes pattern with word access, generates error\n"
+	   "  - disables injects\n" "  - re-inits memory");
+#endif
--

-- 
1.5.3.rc2.29.gc4640f

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[PATCH] mpc83xx: Correct the README for DDR ECC

Update the README for DDR ECC, change the name
to README.mpc83xx.ddrecc.

Signed-off-by: Dave Liu <daveliu <at> freescale.com>
---
 ...ME.mpc8349emds.ddrecc => README.mpc83xx.ddrecc} |   60 ++++++++++----------
 1 files changed, 30 insertions(+), 30 deletions(-)
 rename doc/{README.mpc8349emds.ddrecc => README.mpc83xx.ddrecc} (62%)

diff --git a/doc/README.mpc8349emds.ddrecc b/doc/README.mpc83xx.ddrecc
similarity index 62%
rename from doc/README.mpc8349emds.ddrecc
rename to doc/README.mpc83xx.ddrecc
index eb249c3..0029f08 100644
--- a/doc/README.mpc8349emds.ddrecc
+++ b/doc/README.mpc83xx.ddrecc
 <at>  <at>  -15,10 +15,10  <at>  <at>  IMPORTANT NOTICE: enabling injecting multiple-bit errors is potentially
 dangerous as such errors are NOT corrected by the controller. Therefore caution
 should be taken when enabling the injection of multiple-bit errors: it is only
 safe when used on a carefully selected memory area and used under control of
-the 'ecc test' command (see example 'Injecting Multiple-Bit Errors' below). In
-particular, when you simply set the multiple-bit errors in inject mask and
-enable injection, U-Boot is very likely to hang quickly as the errors will be
-injected when it accesses its code, data etc.
+the 'ecc testdw' 'ecc testword' command (see example 'Injecting Multiple-Bit
+Errors' below). In particular, when you simply set the multiple-bit errors in
+inject mask and enable injection, U-Boot is very likely to hang quickly as the
+errors will be injected when it accesses its code, data etc.

 
 Use cases for DDR 'ecc' command:
 <at>  <at>  -40,7 +40,7  <at>  <at>  Injecting Single-Bit Errors

 2. Run test over some memory region

-=> ecc test 200000 10
+=> ecc testdw 200000 10

 3. Check ECC status

 <at>  <at>  -61,57 +61,57  <at>  <at>  Memory Error Detect:
 16 errors were generated, Single-Bit Error flag was not set as Single Bit Error
 Counter did not reach  Single-Bit Error Threshold.

-4. Make sure used memory region got re-initialized with 0xcafecafe pattern
+4. Make sure used memory region got re-initialized with 0x0123456789abcdef

 => md 200000
-00200000: cafecafe cafecafe cafecafe cafecafe    ................
-00200010: cafecafe cafecafe cafecafe cafecafe    ................
-00200020: cafecafe cafecafe cafecafe cafecafe    ................
-00200030: cafecafe cafecafe cafecafe cafecafe    ................
-00200040: cafecafe cafecafe cafecafe cafecafe    ................
-00200050: cafecafe cafecafe cafecafe cafecafe    ................
-00200060: cafecafe cafecafe cafecafe cafecafe    ................
-00200070: cafecafe cafecafe cafecafe cafecafe    ................
+00200000: 01234567 89abcdef 01234567 89abcdef    .#Eg.....#Eg....
+00200010: 01234567 89abcdef 01234567 89abcdef    .#Eg.....#Eg....
+00200020: 01234567 89abcdef 01234567 89abcdef    .#Eg.....#Eg....
+00200030: 01234567 89abcdef 01234567 89abcdef    .#Eg.....#Eg....
+00200040: 01234567 89abcdef 01234567 89abcdef    .#Eg.....#Eg....
+00200050: 01234567 89abcdef 01234567 89abcdef    .#Eg.....#Eg....
+00200060: 01234567 89abcdef 01234567 89abcdef    .#Eg.....#Eg....
+00200070: 01234567 89abcdef 01234567 89abcdef    .#Eg.....#Eg....
 00200080: deadbeef deadbeef deadbeef deadbeef    ................
 00200090: deadbeef deadbeef deadbeef deadbeef    ................

-
 Injecting Multiple-Bit Errors
 -----------------------------

 1. Set more than 1 bit in Data Path Error Inject Mask

-=> ecc injectdatahi 5
+=> ecc injectdatahi 1
+=> ecc injectdatalo 1

 2. Run test over some memory region

-=> ecc test 200000 10
+=> ecc testword 200000 1

 3. Check ECC status

 => ecc status
 ...
-Memory Data Path Error Injection Mask High/Low: 00000005 00000000
+Memory Data Path Error Injection Mask High/Low: 00000001 00000001
 ...
 Memory Error Detect:
-  Multiple Memory Errors: 1
+  Multiple Memory Errors: 0
   Multiple-Bit Error: 1
   Single-Bit Error: 0
 ...

-Observe that both Multiple Memory Errors and Multiple-Bit Error flags are set.
+The Multiple Memory Errors flags not set and Multiple-Bit Error flags are set.

-4. Make sure used memory region got re-initialized with 0xcafecafe pattern
+4. Make sure used memory region got re-initialized with 0x0123456789abcdef

 => md 200000
-00200000: cafecafe cafecafe cafecafe cafecafe    ................
-00200010: cafecafe cafecafe cafecafe cafecafe    ................
-00200020: cafecafe cafecafe cafecafe cafecafe    ................
-00200030: cafecafe cafecafe cafecafe cafecafe    ................
-00200040: cafecafe cafecafe cafecafe cafecafe    ................
-00200050: cafecafe cafecafe cafecafe cafecafe    ................
-00200060: cafecafe cafecafe cafecafe cafecafe    ................
-00200070: cafecafe cafecafe cafecafe cafecafe    ................
+00200000: 01234567 89abcdef 01234567 89abcdef    .#Eg.....#Eg....
+00200010: 01234567 89abcdef 01234567 89abcdef    .#Eg.....#Eg....
+00200020: 01234567 89abcdef 01234567 89abcdef    .#Eg.....#Eg....
+00200030: 01234567 89abcdef 01234567 89abcdef    .#Eg.....#Eg....
+00200040: 01234567 89abcdef 01234567 89abcdef    .#Eg.....#Eg....
+00200050: 01234567 89abcdef 01234567 89abcdef    .#Eg.....#Eg....
+00200060: 01234567 89abcdef 01234567 89abcdef    .#Eg.....#Eg....
+00200070: 01234567 89abcdef 01234567 89abcdef    .#Eg.....#Eg....
 00200080: deadbeef deadbeef deadbeef deadbeef    ................
 00200090: deadbeef deadbeef deadbeef deadbeef    ................

 <at>  <at>  -140,7 +140,7  <at>  <at>  Test Single-Bit Error Counter and Threshold
 ...
 Memory Single-Bit Error Management (0..255):
   Single-Bit Error Threshold: 255
-  Single Bit Error Counter: 60
+  Single Bit Error Counter: 199

 Memory Error Detect:
   Multiple Memory Errors: 1
--

-- 
1.5.3.rc2.29.gc4640f

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Re: uboot custodian question

I bottom post 

> -----Original Message-----
> From: Nishanth Menon [mailto:menon.nishanth <at> gmail.com] 
> Sent: 01 August 2007 03:53
> To: Peter Pearse
> Subject: uboot custodian question
> 
> Hi Peter,
> am wondering if OMAP patches are expected to be pushed to u or not..
> thought i'd do a bit of devel as i get time..
> Regards,
> Nishanth Menon
> 

Until such time as we get a volunteer for arm/OMAP custodian I will be 
checking them.

But patches should be pushed to the list, not direct to me......

Peter

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U-Boot Release Cycle - Merge Window now open.

Hello everybody,

one of the problems we have with the U-Boot  development  process  is
it's Release Cycle. To be precise, the non-existence of such a thing.

This will be  changed  now.  Like  with  many  other  things,  U-Boot
development  will  from  now  on  follow the Linux model of a release
cycle. That means:

* We will have U-Boot releases at a fixed interval.
* The release interval shall be (approximately) 2 months.
* Immediately following each release, there will be a "merge window".
  While this merge window is open, new features can be added to the
  U-Boot source tree.
* After the merge window closes, no new features may be added to
  allow for a release candidate phase which is intended to fix bugs
  and regressions.

To avoid having merge windows open for both U-Boot and Linux  at  the
same time, we will start with an offset of one month, i. e. the first
U-Boot  release following this new development cycle is scheduled for
end of September 2007.

The merge window for this release opens *NOW*.
It ends on August 17, 2007.

See also http://www.denx.de/wiki/UBoot/ReleaseCycle

Best regards,

Wolfgang Denk

--

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd <at> denx.de
C++ is the best example of second-system effect since OS/360.

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Update for 5329

Stefan,

Here is the updates:
1. Update-CONFIG_MCFUART.patch
2. Added-common-define-CONFIG_CF_MII-for-do_mii.patch
3. Moved-sync-from-m5329evb.c-to-include-asm-m68k-io.patch
4. Added-uart_gpio_conf-for-port-configuration.patch
5. Update-timer.patch
6. Added-fsl_i2c-header-file.patch
7. Added-NAND-Flash-support-and-I2C-support.patch
8. Added-GPIO-enabled-for-I2C-signals.patch

Note: NAND support still partially incomplete, unable to read/write.
Erase, bad, markbad, lock, unlock and info seems working.

Thanks,

Regards,
TsiChung

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_______________________________________________
U-Boot-Users mailing list
U-Boot-Users <at> lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/u-boot-users

Re: uboot custodian question

On Wed, 1 Aug 2007, Peter Pearse wrote:

Hey, any chances that TI DaVinci will come into the main tree until it's too
late for this release? Patches won't be accepted after August 19th or so
according to the new release schedule...

> I bottom post
>
>> -----Original Message-----
>> From: Nishanth Menon [mailto:menon.nishanth <at> gmail.com]
>> Sent: 01 August 2007 03:53
>> To: Peter Pearse
>> Subject: uboot custodian question
>>
>> Hi Peter,
>> am wondering if OMAP patches are expected to be pushed to u or not..
>> thought i'd do a bit of devel as i get time..
>> Regards,
>> Nishanth Menon
>>
>
> Until such time as we get a volunteer for arm/OMAP custodian I will be
> checking them.
>
> But patches should be pushed to the list, not direct to me......
>
> Peter
>
>
>
> ------------------------------------------------------------------------
> -
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> Still grepping through log files to find problems?  Stop.
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> _______________________________________________
> U-Boot-Users mailing list
> U-Boot-Users <at> lists.sourceforge.net
> https://lists.sourceforge.net/lists/listinfo/u-boot-users
>

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