Juan is not available now, and Anthony asked for agenda to be sent early. So here comes: Agenda for the meeting Tue, May 28: - Generating acpi tables - Switching the call to a bi-weekly schedule Please, send any topic that you are interested in covering. Thanks, MST -- -- MST
_______________________________________________ SeaBIOS mailing list SeaBIOS <at> seabios.org http://www.seabios.org/mailman/listinfo/seabios
Hi all. Would it be possible to add some DMI based quirks? I have a device and in coreboot I have some detection code for it: http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/mainboard/bachmann/ot200/mainboard.c;h=0ea053aad0c9e085bbd8ea36f14210404881edb7;hb=HEAD Now it takes quite some time to load Grub in PIO mode even the device could use DMA. For the linux kernel I have added this patch: https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=abf8f2b877846573f0e6498883fe43f08be5696d What would be the best solution in seabios to use PIO for broken devices and DMA for the others? The biggest problem is that the device supports DMA but due a missing resister I breaks in DMA. thanks -- Christian Gmeiner, MSc
Hi Gerd, I just pulled your git branch at "git://git.kraxel.org/seabios 1.7.2-kraxel" into the seabios 1.7.2-stable branch. (I know my timing isn't great.) I did not pull the pvpanic changes as I'm reluctant to put a new feature and change the acpi tables in a stable release. If there are no other pressing changes, I'll tag 1.7.2.2. -Kevin
I'm not sure what happened yet, but I noticed that current seabios
does not build with 20130214-32 version of iasl.
Apparently, the listing file (-l) produced now does not contain
any comments from the original source, so tools/acpi_extract.py
produce nothing from these files.
Here's the diff between listing produced by two versions of iasl
for ssdt-pcihp:
----------------
--- out/ssdt-pcihp.lst-20100528 2013-05-09 17:55:43.872160687 +0400
+++ out/ssdt-pcihp.lst-20130214-32 2013-05-09 17:57:45.222803783 +0400
<at> <at> -1,84 +1,72 <at> <at>
Intel ACPI Component Architecture
-ASL Optimizing Compiler version 20100528 [Jul 2 2010]
-Copyright (c) 2000 - 2010 Intel Corporation
-Supports ACPI Specification Revision 4.0a
-
-Compilation of "out/ssdt-pcihp.dsl.i" - Thu May 9 17:55:43 2013
-
- 1....
- 2..../* ACPI_EXTRACT_ALL_CODE ssdp_pcihp_aml */
- 3....
- 4....DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1)
-
-00000000....53 53 44 54 58 00 00 00 "SSDTX..."
-00000008....01 77 42 58 50 43 00 00 ".wBXPC.."
-00000010....42 58 53 53 44 54 50 43 "BXSSDTPC"
-00000018....01 00 00 00 49 4E 54 4C "....INTL"
-00000020....28 05 10 20 ............ "(.. "
-
- 5....{
- 6.... External(\_SB.PCI0, DeviceObj)
- 7.... External(\_SB.PCI0.PCEJ, MethodObj)
- 8.... Scope(\_SB.PCI0) {
-
-00000024....10 33 5C 2E 5F 53 42 5F ".3\._SB_"
-0000002C....50 43 49 30 ............ "PCI0"
-
- 9....
- 10..../* ACPI_EXTRACT_DEVICE_START ssdt_pcihp_start */
- 11....
- 12....
- 13..../* ACPI_EXTRACT_DEVICE_END ssdt_pcihp_end */
- 14....
- 15....
- 16..../* ACPI_EXTRACT_DEVICE_STRING ssdt_pcihp_name */
- 17....
- 18.... Device(SAA) {
-
-00000030....5B 82 26 53 41 41 5F ... "[.&SAA_"
-
- 19....
- 20..../* ACPI_EXTRACT_NAME_BYTE_CONST ssdt_pcihp_id */
- 21....
- 22.... Name(_SUN, 0xAA)
-
-00000037....08 5F 53 55 4E 0A AA ... "._SUN.."
-
- 23....
- 24..../* ACPI_EXTRACT_NAME_DWORD_CONST ssdt_pcihp_adr */
- 25....
- 26.... Name(_ADR, 0xAA0000)
-
-0000003E....08 5F 41 44 52 0C 00 00 "._ADR..."
-00000046....AA 00 .................. ".."
-
- 27....
- 28..../* ACPI_EXTRACT_METHOD_STRING ssdt_pcihp_ej0 */
- 29....
- 30.... Method(_EJ0, 1) {
-
-00000048....14 0F 5F 45 4A 30 01 ... ".._EJ0."
-
- 31.... Return (PCEJ(_SUN))
-
-0000004F....A4 ..................... "."
-00000050....50 43 45 4A 5F 53 55 4E "PCEJ_SUN"
- 32.... }
- 33.... }
- 34.... }
- 35....}
- 36....
+ASL Optimizing Compiler version 20130214-32 [Apr 6 2013]
+Copyright (c) 2000 - 2013 Intel Corporation
+
+Compilation of "out/ssdt-pcihp.dsl.i" - Thu May 9 17:57:45 2013
+
+ 4: DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1)
+
+00000000: 53 53 44 54 58 00 00 00 "SSDTX..."
+00000008: 01 8B 42 58 50 43 00 00 "..BXPC.."
+00000010: 42 58 53 53 44 54 50 43 "BXSSDTPC"
+00000018: 01 00 00 00 49 4E 54 4C "....INTL"
+00000020: 14 02 13 20 ............ "... "
+
+ 5: {
+ 6: External(\_SB.PCI0, DeviceObj)
+ 7: External(\_SB.PCI0.PCEJ, MethodObj)
+ 8: Scope(\_SB.PCI0) {
+
+00000024: 10 33 5C 2E 5F 53 42 5F ".3\._SB_"
+0000002C: 50 43 49 30 ............ "PCI0"
+
+ 18: Device(SAA) {
+
+00000030: 5B 82 26 53 41 41 5F ... "[.&SAA_"
+
+ 22: Name(_SUN, 0xAA)
+
+00000037: 08 5F 53 55 4E 0A AA ... "._SUN.."
+
+ 26: Name(_ADR, 0xAA0000)
+
+0000003E: 08 5F 41 44 52 0C 00 00 "._ADR..."
+00000046: AA 00 .................. ".."
+
+ 30: Method(_EJ0, 1) {
+
+00000048: 14 0F 5F 45 4A 30 01 ... ".._EJ0."
+
+ 31: Return (PCEJ(_SUN))
+
+[****iasl****]
+out/ssdt-pcihp.dsl.i 31: Return (PCEJ(_SUN))
+Warning 1104 - ^ Reserved method should not return a value (_EJ0)
+
+
+
+0000004F: A4 ..................... "."
+00000050: 50 43 45 4A 5F 53 55 4E "PCEJ_SUN"
+ 32: }
+ 33: }
+ 34: }
+ 35: }
+
Summary of errors and warnings
+out/ssdt-pcihp.dsl.i 31: Return (PCEJ(_SUN))
+Warning 1104 - ^ Reserved method should not return a value (_EJ0)
-ASL Optimizing Compiler version 20100528 [Jul 2 2010]
-ASL Input: out/ssdt-pcihp.dsl.i - 37 lines, 767 bytes, 6 keywords
-AML Output: out/ssdt-pcihp.aml - 88 bytes, 5 named objects, 1 executable opcodes
+ASL Optimizing Compiler version 20130214-32 [Apr 6 2013]
-Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 0 Optimizations
+ASL Input: out/ssdt-pcihp.dsl.i - 37 lines, 359 bytes, 6 keywords
+AML Output: out/ssdt-pcihp.aml - 88 bytes, 5 named objects, 1 executable opcodes
+Listing File: out/ssdt-pcihp.lst - 2016 bytes
+Hex Dump: out/ssdt-pcihp.hex - 228 bytes
+Compilation complete. 0 Errors, 1 Warnings, 0 Remarks, 0 Optimizations
----------------
As you can see, there's no code comments anymore, so
nothing to output by acpi_extract.py
I haven't digged further yet -- just a heads-up for now.
Thanks,
/mjt
[Resending after being subscribed to the list]
I'm not sure what happened yet, but I noticed that current seabios
does not build with 20130214-32 version of iasl.
Apparently, the listing file (-l) produced now does not contain
any comments from the original source, so tools/acpi_extract.py
produce nothing from these files.
Here's the diff between listing produced by two versions of iasl
for ssdt-pcihp:
----------------
--- out/ssdt-pcihp.lst-20100528 2013-05-09 17:55:43.872160687 +0400
+++ out/ssdt-pcihp.lst-20130214-32 2013-05-09 17:57:45.222803783 +0400
<at> <at> -1,84 +1,72 <at> <at>
Intel ACPI Component Architecture
-ASL Optimizing Compiler version 20100528 [Jul 2 2010]
-Copyright (c) 2000 - 2010 Intel Corporation
-Supports ACPI Specification Revision 4.0a
-
-Compilation of "out/ssdt-pcihp.dsl.i" - Thu May 9 17:55:43 2013
-
- 1....
- 2..../* ACPI_EXTRACT_ALL_CODE ssdp_pcihp_aml */
- 3....
- 4....DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1)
-
-00000000....53 53 44 54 58 00 00 00 "SSDTX..."
-00000008....01 77 42 58 50 43 00 00 ".wBXPC.."
-00000010....42 58 53 53 44 54 50 43 "BXSSDTPC"
-00000018....01 00 00 00 49 4E 54 4C "....INTL"
-00000020....28 05 10 20 ............ "(.. "
-
- 5....{
- 6.... External(\_SB.PCI0, DeviceObj)
- 7.... External(\_SB.PCI0.PCEJ, MethodObj)
- 8.... Scope(\_SB.PCI0) {
-
-00000024....10 33 5C 2E 5F 53 42 5F ".3\._SB_"
-0000002C....50 43 49 30 ............ "PCI0"
-
- 9....
- 10..../* ACPI_EXTRACT_DEVICE_START ssdt_pcihp_start */
- 11....
- 12....
- 13..../* ACPI_EXTRACT_DEVICE_END ssdt_pcihp_end */
- 14....
- 15....
- 16..../* ACPI_EXTRACT_DEVICE_STRING ssdt_pcihp_name */
- 17....
- 18.... Device(SAA) {
-
-00000030....5B 82 26 53 41 41 5F ... "[.&SAA_"
-
- 19....
- 20..../* ACPI_EXTRACT_NAME_BYTE_CONST ssdt_pcihp_id */
- 21....
- 22.... Name(_SUN, 0xAA)
-
-00000037....08 5F 53 55 4E 0A AA ... "._SUN.."
-
- 23....
- 24..../* ACPI_EXTRACT_NAME_DWORD_CONST ssdt_pcihp_adr */
- 25....
- 26.... Name(_ADR, 0xAA0000)
-
-0000003E....08 5F 41 44 52 0C 00 00 "._ADR..."
-00000046....AA 00 .................. ".."
-
- 27....
- 28..../* ACPI_EXTRACT_METHOD_STRING ssdt_pcihp_ej0 */
- 29....
- 30.... Method(_EJ0, 1) {
-
-00000048....14 0F 5F 45 4A 30 01 ... ".._EJ0."
-
- 31.... Return (PCEJ(_SUN))
-
-0000004F....A4 ..................... "."
-00000050....50 43 45 4A 5F 53 55 4E "PCEJ_SUN"
- 32.... }
- 33.... }
- 34.... }
- 35....}
- 36....
+ASL Optimizing Compiler version 20130214-32 [Apr 6 2013]
+Copyright (c) 2000 - 2013 Intel Corporation
+
+Compilation of "out/ssdt-pcihp.dsl.i" - Thu May 9 17:57:45 2013
+
+ 4: DefinitionBlock ("ssdt-pcihp.aml", "SSDT", 0x01, "BXPC", "BXSSDTPCIHP", 0x1)
+
+00000000: 53 53 44 54 58 00 00 00 "SSDTX..."
+00000008: 01 8B 42 58 50 43 00 00 "..BXPC.."
+00000010: 42 58 53 53 44 54 50 43 "BXSSDTPC"
+00000018: 01 00 00 00 49 4E 54 4C "....INTL"
+00000020: 14 02 13 20 ............ "... "
+
+ 5: {
+ 6: External(\_SB.PCI0, DeviceObj)
+ 7: External(\_SB.PCI0.PCEJ, MethodObj)
+ 8: Scope(\_SB.PCI0) {
+
+00000024: 10 33 5C 2E 5F 53 42 5F ".3\._SB_"
+0000002C: 50 43 49 30 ............ "PCI0"
+
+ 18: Device(SAA) {
+
+00000030: 5B 82 26 53 41 41 5F ... "[.&SAA_"
+
+ 22: Name(_SUN, 0xAA)
+
+00000037: 08 5F 53 55 4E 0A AA ... "._SUN.."
+
+ 26: Name(_ADR, 0xAA0000)
+
+0000003E: 08 5F 41 44 52 0C 00 00 "._ADR..."
+00000046: AA 00 .................. ".."
+
+ 30: Method(_EJ0, 1) {
+
+00000048: 14 0F 5F 45 4A 30 01 ... ".._EJ0."
+
+ 31: Return (PCEJ(_SUN))
+
+[****iasl****]
+out/ssdt-pcihp.dsl.i 31: Return (PCEJ(_SUN))
+Warning 1104 - ^ Reserved method should not return a value (_EJ0)
+
+
+
+0000004F: A4 ..................... "."
+00000050: 50 43 45 4A 5F 53 55 4E "PCEJ_SUN"
+ 32: }
+ 33: }
+ 34: }
+ 35: }
+
Summary of errors and warnings
+out/ssdt-pcihp.dsl.i 31: Return (PCEJ(_SUN))
+Warning 1104 - ^ Reserved method should not return a value (_EJ0)
-ASL Optimizing Compiler version 20100528 [Jul 2 2010]
-ASL Input: out/ssdt-pcihp.dsl.i - 37 lines, 767 bytes, 6 keywords
-AML Output: out/ssdt-pcihp.aml - 88 bytes, 5 named objects, 1 executable opcodes
+ASL Optimizing Compiler version 20130214-32 [Apr 6 2013]
-Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 0 Optimizations
+ASL Input: out/ssdt-pcihp.dsl.i - 37 lines, 359 bytes, 6 keywords
+AML Output: out/ssdt-pcihp.aml - 88 bytes, 5 named objects, 1 executable opcodes
+Listing File: out/ssdt-pcihp.lst - 2016 bytes
+Hex Dump: out/ssdt-pcihp.hex - 228 bytes
+Compilation complete. 0 Errors, 1 Warnings, 0 Remarks, 0 Optimizations
----------------
As you can see, there's no code comments anymore, so
nothing to output by acpi_extract.py
I haven't digged further yet -- just a heads-up for now.
Thanks,
/mjt
I know qemu-kvm use seabios as pc bios.i just want let vm created by qemu-kvm
show a custom JPEG image during bootup. How to modify the file bios.bin?
I see the following command on coreboot website，but i can't find coreboot.rom file in /usr/share/qemu-kvm/ . maybe qemu-kvm use non-coreboot uses,How do I do to reach my goal？
./build/cbfstool build/coreboot.rom add -f /path/to/image.jpg -n bootsplash.jpg -t raw_______________________________________________ SeaBIOS mailing list SeaBIOS <at> seabios.org http://www.seabios.org/mailman/listinfo/seabios
Make 64 bit window detection logic a bit cleaner:
don't hardcode 0 address as invalid, instead
check start < end.
Signed-off-by: Michael S. Tsirkin <mst <at> redhat.com>
---
src/acpi.c | 2 +-
src/pciinit.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/acpi.c b/src/acpi.c
index b03b2ba..1037093 100644
--- a/src/acpi.c
+++ b/src/acpi.c
<at> <at> -355,7 +355,7 <at> <at> build_ssdt(void)
// store pci io windows
*(u32*)&ssdt_ptr[acpi_pci32_start[0]] = cpu_to_le32(pcimem_start);
*(u32*)&ssdt_ptr[acpi_pci32_end[0]] = cpu_to_le32(pcimem_end - 1);
- if (pcimem64_start) {
+ if (pcimem64_start < pcimem64_end) {
ssdt_ptr[acpi_pci64_valid[0]] = 1;
*(u64*)&ssdt_ptr[acpi_pci64_start[0]] = cpu_to_le64(pcimem64_start);
*(u64*)&ssdt_ptr[acpi_pci64_end[0]] = cpu_to_le64(pcimem64_end - 1);
diff --git a/src/pciinit.c b/src/pciinit.c
index a4a5bf5..fdf1362 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
<at> <at> -818,7 +818,7 <at> <at> static void pci_bios_map_devices(struct pci_bus *busses, struct pci_mem *mem)
pci_region_map_entries(busses, &r64_pref);
} else if (!mem) {
// no bars mapped high -> drop 64bit window (see dsdt)
- pcimem64_start = 0;
+ pcimem64_end = pcimem64_start = 0;
}
// Map regions on each device.
int bus;
--
--
MST
Load memory window setup for pci from host.
This makes it possible for host to make sure
setup matches hardware exactly: especially important
for when ACPI tables are loaded from host.
This will also make it easier to add more chipsets
down the road.
Signed-off-by: Michael S. Tsirkin <mst <at> redhat.com>
---
Changes from v1:
- fix bug in 64 bit range check
- address Kevin's comments:
move file load into pciinit.c
dont reorder initialization
sizeof style fix
src/pciinit.c | 91 ++++++++++++++++++++++++++++++++++++++++++++++++-----------
1 file changed, 75 insertions(+), 16 deletions(-)
diff --git a/src/pciinit.c b/src/pciinit.c
index bb9355f..a4a5bf5 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
<at> <at> -13,6 +13,7 <at> <at>
#include "config.h" // CONFIG_*
#include "memmap.h" // add_e820
#include "paravirt.h" // RamSize
+#include "byteorder.h" // le64_to_cpu
#include "dev-q35.h"
/* PM Timer ticks per second (HZ) */
<at> <at> -61,6 +62,13 <at> <at> struct pci_bus {
struct pci_device *bus_dev;
};
+struct pci_mem {
+ u64 start32;
+ u64 end32;
+ u64 start64;
+ u64 end64;
+};
+
static u32 pci_bar(struct pci_device *pci, int region_num)
{
if (region_num != PCI_ROM_SLOT) {
<at> <at> -361,6 +369,8 <at> <at> static void pci_enable_default_vga(void)
void i440fx_mem_addr_setup(struct pci_device *dev, void *arg)
{
+ if (arg)
+ /* use supplied memory */;
if (RamSize <= 0x80000000)
pcimem_start = 0x80000000;
else if (RamSize <= 0xc0000000)
<at> <at> -383,8 +393,9 <at> <at> void mch_mem_addr_setup(struct pci_device *dev, void *arg)
pci_config_writel(bdf, Q35_HOST_BRIDGE_PCIEXBAR, lower);
add_e820(addr, size, E820_RESERVED);
- /* setup pci i/o window (above mmconfig) */
- pcimem_start = addr + size;
+ /* unless done already, setup pci i/o window (above mmconfig) */
+ if (!arg)
+ pcimem_start = addr + size;
pci_slot_get_irq = mch_pci_slot_get_irq;
}
<at> <at> -397,11 +408,11 <at> <at> static const struct pci_device_id pci_platform_tbl[] = {
PCI_DEVICE_END
};
-static void pci_bios_init_platform(void)
+static void pci_bios_init_platform(struct pci_mem *mem)
{
struct pci_device *pci;
foreachpci(pci) {
- pci_init_device(pci_platform_tbl, pci, NULL);
+ pci_init_device(pci_platform_tbl, pci, mem);
}
}
<at> <at> -762,10 +773,14 <at> <at> static void pci_region_map_entries(struct pci_bus *busses, struct pci_region *r)
}
}
-static void pci_bios_map_devices(struct pci_bus *busses)
+static void pci_bios_map_devices(struct pci_bus *busses, struct pci_mem *mem)
{
if (pci_bios_init_root_regions(busses)) {
struct pci_region r64_mem, r64_pref;
+
+ if (mem && mem->start64 >= mem->end64)
+ panic("PCI: out of 32bit address space\n");
+
r64_mem.list = NULL;
r64_pref.list = NULL;
pci_region_migrate_64bit_entries(&busses[0].r[PCI_REGION_TYPE_MEM],
<at> <at> -781,14 +796,27 <at> <at> static void pci_bios_map_devices(struct pci_bus *busses)
u64 align_mem = pci_region_align(&r64_mem);
u64 align_pref = pci_region_align(&r64_pref);
- r64_mem.base = ALIGN(0x100000000LL + RamSizeOver4G, align_mem);
- r64_pref.base = ALIGN(r64_mem.base + sum_mem, align_pref);
- pcimem64_start = r64_mem.base;
- pcimem64_end = r64_pref.base + sum_pref;
+ if (mem) {
+ /*
+ * Non prefetcheable memory at start of the window,
+ * prefetcheable memory at the end.
+ * This way OS has the maximum flexibility for
+ * allocating the rest of the memory.
+ */
+ r64_mem.base = ALIGN(mem->start64, align_mem);
+ r64_pref.base = ALIGN_DOWN(mem->end64 - sum_pref + 1, align_pref);
+ if (sum_pref && r64_pref.base < r64_mem.base + sum_mem)
+ panic("PCI: out of 64bit address space\n");
+ } else {
+ r64_mem.base = ALIGN(0x100000000LL + RamSizeOver4G, align_mem);
+ r64_pref.base = ALIGN(r64_mem.base + sum_mem, align_pref);
+ pcimem64_start = r64_mem.base;
+ pcimem64_end = r64_pref.base + sum_pref;
+ }
pci_region_map_entries(busses, &r64_mem);
pci_region_map_entries(busses, &r64_pref);
- } else {
+ } else if (!mem) {
// no bars mapped high -> drop 64bit window (see dsdt)
pcimem64_start = 0;
}
<at> <at> -801,11 +829,28 <at> <at> static void pci_bios_map_devices(struct pci_bus *busses)
}
}
+static
+struct pci_mem *pci_mem_get(void)
+{
+ int psize;
+ struct pci_mem *mem = romfile_loadfile("etc/pci-info", &psize);
+ if (!mem)
+ return NULL;
+ if (psize < sizeof(*mem)) {
+ free(mem);
+ return NULL;
+ }
+ mem->start32 = le64_to_cpu(mem->start32);
+ mem->end32 = le64_to_cpu(mem->end32);
+ mem->start64 = le64_to_cpu(mem->start64);
+ mem->end64 = le64_to_cpu(mem->end64);
+ return mem;
+}
+
/****************************************************************
* Main setup code
****************************************************************/
-
void
pci_setup(void)
{
<at> <at> -823,25 +868,39 <at> <at> pci_setup(void)
dprintf(1, "=== PCI device probing ===\n");
pci_probe_devices();
- pcimem_start = RamSize;
- pci_bios_init_platform();
+ struct pci_mem *mem = pci_mem_get();
+
+ if (mem) {
+ pcimem_start = mem->start32;
+ pcimem_end = mem->end32;
+ pcimem64_start = mem->start64;
+ pcimem64_end = mem->end64;
+ } else {
+ pcimem_start = RamSize;
+ }
+
+ pci_bios_init_platform(mem);
dprintf(1, "=== PCI new allocation pass #1 ===\n");
struct pci_bus *busses = malloc_tmp(sizeof(*busses) * (MaxPCIBus + 1));
if (!busses) {
warn_noalloc();
- return;
+ goto done;
}
memset(busses, 0, sizeof(*busses) * (MaxPCIBus + 1));
if (pci_bios_check_devices(busses))
- return;
+ goto done;
dprintf(1, "=== PCI new allocation pass #2 ===\n");
- pci_bios_map_devices(busses);
+ pci_bios_map_devices(busses, mem);
pci_bios_init_devices();
free(busses);
pci_enable_default_vga();
+
+done:
+ if (mem)
+ free(mem);
}
--
--
MST
This makes it possible to load pci window data from host, when running on qemu. This makes it possible for host to make sure setup matches hardware exactly: especially important for when ACPI tables are loaded from host. This will also make it easier to add more chipsets down the road. Michael S. Tsirkin (2): paravirt: init qemu cfg earlier pci: load memory window setup from host src/paravirt.c | 27 ++++++++++++++++++++++++++- src/pciinit.c | 54 ++++++++++++++++++++++++++++++++++++++++-------------- src/post.c | 1 - src/util.h | 8 +++++++- 4 files changed, 73 insertions(+), 17 deletions(-) -- -- MST
If SeaBIOS is run as a payload via coreboot (and presumably as a
CSM), then it's possible the keyboard or mouse will still be
enabled. This can lead to data being queued even after the flush
function attempts to clear the queue.
Disabling the keyboard/mouse prior to flushing is pretty standard
in DOS programming so it's not surprising that it's needed here.
I believe this problem manifests with the Chromebook Pixel. People
have reported that sometimes the 'ESC to Select Boot Devices'
doesn't work. I can reproduce this faithfully by holding 'Ctrl-L'
in the firmware screen during SeaBIOS initialization.
I can't test this fix on an actual Pixel because I don't know how
to update SeaBIOS but I have tested the patch under QEMU.
Signed-off-by: Anthony Liguori <aliguori <at> us.ibm.com>
---
src/ps2port.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/src/ps2port.c b/src/ps2port.c
index 9b760fd..2169171 100644
--- a/src/ps2port.c
+++ b/src/ps2port.c
<at> <at> -55,6 +55,12 <at> <at> static int
i8042_flush(void)
{
dprintf(7, "i8042_flush\n");
+
+ /* Disable the keyboard and mouse to prevent additional data from
+ * being queued. */
+ outb(0xad, PORT_PS2_STATUS);
+ outb(0xa7, PORT_PS2_STATUS);
+
int i;
for (i=0; i<I8042_BUFFER_SIZE; i++) {
u8 status = inb(PORT_PS2_STATUS);
--
--
1.8.0
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